ARMGenMCCodeEmitter.inc source code [llvm/build/lib/Target/ARM/ARMGenMCCodeEmitter.inc]

1	/===- TableGen'erated file -------------------------------------- C++ --===\
2	\| \|
3	\| Machine Code Emitter \|
4	\| \|
5	\| Automatically generated file, do not edit! \|
6	\| \|
7	\===----------------------------------------------------------------------===/
8
9	uint64_t ARMMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
10	SmallVectorImpl<MCFixup> &Fixups,
11	const MCSubtargetInfo &STI) const {
12	static const uint64_t InstBits[] = {
13	UINT64_C(`0`),
14	UINT64_C(`0`),
15	UINT64_C(`0`),
16	UINT64_C(`0`),
17	UINT64_C(`0`),
18	UINT64_C(`0`),
19	UINT64_C(`0`),
20	UINT64_C(`0`),
21	UINT64_C(`0`),
22	UINT64_C(`0`),
23	UINT64_C(`0`),
24	UINT64_C(`0`),
25	UINT64_C(`0`),
26	UINT64_C(`0`),
27	UINT64_C(`0`),
28	UINT64_C(`0`),
29	UINT64_C(`0`),
30	UINT64_C(`0`),
31	UINT64_C(`0`),
32	UINT64_C(`0`),
33	UINT64_C(`0`),
34	UINT64_C(`0`),
35	UINT64_C(`0`),
36	UINT64_C(`0`),
37	UINT64_C(`0`),
38	UINT64_C(`0`),
39	UINT64_C(`0`),
40	UINT64_C(`0`),
41	UINT64_C(`0`),
42	UINT64_C(`0`),
43	UINT64_C(`0`),
44	UINT64_C(`0`),
45	UINT64_C(`0`),
46	UINT64_C(`0`),
47	UINT64_C(`0`),
48	UINT64_C(`0`),
49	UINT64_C(`0`),
50	UINT64_C(`0`),
51	UINT64_C(`0`),
52	UINT64_C(`0`),
53	UINT64_C(`0`),
54	UINT64_C(`0`),
55	UINT64_C(`0`),
56	UINT64_C(`0`),
57	UINT64_C(`0`),
58	UINT64_C(`0`),
59	UINT64_C(`0`),
60	UINT64_C(`0`),
61	UINT64_C(`0`),
62	UINT64_C(`0`),
63	UINT64_C(`0`),
64	UINT64_C(`0`),
65	UINT64_C(`0`),
66	UINT64_C(`0`),
67	UINT64_C(`0`),
68	UINT64_C(`0`),
69	UINT64_C(`0`),
70	UINT64_C(`0`),
71	UINT64_C(`0`),
72	UINT64_C(`0`),
73	UINT64_C(`0`),
74	UINT64_C(`0`),
75	UINT64_C(`0`),
76	UINT64_C(`0`),
77	UINT64_C(`0`),
78	UINT64_C(`0`),
79	UINT64_C(`0`),
80	UINT64_C(`0`),
81	UINT64_C(`0`),
82	UINT64_C(`0`),
83	UINT64_C(`0`),
84	UINT64_C(`0`),
85	UINT64_C(`0`),
86	UINT64_C(`0`),
87	UINT64_C(`0`),
88	UINT64_C(`0`),
89	UINT64_C(`0`),
90	UINT64_C(`0`),
91	UINT64_C(`0`),
92	UINT64_C(`0`),
93	UINT64_C(`0`),
94	UINT64_C(`0`),
95	UINT64_C(`0`),
96	UINT64_C(`0`),
97	UINT64_C(`0`),
98	UINT64_C(`0`),
99	UINT64_C(`0`),
100	UINT64_C(`0`),
101	UINT64_C(`0`),
102	UINT64_C(`0`),
103	UINT64_C(`0`),
104	UINT64_C(`0`),
105	UINT64_C(`0`),
106	UINT64_C(`0`),
107	UINT64_C(`0`),
108	UINT64_C(`0`),
109	UINT64_C(`0`),
110	UINT64_C(`0`),
111	UINT64_C(`0`),
112	UINT64_C(`0`),
113	UINT64_C(`0`),
114	UINT64_C(`0`),
115	UINT64_C(`0`),
116	UINT64_C(`0`),
117	UINT64_C(`0`),
118	UINT64_C(`0`),
119	UINT64_C(`0`),
120	UINT64_C(`0`),
121	UINT64_C(`0`),
122	UINT64_C(`0`),
123	UINT64_C(`0`),
124	UINT64_C(`0`),
125	UINT64_C(`0`),
126	UINT64_C(`0`),
127	UINT64_C(`0`),
128	UINT64_C(`0`),
129	UINT64_C(`0`),
130	UINT64_C(`0`),
131	UINT64_C(`0`),
132	UINT64_C(`0`),
133	UINT64_C(`0`),
134	UINT64_C(`0`),
135	UINT64_C(`0`),
136	UINT64_C(`0`),
137	UINT64_C(`0`),
138	UINT64_C(`0`),
139	UINT64_C(`0`),
140	UINT64_C(`0`),
141	UINT64_C(`0`),
142	UINT64_C(`0`),
143	UINT64_C(`0`),
144	UINT64_C(`0`),
145	UINT64_C(`0`),
146	UINT64_C(`0`),
147	UINT64_C(`0`),
148	UINT64_C(`0`),
149	UINT64_C(`0`),
150	UINT64_C(`0`),
151	UINT64_C(`0`),
152	UINT64_C(`0`),
153	UINT64_C(`0`),
154	UINT64_C(`0`),
155	UINT64_C(`0`),
156	UINT64_C(`0`),
157	UINT64_C(`0`),
158	UINT64_C(`0`),
159	UINT64_C(`0`),
160	UINT64_C(`0`),
161	UINT64_C(`0`),
162	UINT64_C(`0`),
163	UINT64_C(`0`),
164	UINT64_C(`0`),
165	UINT64_C(`0`),
166	UINT64_C(`0`),
167	UINT64_C(`0`),
168	UINT64_C(`0`),
169	UINT64_C(`0`),
170	UINT64_C(`0`),
171	UINT64_C(`0`),
172	UINT64_C(`0`),
173	UINT64_C(`0`),
174	UINT64_C(`0`),
175	UINT64_C(`0`),
176	UINT64_C(`0`),
177	UINT64_C(`0`),
178	UINT64_C(`0`),
179	UINT64_C(`0`),
180	UINT64_C(`0`),
181	UINT64_C(`0`),
182	UINT64_C(`0`),
183	UINT64_C(`0`),
184	UINT64_C(`0`),
185	UINT64_C(`0`),
186	UINT64_C(`0`),
187	UINT64_C(`0`),
188	UINT64_C(`0`),
189	UINT64_C(`0`),
190	UINT64_C(`0`),
191	UINT64_C(`0`),
192	UINT64_C(`0`),
193	UINT64_C(`0`),
194	UINT64_C(`0`),
195	UINT64_C(`0`),
196	UINT64_C(`0`),
197	UINT64_C(`0`),
198	UINT64_C(`0`),
199	UINT64_C(`0`),
200	UINT64_C(`0`),
201	UINT64_C(`0`),
202	UINT64_C(`0`),
203	UINT64_C(`0`),
204	UINT64_C(`0`),
205	UINT64_C(`0`),
206	UINT64_C(`0`),
207	UINT64_C(`0`),
208	UINT64_C(`0`),
209	UINT64_C(`0`),
210	UINT64_C(`0`),
211	UINT64_C(`0`),
212	UINT64_C(`0`),
213	UINT64_C(`0`),
214	UINT64_C(`0`),
215	UINT64_C(`0`),
216	UINT64_C(`0`),
217	UINT64_C(`0`),
218	UINT64_C(`0`),
219	UINT64_C(`0`),
220	UINT64_C(`0`),
221	UINT64_C(`0`),
222	UINT64_C(`0`),
223	UINT64_C(`0`),
224	UINT64_C(`0`),
225	UINT64_C(`0`),
226	UINT64_C(`0`),
227	UINT64_C(`0`),
228	UINT64_C(`0`),
229	UINT64_C(`0`),
230	UINT64_C(`0`),
231	UINT64_C(`0`),
232	UINT64_C(`0`),
233	UINT64_C(`0`),
234	UINT64_C(`0`),
235	UINT64_C(`0`),
236	UINT64_C(`0`),
237	UINT64_C(`0`),
238	UINT64_C(`0`),
239	UINT64_C(`0`),
240	UINT64_C(`0`),
241	UINT64_C(`0`),
242	UINT64_C(`0`),
243	UINT64_C(`0`),
244	UINT64_C(`0`),
245	UINT64_C(`0`),
246	UINT64_C(`0`),
247	UINT64_C(`0`),
248	UINT64_C(`0`),
249	UINT64_C(`0`),
250	UINT64_C(`0`),
251	UINT64_C(`0`),
252	UINT64_C(`0`),
253	UINT64_C(`0`),
254	UINT64_C(`0`),
255	UINT64_C(`0`),
256	UINT64_C(`0`),
257	UINT64_C(`0`),
258	UINT64_C(`0`),
259	UINT64_C(`0`),
260	UINT64_C(`0`),
261	UINT64_C(`0`),
262	UINT64_C(`0`),
263	UINT64_C(`0`),
264	UINT64_C(`0`),
265	UINT64_C(`0`),
266	UINT64_C(`0`),
267	UINT64_C(`0`),
268	UINT64_C(`0`),
269	UINT64_C(`0`),
270	UINT64_C(`0`),
271	UINT64_C(`0`),
272	UINT64_C(`0`),
273	UINT64_C(`0`),
274	UINT64_C(`0`),
275	UINT64_C(`0`),
276	UINT64_C(`0`),
277	UINT64_C(`0`),
278	UINT64_C(`0`),
279	UINT64_C(`0`),
280	UINT64_C(`0`),
281	UINT64_C(`0`),
282	UINT64_C(`0`),
283	UINT64_C(`0`),
284	UINT64_C(`0`),
285	UINT64_C(`0`),
286	UINT64_C(`0`),
287	UINT64_C(`0`),
288	UINT64_C(`0`),
289	UINT64_C(`0`),
290	UINT64_C(`0`),
291	UINT64_C(`0`),
292	UINT64_C(`0`),
293	UINT64_C(`0`),
294	UINT64_C(`0`),
295	UINT64_C(`0`),
296	UINT64_C(`0`),
297	UINT64_C(`0`),
298	UINT64_C(`0`),
299	UINT64_C(`0`),
300	UINT64_C(`0`),
301	UINT64_C(`0`),
302	UINT64_C(`0`),
303	UINT64_C(`0`),
304	UINT64_C(`0`),
305	UINT64_C(`0`),
306	UINT64_C(`0`),
307	UINT64_C(`0`),
308	UINT64_C(`0`),
309	UINT64_C(`0`),
310	UINT64_C(`0`),
311	UINT64_C(`0`),
312	UINT64_C(`0`),
313	UINT64_C(`0`),
314	UINT64_C(`0`),
315	UINT64_C(`0`),
316	UINT64_C(`0`),
317	UINT64_C(`0`),
318	UINT64_C(`0`),
319	UINT64_C(`0`),
320	UINT64_C(`0`),
321	UINT64_C(`0`),
322	UINT64_C(`0`),
323	UINT64_C(`0`),
324	UINT64_C(`0`),
325	UINT64_C(`0`),
326	UINT64_C(`0`),
327	UINT64_C(`0`),
328	UINT64_C(`0`),
329	UINT64_C(`0`),
330	UINT64_C(`0`),
331	UINT64_C(`0`),
332	UINT64_C(`0`),
333	UINT64_C(`0`),
334	UINT64_C(`0`),
335	UINT64_C(`0`),
336	UINT64_C(`0`),
337	UINT64_C(`0`),
338	UINT64_C(`0`),
339	UINT64_C(`0`),
340	UINT64_C(`0`),
341	UINT64_C(`0`),
342	UINT64_C(`0`),
343	UINT64_C(`0`),
344	UINT64_C(`0`),
345	UINT64_C(`0`),
346	UINT64_C(`0`),
347	UINT64_C(`0`),
348	UINT64_C(`0`),
349	UINT64_C(`0`),
350	UINT64_C(`0`),
351	UINT64_C(`0`),
352	UINT64_C(`0`),
353	UINT64_C(`0`),
354	UINT64_C(`0`),
355	UINT64_C(`0`),
356	UINT64_C(`0`),
357	UINT64_C(`0`),
358	UINT64_C(`0`),
359	UINT64_C(`0`),
360	UINT64_C(`0`),
361	UINT64_C(`0`),
362	UINT64_C(`0`),
363	UINT64_C(`0`),
364	UINT64_C(`0`),
365	UINT64_C(`0`),
366	UINT64_C(`0`),
367	UINT64_C(`0`),
368	UINT64_C(`0`),
369	UINT64_C(`0`),
370	UINT64_C(`0`),
371	UINT64_C(`0`),
372	UINT64_C(`0`),
373	UINT64_C(`0`),
374	UINT64_C(`0`),
375	UINT64_C(`0`),
376	UINT64_C(`0`),
377	UINT64_C(`0`),
378	UINT64_C(`0`),
379	UINT64_C(`0`),
380	UINT64_C(`0`),
381	UINT64_C(`0`),
382	UINT64_C(`0`),
383	UINT64_C(`0`),
384	UINT64_C(`0`),
385	UINT64_C(`0`),
386	UINT64_C(`0`),
387	UINT64_C(`0`),
388	UINT64_C(`0`),
389	UINT64_C(`0`),
390	UINT64_C(`0`),
391	UINT64_C(`0`),
392	UINT64_C(`0`),
393	UINT64_C(`0`),
394	UINT64_C(`0`),
395	UINT64_C(`0`),
396	UINT64_C(`0`),
397	UINT64_C(`0`),
398	UINT64_C(`0`),
399	UINT64_C(`0`),
400	UINT64_C(`0`),
401	UINT64_C(`0`),
402	UINT64_C(`0`),
403	UINT64_C(`0`),
404	UINT64_C(`0`),
405	UINT64_C(`0`),
406	UINT64_C(`0`),
407	UINT64_C(`0`),
408	UINT64_C(`0`),
409	UINT64_C(`0`),
410	UINT64_C(`0`),
411	UINT64_C(`0`),
412	UINT64_C(`0`),
413	UINT64_C(`0`),
414	UINT64_C(`0`),
415	UINT64_C(`0`),
416	UINT64_C(`0`),
417	UINT64_C(`0`),
418	UINT64_C(`0`),
419	UINT64_C(`0`),
420	UINT64_C(`0`),
421	UINT64_C(`0`),
422	UINT64_C(`0`),
423	UINT64_C(`0`),
424	UINT64_C(`0`),
425	UINT64_C(`0`),
426	UINT64_C(`0`),
427	UINT64_C(`0`),
428	UINT64_C(`0`),
429	UINT64_C(`0`),
430	UINT64_C(`0`),
431	UINT64_C(`0`),
432	UINT64_C(`0`),
433	UINT64_C(`0`),
434	UINT64_C(`0`),
435	UINT64_C(`0`),
436	UINT64_C(`0`),
437	UINT64_C(`0`),
438	UINT64_C(`0`),
439	UINT64_C(`0`),
440	UINT64_C(`0`),
441	UINT64_C(`0`),
442	UINT64_C(`0`),
443	UINT64_C(`0`),
444	UINT64_C(`0`),
445	UINT64_C(`0`),
446	UINT64_C(`0`),
447	UINT64_C(`0`),
448	UINT64_C(`0`),
449	UINT64_C(`0`),
450	UINT64_C(`0`),
451	UINT64_C(`0`),
452	UINT64_C(`0`),
453	UINT64_C(`0`),
454	UINT64_C(`0`),
455	UINT64_C(`0`),
456	UINT64_C(`0`),
457	UINT64_C(`0`),
458	UINT64_C(`0`),
459	UINT64_C(`0`),
460	UINT64_C(`0`),
461	UINT64_C(`0`),
462	UINT64_C(`0`),
463	UINT64_C(`0`),
464	UINT64_C(`0`),
465	UINT64_C(`0`),
466	UINT64_C(`0`),
467	UINT64_C(`0`),
468	UINT64_C(`0`),
469	UINT64_C(`0`),
470	UINT64_C(`0`),
471	UINT64_C(`0`),
472	UINT64_C(`0`),
473	UINT64_C(`0`),
474	UINT64_C(`0`),
475	UINT64_C(`0`),
476	UINT64_C(`0`),
477	UINT64_C(`0`),
478	UINT64_C(`0`),
479	UINT64_C(`0`),
480	UINT64_C(`0`),
481	UINT64_C(`0`),
482	UINT64_C(`0`),
483	UINT64_C(`0`),
484	UINT64_C(`0`),
485	UINT64_C(`0`),
486	UINT64_C(`0`),
487	UINT64_C(`0`),
488	UINT64_C(`0`),
489	UINT64_C(`0`),
490	UINT64_C(`0`),
491	UINT64_C(`0`),
492	UINT64_C(`0`),
493	UINT64_C(`0`),
494	UINT64_C(`0`),
495	UINT64_C(`0`),
496	UINT64_C(`0`),
497	UINT64_C(`0`),
498	UINT64_C(`0`),
499	UINT64_C(`0`),
500	UINT64_C(`0`),
501	UINT64_C(`0`),
502	UINT64_C(`0`),
503	UINT64_C(`0`),
504	UINT64_C(`0`),
505	UINT64_C(`0`),
506	UINT64_C(`0`),
507	UINT64_C(`0`),
508	UINT64_C(`0`),
509	UINT64_C(`0`),
510	UINT64_C(`0`),
511	UINT64_C(`0`),
512	UINT64_C(`0`),
513	UINT64_C(`0`),
514	UINT64_C(`0`),
515	UINT64_C(`0`),
516	UINT64_C(`0`),
517	UINT64_C(`0`),
518	UINT64_C(`0`),
519	UINT64_C(`0`),
520	UINT64_C(`0`),
521	UINT64_C(`0`),
522	UINT64_C(`0`),
523	UINT64_C(`0`),
524	UINT64_C(`0`),
525	UINT64_C(`0`),
526	UINT64_C(`0`),
527	UINT64_C(`0`),
528	UINT64_C(`0`),
529	UINT64_C(`0`),
530	UINT64_C(`0`),
531	UINT64_C(`0`),
532	UINT64_C(`0`),
533	UINT64_C(`0`),
534	UINT64_C(`0`),
535	UINT64_C(`0`),
536	UINT64_C(`0`),
537	UINT64_C(`0`),
538	UINT64_C(`0`),
539	UINT64_C(`0`),
540	UINT64_C(`0`),
541	UINT64_C(`0`),
542	UINT64_C(`0`),
543	UINT64_C(`0`),
544	UINT64_C(`0`),
545	UINT64_C(`0`),
546	UINT64_C(`0`),
547	UINT64_C(`0`),
548	UINT64_C(`0`),
549	UINT64_C(`0`),
550	UINT64_C(`0`),
551	UINT64_C(`0`),
552	UINT64_C(`0`),
553	UINT64_C(`0`),
554	UINT64_C(`0`),
555	UINT64_C(`0`),
556	UINT64_C(`0`),
557	UINT64_C(`0`),
558	UINT64_C(`0`),
559	UINT64_C(`0`),
560	UINT64_C(`0`),
561	UINT64_C(`0`),
562	UINT64_C(`0`),
563	UINT64_C(`0`),
564	UINT64_C(`0`),
565	UINT64_C(`0`),
566	UINT64_C(`0`),
567	UINT64_C(`0`),
568	UINT64_C(`0`),
569	UINT64_C(`0`),
570	UINT64_C(`0`),
571	UINT64_C(`0`),
572	UINT64_C(`0`),
573	UINT64_C(`0`),
574	UINT64_C(`0`),
575	UINT64_C(`0`),
576	UINT64_C(`0`),
577	UINT64_C(`0`),
578	UINT64_C(`0`),
579	UINT64_C(`0`),
580	UINT64_C(`0`),
581	UINT64_C(`0`),
582	UINT64_C(`0`),
583	UINT64_C(`0`),
584	UINT64_C(`0`),
585	UINT64_C(`0`),
586	UINT64_C(`0`),
587	UINT64_C(`0`),
588	UINT64_C(`0`),
589	UINT64_C(`0`),
590	UINT64_C(`0`),
591	UINT64_C(`0`),
592	UINT64_C(`0`),
593	UINT64_C(`0`),
594	UINT64_C(`0`),
595	UINT64_C(`0`),
596	UINT64_C(`0`),
597	UINT64_C(`0`),
598	UINT64_C(`0`),
599	UINT64_C(`0`),
600	UINT64_C(`0`),
601	UINT64_C(`0`),
602	UINT64_C(`0`),
603	UINT64_C(`0`),
604	UINT64_C(`0`),
605	UINT64_C(`0`),
606	UINT64_C(`0`),
607	UINT64_C(`0`),
608	UINT64_C(`0`),
609	UINT64_C(`0`),
610	UINT64_C(`0`),
611	UINT64_C(`0`),
612	UINT64_C(`0`),
613	UINT64_C(`0`),
614	UINT64_C(`0`),
615	UINT64_C(`0`),
616	UINT64_C(`0`),
617	UINT64_C(`0`),
618	UINT64_C(`0`),
619	UINT64_C(`0`),
620	UINT64_C(`0`),
621	UINT64_C(`0`),
622	UINT64_C(`0`),
623	UINT64_C(`0`),
624	UINT64_C(`0`),
625	UINT64_C(`0`),
626	UINT64_C(`0`),
627	UINT64_C(`0`),
628	UINT64_C(`0`),
629	UINT64_C(`0`),
630	UINT64_C(`0`),
631	UINT64_C(`0`),
632	UINT64_C(`0`),
633	UINT64_C(`0`),
634	UINT64_C(`0`),
635	UINT64_C(`0`),
636	UINT64_C(`0`),
637	UINT64_C(`0`),
638	UINT64_C(`0`),
639	UINT64_C(`0`),
640	UINT64_C(`0`),
641	UINT64_C(`0`),
642	UINT64_C(`0`),
643	UINT64_C(`0`),
644	UINT64_C(`0`),
645	UINT64_C(`0`),
646	UINT64_C(`0`),
647	UINT64_C(`0`),
648	UINT64_C(`0`),
649	UINT64_C(`0`),
650	UINT64_C(`0`),
651	UINT64_C(`0`),
652	UINT64_C(`0`),
653	UINT64_C(`0`),
654	UINT64_C(`0`),
655	UINT64_C(`0`),
656	UINT64_C(`0`),
657	UINT64_C(`0`),
658	UINT64_C(`0`),
659	UINT64_C(`0`),
660	UINT64_C(`0`),
661	UINT64_C(`0`),
662	UINT64_C(`0`),
663	UINT64_C(`0`),
664	UINT64_C(`0`),
665	UINT64_C(`0`),
666	UINT64_C(`0`),
667	UINT64_C(`0`),
668	UINT64_C(`0`),
669	UINT64_C(`44040192`), // ADCri
670	UINT64_C(`10485760`), // ADCrr
671	UINT64_C(`10485760`), // ADCrsi
672	UINT64_C(`10485776`), // ADCrsr
673	UINT64_C(`41943040`), // ADDri
674	UINT64_C(`8388608`), // ADDrr
675	UINT64_C(`8388608`), // ADDrsi
676	UINT64_C(`8388624`), // ADDrsr
677	UINT64_C(`34537472`), // ADR
678	UINT64_C(`4088398656`), // AESD
679	UINT64_C(`4088398592`), // AESE
680	UINT64_C(`4088398784`), // AESIMC
681	UINT64_C(`4088398720`), // AESMC
682	UINT64_C(`33554432`), // ANDri
683	UINT64_C(`0`), // ANDrr
684	UINT64_C(`0`), // ANDrsi
685	UINT64_C(`16`), // ANDrsr
686	UINT64_C(`4261416192`), // BF16VDOTI_VDOTD
687	UINT64_C(`4261416256`), // BF16VDOTI_VDOTQ
688	UINT64_C(`4227861760`), // BF16VDOTS_VDOTD
689	UINT64_C(`4227861824`), // BF16VDOTS_VDOTQ
690	UINT64_C(`4088792640`), // BF16_VCVT
691	UINT64_C(`246614336`), // BF16_VCVTB
692	UINT64_C(`246614464`), // BF16_VCVTT
693	UINT64_C(`130023455`), // BFC
694	UINT64_C(`130023440`), // BFI
695	UINT64_C(`62914560`), // BICri
696	UINT64_C(`29360128`), // BICrr
697	UINT64_C(`29360128`), // BICrsi
698	UINT64_C(`29360144`), // BICrsr
699	UINT64_C(`3776970864`), // BKPT
700	UINT64_C(`3942645760`), // BL
701	UINT64_C(`3778019120`), // BLX
702	UINT64_C(`19922736`), // BLX_pred
703	UINT64_C(`4194304000`), // BLXi
704	UINT64_C(`184549376`), // BL_pred
705	UINT64_C(`3778019088`), // BX
706	UINT64_C(`19922720`), // BXJ
707	UINT64_C(`19922718`), // BX_RET
708	UINT64_C(`19922704`), // BX_pred
709	UINT64_C(`167772160`), // Bcc
710	UINT64_C(`3992977408`), // CDE_CX1
711	UINT64_C(`4261412864`), // CDE_CX1A
712	UINT64_C(`3992977472`), // CDE_CX1D
713	UINT64_C(`4261412928`), // CDE_CX1DA
714	UINT64_C(`3997171712`), // CDE_CX2
715	UINT64_C(`4265607168`), // CDE_CX2A
716	UINT64_C(`3997171776`), // CDE_CX2D
717	UINT64_C(`4265607232`), // CDE_CX2DA
718	UINT64_C(`4001366016`), // CDE_CX3
719	UINT64_C(`4269801472`), // CDE_CX3A
720	UINT64_C(`4001366080`), // CDE_CX3D
721	UINT64_C(`4269801536`), // CDE_CX3DA
722	UINT64_C(`4246732800`), // CDE_VCX1A_fpdp
723	UINT64_C(`4229955584`), // CDE_VCX1A_fpsp
724	UINT64_C(`4229955648`), // CDE_VCX1A_vec
725	UINT64_C(`3978297344`), // CDE_VCX1_fpdp
726	UINT64_C(`3961520128`), // CDE_VCX1_fpsp
727	UINT64_C(`3961520192`), // CDE_VCX1_vec
728	UINT64_C(`4247781376`), // CDE_VCX2A_fpdp
729	UINT64_C(`4231004160`), // CDE_VCX2A_fpsp
730	UINT64_C(`4231004224`), // CDE_VCX2A_vec
731	UINT64_C(`3979345920`), // CDE_VCX2_fpdp
732	UINT64_C(`3962568704`), // CDE_VCX2_fpsp
733	UINT64_C(`3962568768`), // CDE_VCX2_vec
734	UINT64_C(`4253024256`), // CDE_VCX3A_fpdp
735	UINT64_C(`4236247040`), // CDE_VCX3A_fpsp
736	UINT64_C(`4236247104`), // CDE_VCX3A_vec
737	UINT64_C(`3984588800`), // CDE_VCX3_fpdp
738	UINT64_C(`3967811584`), // CDE_VCX3_fpsp
739	UINT64_C(`3967811648`), // CDE_VCX3_vec
740	UINT64_C(`234881024`), // CDP
741	UINT64_C(`4261412864`), // CDP2
742	UINT64_C(`4118802463`), // CLREX
743	UINT64_C(`24055568`), // CLZ
744	UINT64_C(`57671680`), // CMNri
745	UINT64_C(`24117248`), // CMNzrr
746	UINT64_C(`24117248`), // CMNzrsi
747	UINT64_C(`24117264`), // CMNzrsr
748	UINT64_C(`55574528`), // CMPri
749	UINT64_C(`22020096`), // CMPrr
750	UINT64_C(`22020096`), // CMPrsi
751	UINT64_C(`22020112`), // CMPrsr
752	UINT64_C(`4043440128`), // CPS1p
753	UINT64_C(`4043309056`), // CPS2p
754	UINT64_C(`4043440128`), // CPS3p
755	UINT64_C(`3774873664`), // CRC32B
756	UINT64_C(`3774874176`), // CRC32CB
757	UINT64_C(`3776971328`), // CRC32CH
758	UINT64_C(`3779068480`), // CRC32CW
759	UINT64_C(`3776970816`), // CRC32H
760	UINT64_C(`3779067968`), // CRC32W
761	UINT64_C(`52490480`), // DBG
762	UINT64_C(`4118802512`), // DMB
763	UINT64_C(`4118802496`), // DSB
764	UINT64_C(`35651584`), // EORri
765	UINT64_C(`2097152`), // EORrr
766	UINT64_C(`2097152`), // EORrsi
767	UINT64_C(`2097168`), // EORrsr
768	UINT64_C(`23068782`), // ERET
769	UINT64_C(`246418176`), // FCONSTD
770	UINT64_C(`246417664`), // FCONSTH
771	UINT64_C(`246417920`), // FCONSTS
772	UINT64_C(`221252353`), // FLDMXDB_UPD
773	UINT64_C(`210766593`), // FLDMXIA
774	UINT64_C(`212863745`), // FLDMXIA_UPD
775	UINT64_C(`250739216`), // FMSTAT
776	UINT64_C(`220203777`), // FSTMXDB_UPD
777	UINT64_C(`209718017`), // FSTMXIA
778	UINT64_C(`211815169`), // FSTMXIA_UPD
779	UINT64_C(`52490240`), // HINT
780	UINT64_C(`3774873712`), // HLT
781	UINT64_C(`3779068016`), // HVC
782	UINT64_C(`4118802528`), // ISB
783	UINT64_C(`26217631`), // LDA
784	UINT64_C(`30411935`), // LDAB
785	UINT64_C(`26218143`), // LDAEX
786	UINT64_C(`30412447`), // LDAEXB
787	UINT64_C(`28315295`), // LDAEXD
788	UINT64_C(`32509599`), // LDAEXH
789	UINT64_C(`32509087`), // LDAH
790	UINT64_C(`4249878528`), // LDC2L_OFFSET
791	UINT64_C(`4241489920`), // LDC2L_OPTION
792	UINT64_C(`4235198464`), // LDC2L_POST
793	UINT64_C(`4251975680`), // LDC2L_PRE
794	UINT64_C(`4245684224`), // LDC2_OFFSET
795	UINT64_C(`4237295616`), // LDC2_OPTION
796	UINT64_C(`4231004160`), // LDC2_POST
797	UINT64_C(`4247781376`), // LDC2_PRE
798	UINT64_C(`223346688`), // LDCL_OFFSET
799	UINT64_C(`214958080`), // LDCL_OPTION
800	UINT64_C(`208666624`), // LDCL_POST
801	UINT64_C(`225443840`), // LDCL_PRE
802	UINT64_C(`219152384`), // LDC_OFFSET
803	UINT64_C(`210763776`), // LDC_OPTION
804	UINT64_C(`204472320`), // LDC_POST
805	UINT64_C(`221249536`), // LDC_PRE
806	UINT64_C(`135266304`), // LDMDA
807	UINT64_C(`137363456`), // LDMDA_UPD
808	UINT64_C(`152043520`), // LDMDB
809	UINT64_C(`154140672`), // LDMDB_UPD
810	UINT64_C(`143654912`), // LDMIA
811	UINT64_C(`145752064`), // LDMIA_UPD
812	UINT64_C(`160432128`), // LDMIB
813	UINT64_C(`162529280`), // LDMIB_UPD
814	UINT64_C(`74448896`), // LDRBT_POST_IMM
815	UINT64_C(`108003328`), // LDRBT_POST_REG
816	UINT64_C(`72351744`), // LDRB_POST_IMM
817	UINT64_C(`105906176`), // LDRB_POST_REG
818	UINT64_C(`91226112`), // LDRB_PRE_IMM
819	UINT64_C(`124780544`), // LDRB_PRE_REG
820	UINT64_C(`89128960`), // LDRBi12
821	UINT64_C(`122683392`), // LDRBrs
822	UINT64_C(`16777424`), // LDRD
823	UINT64_C(`208`), // LDRD_POST
824	UINT64_C(`18874576`), // LDRD_PRE
825	UINT64_C(`26218399`), // LDREX
826	UINT64_C(`30412703`), // LDREXB
827	UINT64_C(`28315551`), // LDREXD
828	UINT64_C(`32509855`), // LDREXH
829	UINT64_C(`17825968`), // LDRH
830	UINT64_C(`7340208`), // LDRHTi
831	UINT64_C(`3145904`), // LDRHTr
832	UINT64_C(`1048752`), // LDRH_POST
833	UINT64_C(`19923120`), // LDRH_PRE
834	UINT64_C(`17826000`), // LDRSB
835	UINT64_C(`7340240`), // LDRSBTi
836	UINT64_C(`3145936`), // LDRSBTr
837	UINT64_C(`1048784`), // LDRSB_POST
838	UINT64_C(`19923152`), // LDRSB_PRE
839	UINT64_C(`17826032`), // LDRSH
840	UINT64_C(`7340272`), // LDRSHTi
841	UINT64_C(`3145968`), // LDRSHTr
842	UINT64_C(`1048816`), // LDRSH_POST
843	UINT64_C(`19923184`), // LDRSH_PRE
844	UINT64_C(`70254592`), // LDRT_POST_IMM
845	UINT64_C(`103809024`), // LDRT_POST_REG
846	UINT64_C(`68157440`), // LDR_POST_IMM
847	UINT64_C(`101711872`), // LDR_POST_REG
848	UINT64_C(`87031808`), // LDR_PRE_IMM
849	UINT64_C(`120586240`), // LDR_PRE_REG
850	UINT64_C(`85917696`), // LDRcp
851	UINT64_C(`84934656`), // LDRi12
852	UINT64_C(`118489088`), // LDRrs
853	UINT64_C(`234881040`), // MCR
854	UINT64_C(`4261412880`), // MCR2
855	UINT64_C(`205520896`), // MCRR
856	UINT64_C(`4232052736`), // MCRR2
857	UINT64_C(`2097296`), // MLA
858	UINT64_C(`6291600`), // MLS
859	UINT64_C(`27324430`), // MOVPCLR
860	UINT64_C(`54525952`), // MOVTi16
861	UINT64_C(`60817408`), // MOVi
862	UINT64_C(`50331648`), // MOVi16
863	UINT64_C(`27262976`), // MOVr
864	UINT64_C(`27262976`), // MOVr_TC
865	UINT64_C(`27262976`), // MOVsi
866	UINT64_C(`27262992`), // MOVsr
867	UINT64_C(`235929616`), // MRC
868	UINT64_C(`4262461456`), // MRC2
869	UINT64_C(`206569472`), // MRRC
870	UINT64_C(`4233101312`), // MRRC2
871	UINT64_C(`17760256`), // MRS
872	UINT64_C(`16777728`), // MRSbanked
873	UINT64_C(`21954560`), // MRSsys
874	UINT64_C(`18935808`), // MSR
875	UINT64_C(`18936320`), // MSRbanked
876	UINT64_C(`52490240`), // MSRi
877	UINT64_C(`144`), // MUL
878	UINT64_C(`3931111727`), // MVE_ASRLi
879	UINT64_C(`3931111725`), // MVE_ASRLr
880	UINT64_C(`4027637761`), // MVE_DLSTP_16
881	UINT64_C(`4028686337`), // MVE_DLSTP_32
882	UINT64_C(`4029734913`), // MVE_DLSTP_64
883	UINT64_C(`4026589185`), // MVE_DLSTP_8
884	UINT64_C(`4027572225`), // MVE_LCTP
885	UINT64_C(`4028612609`), // MVE_LETP
886	UINT64_C(`3931111695`), // MVE_LSLLi
887	UINT64_C(`3931111693`), // MVE_LSLLr
888	UINT64_C(`3931111711`), // MVE_LSRL
889	UINT64_C(`3931115309`), // MVE_SQRSHR
890	UINT64_C(`3931177261`), // MVE_SQRSHRL
891	UINT64_C(`3931115327`), // MVE_SQSHL
892	UINT64_C(`3931177279`), // MVE_SQSHLL
893	UINT64_C(`3931115311`), // MVE_SRSHR
894	UINT64_C(`3931177263`), // MVE_SRSHRL
895	UINT64_C(`3931115277`), // MVE_UQRSHL
896	UINT64_C(`3931177229`), // MVE_UQRSHLL
897	UINT64_C(`3931115279`), // MVE_UQSHL
898	UINT64_C(`3931177231`), // MVE_UQSHLL
899	UINT64_C(`3931115295`), // MVE_URSHR
900	UINT64_C(`3931177247`), // MVE_URSHRL
901	UINT64_C(`4002418433`), // MVE_VABAVs16
902	UINT64_C(`4003467009`), // MVE_VABAVs32
903	UINT64_C(`4001369857`), // MVE_VABAVs8
904	UINT64_C(`4270853889`), // MVE_VABAVu16
905	UINT64_C(`4271902465`), // MVE_VABAVu32
906	UINT64_C(`4269805313`), // MVE_VABAVu8
907	UINT64_C(`4281339200`), // MVE_VABDf16
908	UINT64_C(`4280290624`), // MVE_VABDf32
909	UINT64_C(`4010805056`), // MVE_VABDs16
910	UINT64_C(`4011853632`), // MVE_VABDs32
911	UINT64_C(`4009756480`), // MVE_VABDs8
912	UINT64_C(`4279240512`), // MVE_VABDu16
913	UINT64_C(`4280289088`), // MVE_VABDu32
914	UINT64_C(`4278191936`), // MVE_VABDu8
915	UINT64_C(`4290053952`), // MVE_VABSf16
916	UINT64_C(`4290316096`), // MVE_VABSf32
917	UINT64_C(`4290052928`), // MVE_VABSs16
918	UINT64_C(`4290315072`), // MVE_VABSs32
919	UINT64_C(`4289790784`), // MVE_VABSs8
920	UINT64_C(`3996126976`), // MVE_VADC
921	UINT64_C(`3996131072`), // MVE_VADCI
922	UINT64_C(`4001959712`), // MVE_VADDLVs32acc
923	UINT64_C(`4001959680`), // MVE_VADDLVs32no_acc
924	UINT64_C(`4270395168`), // MVE_VADDLVu32acc
925	UINT64_C(`4270395136`), // MVE_VADDLVu32no_acc
926	UINT64_C(`4009037600`), // MVE_VADDVs16acc
927	UINT64_C(`4009037568`), // MVE_VADDVs16no_acc
928	UINT64_C(`4009299744`), // MVE_VADDVs32acc
929	UINT64_C(`4009299712`), // MVE_VADDVs32no_acc
930	UINT64_C(`4008775456`), // MVE_VADDVs8acc
931	UINT64_C(`4008775424`), // MVE_VADDVs8no_acc
932	UINT64_C(`4277473056`), // MVE_VADDVu16acc
933	UINT64_C(`4277473024`), // MVE_VADDVu16no_acc
934	UINT64_C(`4277735200`), // MVE_VADDVu32acc
935	UINT64_C(`4277735168`), // MVE_VADDVu32no_acc
936	UINT64_C(`4277210912`), // MVE_VADDVu8acc
937	UINT64_C(`4277210880`), // MVE_VADDVu8no_acc
938	UINT64_C(`4264562496`), // MVE_VADD_qr_f16
939	UINT64_C(`3996127040`), // MVE_VADD_qr_f32
940	UINT64_C(`3994095424`), // MVE_VADD_qr_i16
941	UINT64_C(`3995144000`), // MVE_VADD_qr_i32
942	UINT64_C(`3993046848`), // MVE_VADD_qr_i8
943	UINT64_C(`4010806592`), // MVE_VADDf16
944	UINT64_C(`4009758016`), // MVE_VADDf32
945	UINT64_C(`4010805312`), // MVE_VADDi16
946	UINT64_C(`4011853888`), // MVE_VADDi32
947	UINT64_C(`4009756736`), // MVE_VADDi8
948	UINT64_C(`4009754960`), // MVE_VAND
949	UINT64_C(`4010803536`), // MVE_VBIC
950	UINT64_C(`4018145648`), // MVE_VBICimmi16
951	UINT64_C(`4018143600`), // MVE_VBICimmi32
952	UINT64_C(`4262534752`), // MVE_VBRSR16
953	UINT64_C(`4263583328`), // MVE_VBRSR32
954	UINT64_C(`4261486176`), // MVE_VBRSR8
955	UINT64_C(`4236249152`), // MVE_VCADDf16
956	UINT64_C(`4237297728`), // MVE_VCADDf32
957	UINT64_C(`4262465280`), // MVE_VCADDi16
958	UINT64_C(`4263513856`), // MVE_VCADDi32
959	UINT64_C(`4261416704`), // MVE_VCADDi8
960	UINT64_C(`4289987648`), // MVE_VCLSs16
961	UINT64_C(`4290249792`), // MVE_VCLSs32
962	UINT64_C(`4289725504`), // MVE_VCLSs8
963	UINT64_C(`4289987776`), // MVE_VCLZs16
964	UINT64_C(`4290249920`), // MVE_VCLZs32
965	UINT64_C(`4289725632`), // MVE_VCLZs8
966	UINT64_C(`4229957696`), // MVE_VCMLAf16
967	UINT64_C(`4231006272`), // MVE_VCMLAf32
968	UINT64_C(`4264627968`), // MVE_VCMPf16
969	UINT64_C(`4264628032`), // MVE_VCMPf16r
970	UINT64_C(`3996192512`), // MVE_VCMPf32
971	UINT64_C(`3996192576`), // MVE_VCMPf32r
972	UINT64_C(`4262530816`), // MVE_VCMPi16
973	UINT64_C(`4262530880`), // MVE_VCMPi16r
974	UINT64_C(`4263579392`), // MVE_VCMPi32
975	UINT64_C(`4263579456`), // MVE_VCMPi32r
976	UINT64_C(`4261482240`), // MVE_VCMPi8
977	UINT64_C(`4261482304`), // MVE_VCMPi8r
978	UINT64_C(`4262534912`), // MVE_VCMPs16
979	UINT64_C(`4262534976`), // MVE_VCMPs16r
980	UINT64_C(`4263583488`), // MVE_VCMPs32
981	UINT64_C(`4263583552`), // MVE_VCMPs32r
982	UINT64_C(`4261486336`), // MVE_VCMPs8
983	UINT64_C(`4261486400`), // MVE_VCMPs8r
984	UINT64_C(`4262530817`), // MVE_VCMPu16
985	UINT64_C(`4262530912`), // MVE_VCMPu16r
986	UINT64_C(`4263579393`), // MVE_VCMPu32
987	UINT64_C(`4263579488`), // MVE_VCMPu32r
988	UINT64_C(`4261482241`), // MVE_VCMPu8
989	UINT64_C(`4261482336`), // MVE_VCMPu8r
990	UINT64_C(`3996126720`), // MVE_VCMULf16
991	UINT64_C(`4264562176`), // MVE_VCMULf32
992	UINT64_C(`4027639809`), // MVE_VCTP16
993	UINT64_C(`4028688385`), // MVE_VCTP32
994	UINT64_C(`4029736961`), // MVE_VCTP64
995	UINT64_C(`4026591233`), // MVE_VCTP8
996	UINT64_C(`3997109761`), // MVE_VCVTf16f32bh
997	UINT64_C(`3997113857`), // MVE_VCVTf16f32th
998	UINT64_C(`4021292112`), // MVE_VCVTf16s16_fix
999	UINT64_C(`4290184768`), // MVE_VCVTf16s16n
1000	UINT64_C(`4289727568`), // MVE_VCVTf16u16_fix
1001	UINT64_C(`4290184896`), // MVE_VCVTf16u16n
1002	UINT64_C(`4265545217`), // MVE_VCVTf32f16bh
1003	UINT64_C(`4265549313`), // MVE_VCVTf32f16th
1004	UINT64_C(`4020244048`), // MVE_VCVTf32s32_fix
1005	UINT64_C(`4290446912`), // MVE_VCVTf32s32n
1006	UINT64_C(`4288679504`), // MVE_VCVTf32u32_fix
1007	UINT64_C(`4290447040`), // MVE_VCVTf32u32n
1008	UINT64_C(`4021292368`), // MVE_VCVTs16f16_fix
1009	UINT64_C(`4290183232`), // MVE_VCVTs16f16a
1010	UINT64_C(`4290184000`), // MVE_VCVTs16f16m
1011	UINT64_C(`4290183488`), // MVE_VCVTs16f16n
1012	UINT64_C(`4290183744`), // MVE_VCVTs16f16p
1013	UINT64_C(`4290185024`), // MVE_VCVTs16f16z
1014	UINT64_C(`4020244304`), // MVE_VCVTs32f32_fix
1015	UINT64_C(`4290445376`), // MVE_VCVTs32f32a
1016	UINT64_C(`4290446144`), // MVE_VCVTs32f32m
1017	UINT64_C(`4290445632`), // MVE_VCVTs32f32n
1018	UINT64_C(`4290445888`), // MVE_VCVTs32f32p
1019	UINT64_C(`4290447168`), // MVE_VCVTs32f32z
1020	UINT64_C(`4289727824`), // MVE_VCVTu16f16_fix
1021	UINT64_C(`4290183360`), // MVE_VCVTu16f16a
1022	UINT64_C(`4290184128`), // MVE_VCVTu16f16m
1023	UINT64_C(`4290183616`), // MVE_VCVTu16f16n
1024	UINT64_C(`4290183872`), // MVE_VCVTu16f16p
1025	UINT64_C(`4290185152`), // MVE_VCVTu16f16z
1026	UINT64_C(`4288679760`), // MVE_VCVTu32f32_fix
1027	UINT64_C(`4290445504`), // MVE_VCVTu32f32a
1028	UINT64_C(`4290446272`), // MVE_VCVTu32f32m
1029	UINT64_C(`4290445760`), // MVE_VCVTu32f32n
1030	UINT64_C(`4290446016`), // MVE_VCVTu32f32p
1031	UINT64_C(`4290447296`), // MVE_VCVTu32f32z
1032	UINT64_C(`3994099566`), // MVE_VDDUPu16
1033	UINT64_C(`3995148142`), // MVE_VDDUPu32
1034	UINT64_C(`3993050990`), // MVE_VDDUPu8
1035	UINT64_C(`4003466032`), // MVE_VDUP16
1036	UINT64_C(`4003466000`), // MVE_VDUP32
1037	UINT64_C(`4007660304`), // MVE_VDUP8
1038	UINT64_C(`3994099552`), // MVE_VDWDUPu16
1039	UINT64_C(`3995148128`), // MVE_VDWDUPu32
1040	UINT64_C(`3993050976`), // MVE_VDWDUPu8
1041	UINT64_C(`4278190416`), // MVE_VEOR
1042	UINT64_C(`4264631872`), // MVE_VFMA_qr_Sf16
1043	UINT64_C(`3996196416`), // MVE_VFMA_qr_Sf32
1044	UINT64_C(`4264627776`), // MVE_VFMA_qr_f16
1045	UINT64_C(`3996192320`), // MVE_VFMA_qr_f32
1046	UINT64_C(`4010806352`), // MVE_VFMAf16
1047	UINT64_C(`4009757776`), // MVE_VFMAf32
1048	UINT64_C(`4012903504`), // MVE_VFMSf16
1049	UINT64_C(`4011854928`), // MVE_VFMSf32
1050	UINT64_C(`3994029888`), // MVE_VHADD_qr_s16
1051	UINT64_C(`3995078464`), // MVE_VHADD_qr_s32
1052	UINT64_C(`3992981312`), // MVE_VHADD_qr_s8
1053	UINT64_C(`4262465344`), // MVE_VHADD_qr_u16
1054	UINT64_C(`4263513920`), // MVE_VHADD_qr_u32
1055	UINT64_C(`4261416768`), // MVE_VHADD_qr_u8
1056	UINT64_C(`4010803264`), // MVE_VHADDs16
1057	UINT64_C(`4011851840`), // MVE_VHADDs32
1058	UINT64_C(`4009754688`), // MVE_VHADDs8
1059	UINT64_C(`4279238720`), // MVE_VHADDu16
1060	UINT64_C(`4280287296`), // MVE_VHADDu32
1061	UINT64_C(`4278190144`), // MVE_VHADDu8
1062	UINT64_C(`3994029824`), // MVE_VHCADDs16
1063	UINT64_C(`3995078400`), // MVE_VHCADDs32
1064	UINT64_C(`3992981248`), // MVE_VHCADDs8
1065	UINT64_C(`3994033984`), // MVE_VHSUB_qr_s16
1066	UINT64_C(`3995082560`), // MVE_VHSUB_qr_s32
1067	UINT64_C(`3992985408`), // MVE_VHSUB_qr_s8
1068	UINT64_C(`4262469440`), // MVE_VHSUB_qr_u16
1069	UINT64_C(`4263518016`), // MVE_VHSUB_qr_u32
1070	UINT64_C(`4261420864`), // MVE_VHSUB_qr_u8
1071	UINT64_C(`4010803776`), // MVE_VHSUBs16
1072	UINT64_C(`4011852352`), // MVE_VHSUBs32
1073	UINT64_C(`4009755200`), // MVE_VHSUBs8
1074	UINT64_C(`4279239232`), // MVE_VHSUBu16
1075	UINT64_C(`4280287808`), // MVE_VHSUBu32
1076	UINT64_C(`4278190656`), // MVE_VHSUBu8
1077	UINT64_C(`3994095470`), // MVE_VIDUPu16
1078	UINT64_C(`3995144046`), // MVE_VIDUPu32
1079	UINT64_C(`3993046894`), // MVE_VIDUPu8
1080	UINT64_C(`3994095456`), // MVE_VIWDUPu16
1081	UINT64_C(`3995144032`), // MVE_VIWDUPu32
1082	UINT64_C(`3993046880`), // MVE_VIWDUPu8
1083	UINT64_C(`4237303424`), // MVE_VLD20_16
1084	UINT64_C(`4239400576`), // MVE_VLD20_16_wb
1085	UINT64_C(`4237303552`), // MVE_VLD20_32
1086	UINT64_C(`4239400704`), // MVE_VLD20_32_wb
1087	UINT64_C(`4237303296`), // MVE_VLD20_8
1088	UINT64_C(`4239400448`), // MVE_VLD20_8_wb
1089	UINT64_C(`4237303456`), // MVE_VLD21_16
1090	UINT64_C(`4239400608`), // MVE_VLD21_16_wb
1091	UINT64_C(`4237303584`), // MVE_VLD21_32
1092	UINT64_C(`4239400736`), // MVE_VLD21_32_wb
1093	UINT64_C(`4237303328`), // MVE_VLD21_8
1094	UINT64_C(`4239400480`), // MVE_VLD21_8_wb
1095	UINT64_C(`4237303425`), // MVE_VLD40_16
1096	UINT64_C(`4239400577`), // MVE_VLD40_16_wb
1097	UINT64_C(`4237303553`), // MVE_VLD40_32
1098	UINT64_C(`4239400705`), // MVE_VLD40_32_wb
1099	UINT64_C(`4237303297`), // MVE_VLD40_8
1100	UINT64_C(`4239400449`), // MVE_VLD40_8_wb
1101	UINT64_C(`4237303457`), // MVE_VLD41_16
1102	UINT64_C(`4239400609`), // MVE_VLD41_16_wb
1103	UINT64_C(`4237303585`), // MVE_VLD41_32
1104	UINT64_C(`4239400737`), // MVE_VLD41_32_wb
1105	UINT64_C(`4237303329`), // MVE_VLD41_8
1106	UINT64_C(`4239400481`), // MVE_VLD41_8_wb
1107	UINT64_C(`4237303489`), // MVE_VLD42_16
1108	UINT64_C(`4239400641`), // MVE_VLD42_16_wb
1109	UINT64_C(`4237303617`), // MVE_VLD42_32
1110	UINT64_C(`4239400769`), // MVE_VLD42_32_wb
1111	UINT64_C(`4237303361`), // MVE_VLD42_8
1112	UINT64_C(`4239400513`), // MVE_VLD42_8_wb
1113	UINT64_C(`4237303521`), // MVE_VLD43_16
1114	UINT64_C(`4239400673`), // MVE_VLD43_16_wb
1115	UINT64_C(`4237303649`), // MVE_VLD43_32
1116	UINT64_C(`4239400801`), // MVE_VLD43_32_wb
1117	UINT64_C(`4237303393`), // MVE_VLD43_8
1118	UINT64_C(`4239400545`), // MVE_VLD43_8_wb
1119	UINT64_C(`3977252480`), // MVE_VLDRBS16
1120	UINT64_C(`3962572416`), // MVE_VLDRBS16_post
1121	UINT64_C(`3979349632`), // MVE_VLDRBS16_pre
1122	UINT64_C(`3968863872`), // MVE_VLDRBS16_rq
1123	UINT64_C(`3977252608`), // MVE_VLDRBS32
1124	UINT64_C(`3962572544`), // MVE_VLDRBS32_post
1125	UINT64_C(`3979349760`), // MVE_VLDRBS32_pre
1126	UINT64_C(`3968864000`), // MVE_VLDRBS32_rq
1127	UINT64_C(`4245687936`), // MVE_VLDRBU16
1128	UINT64_C(`4231007872`), // MVE_VLDRBU16_post
1129	UINT64_C(`4247785088`), // MVE_VLDRBU16_pre
1130	UINT64_C(`4237299328`), // MVE_VLDRBU16_rq
1131	UINT64_C(`4245688064`), // MVE_VLDRBU32
1132	UINT64_C(`4231008000`), // MVE_VLDRBU32_post
1133	UINT64_C(`4247785216`), // MVE_VLDRBU32_pre
1134	UINT64_C(`4237299456`), // MVE_VLDRBU32_rq
1135	UINT64_C(`3977256448`), // MVE_VLDRBU8
1136	UINT64_C(`3962576384`), // MVE_VLDRBU8_post
1137	UINT64_C(`3979353600`), // MVE_VLDRBU8_pre
1138	UINT64_C(`4237299200`), // MVE_VLDRBU8_rq
1139	UINT64_C(`4245692160`), // MVE_VLDRDU64_qi
1140	UINT64_C(`4247789312`), // MVE_VLDRDU64_qi_pre
1141	UINT64_C(`4237299665`), // MVE_VLDRDU64_rq
1142	UINT64_C(`4237299664`), // MVE_VLDRDU64_rq_u
1143	UINT64_C(`3977776896`), // MVE_VLDRHS32
1144	UINT64_C(`3963096832`), // MVE_VLDRHS32_post
1145	UINT64_C(`3979874048`), // MVE_VLDRHS32_pre
1146	UINT64_C(`3968864017`), // MVE_VLDRHS32_rq
1147	UINT64_C(`3968864016`), // MVE_VLDRHS32_rq_u
1148	UINT64_C(`3977256576`), // MVE_VLDRHU16
1149	UINT64_C(`3962576512`), // MVE_VLDRHU16_post
1150	UINT64_C(`3979353728`), // MVE_VLDRHU16_pre
1151	UINT64_C(`4237299345`), // MVE_VLDRHU16_rq
1152	UINT64_C(`4237299344`), // MVE_VLDRHU16_rq_u
1153	UINT64_C(`4246212352`), // MVE_VLDRHU32
1154	UINT64_C(`4231532288`), // MVE_VLDRHU32_post
1155	UINT64_C(`4248309504`), // MVE_VLDRHU32_pre
1156	UINT64_C(`4237299473`), // MVE_VLDRHU32_rq
1157	UINT64_C(`4237299472`), // MVE_VLDRHU32_rq_u
1158	UINT64_C(`3977256704`), // MVE_VLDRWU32
1159	UINT64_C(`3962576640`), // MVE_VLDRWU32_post
1160	UINT64_C(`3979353856`), // MVE_VLDRWU32_pre
1161	UINT64_C(`4245691904`), // MVE_VLDRWU32_qi
1162	UINT64_C(`4247789056`), // MVE_VLDRWU32_qi_pre
1163	UINT64_C(`4237299521`), // MVE_VLDRWU32_rq
1164	UINT64_C(`4237299520`), // MVE_VLDRWU32_rq_u
1165	UINT64_C(`4007923456`), // MVE_VMAXAVs16
1166	UINT64_C(`4008185600`), // MVE_VMAXAVs32
1167	UINT64_C(`4007661312`), // MVE_VMAXAVs8
1168	UINT64_C(`3996585601`), // MVE_VMAXAs16
1169	UINT64_C(`3996847745`), // MVE_VMAXAs32
1170	UINT64_C(`3996323457`), // MVE_VMAXAs8
1171	UINT64_C(`4276883200`), // MVE_VMAXNMAVf16
1172	UINT64_C(`4008447744`), // MVE_VMAXNMAVf32
1173	UINT64_C(`4265545345`), // MVE_VMAXNMAf16
1174	UINT64_C(`3997109889`), // MVE_VMAXNMAf32
1175	UINT64_C(`4277014272`), // MVE_VMAXNMVf16
1176	UINT64_C(`4008578816`), // MVE_VMAXNMVf32
1177	UINT64_C(`4279242576`), // MVE_VMAXNMf16
1178	UINT64_C(`4278194000`), // MVE_VMAXNMf32
1179	UINT64_C(`4008054528`), // MVE_VMAXVs16
1180	UINT64_C(`4008316672`), // MVE_VMAXVs32
1181	UINT64_C(`4007792384`), // MVE_VMAXVs8
1182	UINT64_C(`4276489984`), // MVE_VMAXVu16
1183	UINT64_C(`4276752128`), // MVE_VMAXVu32
1184	UINT64_C(`4276227840`), // MVE_VMAXVu8
1185	UINT64_C(`4010804800`), // MVE_VMAXs16
1186	UINT64_C(`4011853376`), // MVE_VMAXs32
1187	UINT64_C(`4009756224`), // MVE_VMAXs8
1188	UINT64_C(`4279240256`), // MVE_VMAXu16
1189	UINT64_C(`4280288832`), // MVE_VMAXu32
1190	UINT64_C(`4278191680`), // MVE_VMAXu8
1191	UINT64_C(`4007923584`), // MVE_VMINAVs16
1192	UINT64_C(`4008185728`), // MVE_VMINAVs32
1193	UINT64_C(`4007661440`), // MVE_VMINAVs8
1194	UINT64_C(`3996589697`), // MVE_VMINAs16
1195	UINT64_C(`3996851841`), // MVE_VMINAs32
1196	UINT64_C(`3996327553`), // MVE_VMINAs8
1197	UINT64_C(`4276883328`), // MVE_VMINNMAVf16
1198	UINT64_C(`4008447872`), // MVE_VMINNMAVf32
1199	UINT64_C(`4265549441`), // MVE_VMINNMAf16
1200	UINT64_C(`3997113985`), // MVE_VMINNMAf32
1201	UINT64_C(`4277014400`), // MVE_VMINNMVf16
1202	UINT64_C(`4008578944`), // MVE_VMINNMVf32
1203	UINT64_C(`4281339728`), // MVE_VMINNMf16
1204	UINT64_C(`4280291152`), // MVE_VMINNMf32
1205	UINT64_C(`4008054656`), // MVE_VMINVs16
1206	UINT64_C(`4008316800`), // MVE_VMINVs32
1207	UINT64_C(`4007792512`), // MVE_VMINVs8
1208	UINT64_C(`4276490112`), // MVE_VMINVu16
1209	UINT64_C(`4276752256`), // MVE_VMINVu32
1210	UINT64_C(`4276227968`), // MVE_VMINVu8
1211	UINT64_C(`4010804816`), // MVE_VMINs16
1212	UINT64_C(`4011853392`), // MVE_VMINs32
1213	UINT64_C(`4009756240`), // MVE_VMINs8
1214	UINT64_C(`4279240272`), // MVE_VMINu16
1215	UINT64_C(`4280288848`), // MVE_VMINu32
1216	UINT64_C(`4278191696`), // MVE_VMINu8
1217	UINT64_C(`4008709664`), // MVE_VMLADAVas16
1218	UINT64_C(`4008775200`), // MVE_VMLADAVas32
1219	UINT64_C(`4008709920`), // MVE_VMLADAVas8
1220	UINT64_C(`4277145120`), // MVE_VMLADAVau16
1221	UINT64_C(`4277210656`), // MVE_VMLADAVau32
1222	UINT64_C(`4277145376`), // MVE_VMLADAVau8
1223	UINT64_C(`4008713760`), // MVE_VMLADAVaxs16
1224	UINT64_C(`4008779296`), // MVE_VMLADAVaxs32
1225	UINT64_C(`4008714016`), // MVE_VMLADAVaxs8
1226	UINT64_C(`4008709632`), // MVE_VMLADAVs16
1227	UINT64_C(`4008775168`), // MVE_VMLADAVs32
1228	UINT64_C(`4008709888`), // MVE_VMLADAVs8
1229	UINT64_C(`4277145088`), // MVE_VMLADAVu16
1230	UINT64_C(`4277210624`), // MVE_VMLADAVu32
1231	UINT64_C(`4277145344`), // MVE_VMLADAVu8
1232	UINT64_C(`4008713728`), // MVE_VMLADAVxs16
1233	UINT64_C(`4008779264`), // MVE_VMLADAVxs32
1234	UINT64_C(`4008713984`), // MVE_VMLADAVxs8
1235	UINT64_C(`4001369632`), // MVE_VMLALDAVas16
1236	UINT64_C(`4001435168`), // MVE_VMLALDAVas32
1237	UINT64_C(`4269805088`), // MVE_VMLALDAVau16
1238	UINT64_C(`4269870624`), // MVE_VMLALDAVau32
1239	UINT64_C(`4001373728`), // MVE_VMLALDAVaxs16
1240	UINT64_C(`4001439264`), // MVE_VMLALDAVaxs32
1241	UINT64_C(`4001369600`), // MVE_VMLALDAVs16
1242	UINT64_C(`4001435136`), // MVE_VMLALDAVs32
1243	UINT64_C(`4269805056`), // MVE_VMLALDAVu16
1244	UINT64_C(`4269870592`), // MVE_VMLALDAVu32
1245	UINT64_C(`4001373696`), // MVE_VMLALDAVxs16
1246	UINT64_C(`4001439232`), // MVE_VMLALDAVxs32
1247	UINT64_C(`3994099264`), // MVE_VMLAS_qr_s16
1248	UINT64_C(`3995147840`), // MVE_VMLAS_qr_s32
1249	UINT64_C(`3993050688`), // MVE_VMLAS_qr_s8
1250	UINT64_C(`4262534720`), // MVE_VMLAS_qr_u16
1251	UINT64_C(`4263583296`), // MVE_VMLAS_qr_u32
1252	UINT64_C(`4261486144`), // MVE_VMLAS_qr_u8
1253	UINT64_C(`3994095168`), // MVE_VMLA_qr_s16
1254	UINT64_C(`3995143744`), // MVE_VMLA_qr_s32
1255	UINT64_C(`3993046592`), // MVE_VMLA_qr_s8
1256	UINT64_C(`4262530624`), // MVE_VMLA_qr_u16
1257	UINT64_C(`4263579200`), // MVE_VMLA_qr_u32
1258	UINT64_C(`4261482048`), // MVE_VMLA_qr_u8
1259	UINT64_C(`4008709665`), // MVE_VMLSDAVas16
1260	UINT64_C(`4008775201`), // MVE_VMLSDAVas32
1261	UINT64_C(`4277145121`), // MVE_VMLSDAVas8
1262	UINT64_C(`4008713761`), // MVE_VMLSDAVaxs16
1263	UINT64_C(`4008779297`), // MVE_VMLSDAVaxs32
1264	UINT64_C(`4277149217`), // MVE_VMLSDAVaxs8
1265	UINT64_C(`4008709633`), // MVE_VMLSDAVs16
1266	UINT64_C(`4008775169`), // MVE_VMLSDAVs32
1267	UINT64_C(`4277145089`), // MVE_VMLSDAVs8
1268	UINT64_C(`4008713729`), // MVE_VMLSDAVxs16
1269	UINT64_C(`4008779265`), // MVE_VMLSDAVxs32
1270	UINT64_C(`4277149185`), // MVE_VMLSDAVxs8
1271	UINT64_C(`4001369633`), // MVE_VMLSLDAVas16
1272	UINT64_C(`4001435169`), // MVE_VMLSLDAVas32
1273	UINT64_C(`4001373729`), // MVE_VMLSLDAVaxs16
1274	UINT64_C(`4001439265`), // MVE_VMLSLDAVaxs32
1275	UINT64_C(`4001369601`), // MVE_VMLSLDAVs16
1276	UINT64_C(`4001435137`), // MVE_VMLSLDAVs32
1277	UINT64_C(`4001373697`), // MVE_VMLSLDAVxs16
1278	UINT64_C(`4001439233`), // MVE_VMLSLDAVxs32
1279	UINT64_C(`4004515648`), // MVE_VMOVLs16bh
1280	UINT64_C(`4004519744`), // MVE_VMOVLs16th
1281	UINT64_C(`4003991360`), // MVE_VMOVLs8bh
1282	UINT64_C(`4003995456`), // MVE_VMOVLs8th
1283	UINT64_C(`4272951104`), // MVE_VMOVLu16bh
1284	UINT64_C(`4272955200`), // MVE_VMOVLu16th
1285	UINT64_C(`4272426816`), // MVE_VMOVLu8bh
1286	UINT64_C(`4272430912`), // MVE_VMOVLu8th
1287	UINT64_C(`4264627841`), // MVE_VMOVNi16bh
1288	UINT64_C(`4264631937`), // MVE_VMOVNi16th
1289	UINT64_C(`4264889985`), // MVE_VMOVNi32bh
1290	UINT64_C(`4264894081`), // MVE_VMOVNi32th
1291	UINT64_C(`3994028816`), // MVE_VMOV_from_lane_32
1292	UINT64_C(`3994028848`), // MVE_VMOV_from_lane_s16
1293	UINT64_C(`3998223120`), // MVE_VMOV_from_lane_s8
1294	UINT64_C(`4002417456`), // MVE_VMOV_from_lane_u16
1295	UINT64_C(`4006611728`), // MVE_VMOV_from_lane_u8
1296	UINT64_C(`3960475392`), // MVE_VMOV_q_rr
1297	UINT64_C(`3959426816`), // MVE_VMOV_rr_q
1298	UINT64_C(`3992980272`), // MVE_VMOV_to_lane_16
1299	UINT64_C(`3992980240`), // MVE_VMOV_to_lane_32
1300	UINT64_C(`3997174544`), // MVE_VMOV_to_lane_8
1301	UINT64_C(`4018147152`), // MVE_VMOVimmf32
1302	UINT64_C(`4018145360`), // MVE_VMOVimmi16
1303	UINT64_C(`4018143312`), // MVE_VMOVimmi32
1304	UINT64_C(`4018146928`), // MVE_VMOVimmi64
1305	UINT64_C(`4018146896`), // MVE_VMOVimmi8
1306	UINT64_C(`3994095105`), // MVE_VMULHs16
1307	UINT64_C(`3995143681`), // MVE_VMULHs32
1308	UINT64_C(`3993046529`), // MVE_VMULHs8
1309	UINT64_C(`4262530561`), // MVE_VMULHu16
1310	UINT64_C(`4263579137`), // MVE_VMULHu32
1311	UINT64_C(`4261481985`), // MVE_VMULHu8
1312	UINT64_C(`4264627712`), // MVE_VMULLBp16
1313	UINT64_C(`3996192256`), // MVE_VMULLBp8
1314	UINT64_C(`3994095104`), // MVE_VMULLBs16
1315	UINT64_C(`3995143680`), // MVE_VMULLBs32
1316	UINT64_C(`3993046528`), // MVE_VMULLBs8
1317	UINT64_C(`4262530560`), // MVE_VMULLBu16
1318	UINT64_C(`4263579136`), // MVE_VMULLBu32
1319	UINT64_C(`4261481984`), // MVE_VMULLBu8
1320	UINT64_C(`4264631808`), // MVE_VMULLTp16
1321	UINT64_C(`3996196352`), // MVE_VMULLTp8
1322	UINT64_C(`3994099200`), // MVE_VMULLTs16
1323	UINT64_C(`3995147776`), // MVE_VMULLTs32
1324	UINT64_C(`3993050624`), // MVE_VMULLTs8
1325	UINT64_C(`4262534656`), // MVE_VMULLTu16
1326	UINT64_C(`4263583232`), // MVE_VMULLTu32
1327	UINT64_C(`4261486080`), // MVE_VMULLTu8
1328	UINT64_C(`4264627808`), // MVE_VMUL_qr_f16
1329	UINT64_C(`3996192352`), // MVE_VMUL_qr_f32
1330	UINT64_C(`3994099296`), // MVE_VMUL_qr_i16
1331	UINT64_C(`3995147872`), // MVE_VMUL_qr_i32
1332	UINT64_C(`3993050720`), // MVE_VMUL_qr_i8
1333	UINT64_C(`4279242064`), // MVE_VMULf16
1334	UINT64_C(`4278193488`), // MVE_VMULf32
1335	UINT64_C(`4010805584`), // MVE_VMULi16
1336	UINT64_C(`4011854160`), // MVE_VMULi32
1337	UINT64_C(`4009757008`), // MVE_VMULi8
1338	UINT64_C(`4289725888`), // MVE_VMVN
1339	UINT64_C(`4018145392`), // MVE_VMVNimmi16
1340	UINT64_C(`4018143344`), // MVE_VMVNimmi32
1341	UINT64_C(`4290054080`), // MVE_VNEGf16
1342	UINT64_C(`4290316224`), // MVE_VNEGf32
1343	UINT64_C(`4290053056`), // MVE_VNEGs16
1344	UINT64_C(`4290315200`), // MVE_VNEGs32
1345	UINT64_C(`4289790912`), // MVE_VNEGs8
1346	UINT64_C(`4012900688`), // MVE_VORN
1347	UINT64_C(`4011852112`), // MVE_VORR
1348	UINT64_C(`4018145616`), // MVE_VORRimmi16
1349	UINT64_C(`4018143568`), // MVE_VORRimmi32
1350	UINT64_C(`4264628045`), // MVE_VPNOT
1351	UINT64_C(`4264627969`), // MVE_VPSEL
1352	UINT64_C(`4264628045`), // MVE_VPST
1353	UINT64_C(`4261482240`), // MVE_VPTv16i8
1354	UINT64_C(`4261482304`), // MVE_VPTv16i8r
1355	UINT64_C(`4261486336`), // MVE_VPTv16s8
1356	UINT64_C(`4261486400`), // MVE_VPTv16s8r
1357	UINT64_C(`4261482241`), // MVE_VPTv16u8
1358	UINT64_C(`4261482336`), // MVE_VPTv16u8r
1359	UINT64_C(`3996192512`), // MVE_VPTv4f32
1360	UINT64_C(`3996192576`), // MVE_VPTv4f32r
1361	UINT64_C(`4263579392`), // MVE_VPTv4i32
1362	UINT64_C(`4263579456`), // MVE_VPTv4i32r
1363	UINT64_C(`4263583488`), // MVE_VPTv4s32
1364	UINT64_C(`4263583552`), // MVE_VPTv4s32r
1365	UINT64_C(`4263579393`), // MVE_VPTv4u32
1366	UINT64_C(`4263579488`), // MVE_VPTv4u32r
1367	UINT64_C(`4264627968`), // MVE_VPTv8f16
1368	UINT64_C(`4264628032`), // MVE_VPTv8f16r
1369	UINT64_C(`4262530816`), // MVE_VPTv8i16
1370	UINT64_C(`4262530880`), // MVE_VPTv8i16r
1371	UINT64_C(`4262534912`), // MVE_VPTv8s16
1372	UINT64_C(`4262534976`), // MVE_VPTv8s16r
1373	UINT64_C(`4262530817`), // MVE_VPTv8u16
1374	UINT64_C(`4262530912`), // MVE_VPTv8u16r
1375	UINT64_C(`4289988416`), // MVE_VQABSs16
1376	UINT64_C(`4290250560`), // MVE_VQABSs32
1377	UINT64_C(`4289726272`), // MVE_VQABSs8
1378	UINT64_C(`3994029920`), // MVE_VQADD_qr_s16
1379	UINT64_C(`3995078496`), // MVE_VQADD_qr_s32
1380	UINT64_C(`3992981344`), // MVE_VQADD_qr_s8
1381	UINT64_C(`4262465376`), // MVE_VQADD_qr_u16
1382	UINT64_C(`4263513952`), // MVE_VQADD_qr_u32
1383	UINT64_C(`4261416800`), // MVE_VQADD_qr_u8
1384	UINT64_C(`4010803280`), // MVE_VQADDs16
1385	UINT64_C(`4011851856`), // MVE_VQADDs32
1386	UINT64_C(`4009754704`), // MVE_VQADDs8
1387	UINT64_C(`4279238736`), // MVE_VQADDu16
1388	UINT64_C(`4280287312`), // MVE_VQADDu32
1389	UINT64_C(`4278190160`), // MVE_VQADDu8
1390	UINT64_C(`3994033664`), // MVE_VQDMLADHXs16
1391	UINT64_C(`3995082240`), // MVE_VQDMLADHXs32
1392	UINT64_C(`3992985088`), // MVE_VQDMLADHXs8
1393	UINT64_C(`3994029568`), // MVE_VQDMLADHs16
1394	UINT64_C(`3995078144`), // MVE_VQDMLADHs32
1395	UINT64_C(`3992980992`), // MVE_VQDMLADHs8
1396	UINT64_C(`3994029664`), // MVE_VQDMLAH_qrs16
1397	UINT64_C(`3995078240`), // MVE_VQDMLAH_qrs32
1398	UINT64_C(`3992981088`), // MVE_VQDMLAH_qrs8
1399	UINT64_C(`3994033760`), // MVE_VQDMLASH_qrs16
1400	UINT64_C(`3995082336`), // MVE_VQDMLASH_qrs32
1401	UINT64_C(`3992985184`), // MVE_VQDMLASH_qrs8
1402	UINT64_C(`4262469120`), // MVE_VQDMLSDHXs16
1403	UINT64_C(`4263517696`), // MVE_VQDMLSDHXs32
1404	UINT64_C(`4261420544`), // MVE_VQDMLSDHXs8
1405	UINT64_C(`4262465024`), // MVE_VQDMLSDHs16
1406	UINT64_C(`4263513600`), // MVE_VQDMLSDHs32
1407	UINT64_C(`4261416448`), // MVE_VQDMLSDHs8
1408	UINT64_C(`3994095200`), // MVE_VQDMULH_qr_s16
1409	UINT64_C(`3995143776`), // MVE_VQDMULH_qr_s32
1410	UINT64_C(`3993046624`), // MVE_VQDMULH_qr_s8
1411	UINT64_C(`4010806080`), // MVE_VQDMULHi16
1412	UINT64_C(`4011854656`), // MVE_VQDMULHi32
1413	UINT64_C(`4009757504`), // MVE_VQDMULHi8
1414	UINT64_C(`3996127072`), // MVE_VQDMULL_qr_s16bh
1415	UINT64_C(`3996131168`), // MVE_VQDMULL_qr_s16th
1416	UINT64_C(`4264562528`), // MVE_VQDMULL_qr_s32bh
1417	UINT64_C(`4264566624`), // MVE_VQDMULL_qr_s32th
1418	UINT64_C(`3996126977`), // MVE_VQDMULLs16bh
1419	UINT64_C(`3996131073`), // MVE_VQDMULLs16th
1420	UINT64_C(`4264562433`), // MVE_VQDMULLs32bh
1421	UINT64_C(`4264566529`), // MVE_VQDMULLs32th
1422	UINT64_C(`3996323329`), // MVE_VQMOVNs16bh
1423	UINT64_C(`3996327425`), // MVE_VQMOVNs16th
1424	UINT64_C(`3996585473`), // MVE_VQMOVNs32bh
1425	UINT64_C(`3996589569`), // MVE_VQMOVNs32th
1426	UINT64_C(`4264758785`), // MVE_VQMOVNu16bh
1427	UINT64_C(`4264762881`), // MVE_VQMOVNu16th
1428	UINT64_C(`4265020929`), // MVE_VQMOVNu32bh
1429	UINT64_C(`4265025025`), // MVE_VQMOVNu32th
1430	UINT64_C(`3996192385`), // MVE_VQMOVUNs16bh
1431	UINT64_C(`3996196481`), // MVE_VQMOVUNs16th
1432	UINT64_C(`3996454529`), // MVE_VQMOVUNs32bh
1433	UINT64_C(`3996458625`), // MVE_VQMOVUNs32th
1434	UINT64_C(`4289988544`), // MVE_VQNEGs16
1435	UINT64_C(`4290250688`), // MVE_VQNEGs32
1436	UINT64_C(`4289726400`), // MVE_VQNEGs8
1437	UINT64_C(`3994033665`), // MVE_VQRDMLADHXs16
1438	UINT64_C(`3995082241`), // MVE_VQRDMLADHXs32
1439	UINT64_C(`3992985089`), // MVE_VQRDMLADHXs8
1440	UINT64_C(`3994029569`), // MVE_VQRDMLADHs16
1441	UINT64_C(`3995078145`), // MVE_VQRDMLADHs32
1442	UINT64_C(`3992980993`), // MVE_VQRDMLADHs8
1443	UINT64_C(`3994029632`), // MVE_VQRDMLAH_qrs16
1444	UINT64_C(`3995078208`), // MVE_VQRDMLAH_qrs32
1445	UINT64_C(`3992981056`), // MVE_VQRDMLAH_qrs8
1446	UINT64_C(`3994033728`), // MVE_VQRDMLASH_qrs16
1447	UINT64_C(`3995082304`), // MVE_VQRDMLASH_qrs32
1448	UINT64_C(`3992985152`), // MVE_VQRDMLASH_qrs8
1449	UINT64_C(`4262469121`), // MVE_VQRDMLSDHXs16
1450	UINT64_C(`4263517697`), // MVE_VQRDMLSDHXs32
1451	UINT64_C(`4261420545`), // MVE_VQRDMLSDHXs8
1452	UINT64_C(`4262465025`), // MVE_VQRDMLSDHs16
1453	UINT64_C(`4263513601`), // MVE_VQRDMLSDHs32
1454	UINT64_C(`4261416449`), // MVE_VQRDMLSDHs8
1455	UINT64_C(`4262530656`), // MVE_VQRDMULH_qr_s16
1456	UINT64_C(`4263579232`), // MVE_VQRDMULH_qr_s32
1457	UINT64_C(`4261482080`), // MVE_VQRDMULH_qr_s8
1458	UINT64_C(`4279241536`), // MVE_VQRDMULHi16
1459	UINT64_C(`4280290112`), // MVE_VQRDMULHi32
1460	UINT64_C(`4278192960`), // MVE_VQRDMULHi8
1461	UINT64_C(`4010804560`), // MVE_VQRSHL_by_vecs16
1462	UINT64_C(`4011853136`), // MVE_VQRSHL_by_vecs32
1463	UINT64_C(`4009755984`), // MVE_VQRSHL_by_vecs8
1464	UINT64_C(`4279240016`), // MVE_VQRSHL_by_vecu16
1465	UINT64_C(`4280288592`), // MVE_VQRSHL_by_vecu32
1466	UINT64_C(`4278191440`), // MVE_VQRSHL_by_vecu8
1467	UINT64_C(`3996589792`), // MVE_VQRSHL_qrs16
1468	UINT64_C(`3996851936`), // MVE_VQRSHL_qrs32
1469	UINT64_C(`3996327648`), // MVE_VQRSHL_qrs8
1470	UINT64_C(`4265025248`), // MVE_VQRSHL_qru16
1471	UINT64_C(`4265287392`), // MVE_VQRSHL_qru32
1472	UINT64_C(`4264763104`), // MVE_VQRSHL_qru8
1473	UINT64_C(`4001894209`), // MVE_VQRSHRNbhs16
1474	UINT64_C(`4002418497`), // MVE_VQRSHRNbhs32
1475	UINT64_C(`4270329665`), // MVE_VQRSHRNbhu16
1476	UINT64_C(`4270853953`), // MVE_VQRSHRNbhu32
1477	UINT64_C(`4001898305`), // MVE_VQRSHRNths16
1478	UINT64_C(`4002422593`), // MVE_VQRSHRNths32
1479	UINT64_C(`4270333761`), // MVE_VQRSHRNthu16
1480	UINT64_C(`4270858049`), // MVE_VQRSHRNthu32
1481	UINT64_C(`4270329792`), // MVE_VQRSHRUNs16bh
1482	UINT64_C(`4270333888`), // MVE_VQRSHRUNs16th
1483	UINT64_C(`4270854080`), // MVE_VQRSHRUNs32bh
1484	UINT64_C(`4270858176`), // MVE_VQRSHRUNs32th
1485	UINT64_C(`4287628880`), // MVE_VQSHLU_imms16
1486	UINT64_C(`4288677456`), // MVE_VQSHLU_imms32
1487	UINT64_C(`4287104592`), // MVE_VQSHLU_imms8
1488	UINT64_C(`4010804304`), // MVE_VQSHL_by_vecs16
1489	UINT64_C(`4011852880`), // MVE_VQSHL_by_vecs32
1490	UINT64_C(`4009755728`), // MVE_VQSHL_by_vecs8
1491	UINT64_C(`4279239760`), // MVE_VQSHL_by_vecu16
1492	UINT64_C(`4280288336`), // MVE_VQSHL_by_vecu32
1493	UINT64_C(`4278191184`), // MVE_VQSHL_by_vecu8
1494	UINT64_C(`3996458720`), // MVE_VQSHL_qrs16
1495	UINT64_C(`3996720864`), // MVE_VQSHL_qrs32
1496	UINT64_C(`3996196576`), // MVE_VQSHL_qrs8
1497	UINT64_C(`4264894176`), // MVE_VQSHL_qru16
1498	UINT64_C(`4265156320`), // MVE_VQSHL_qru32
1499	UINT64_C(`4264632032`), // MVE_VQSHL_qru8
1500	UINT64_C(`4019193680`), // MVE_VQSHLimms16
1501	UINT64_C(`4020242256`), // MVE_VQSHLimms32
1502	UINT64_C(`4018669392`), // MVE_VQSHLimms8
1503	UINT64_C(`4287629136`), // MVE_VQSHLimmu16
1504	UINT64_C(`4288677712`), // MVE_VQSHLimmu32
1505	UINT64_C(`4287104848`), // MVE_VQSHLimmu8
1506	UINT64_C(`4001894208`), // MVE_VQSHRNbhs16
1507	UINT64_C(`4002418496`), // MVE_VQSHRNbhs32
1508	UINT64_C(`4270329664`), // MVE_VQSHRNbhu16
1509	UINT64_C(`4270853952`), // MVE_VQSHRNbhu32
1510	UINT64_C(`4001898304`), // MVE_VQSHRNths16
1511	UINT64_C(`4002422592`), // MVE_VQSHRNths32
1512	UINT64_C(`4270333760`), // MVE_VQSHRNthu16
1513	UINT64_C(`4270858048`), // MVE_VQSHRNthu32
1514	UINT64_C(`4001894336`), // MVE_VQSHRUNs16bh
1515	UINT64_C(`4001898432`), // MVE_VQSHRUNs16th
1516	UINT64_C(`4002418624`), // MVE_VQSHRUNs32bh
1517	UINT64_C(`4002422720`), // MVE_VQSHRUNs32th
1518	UINT64_C(`3994034016`), // MVE_VQSUB_qr_s16
1519	UINT64_C(`3995082592`), // MVE_VQSUB_qr_s32
1520	UINT64_C(`3992985440`), // MVE_VQSUB_qr_s8
1521	UINT64_C(`4262469472`), // MVE_VQSUB_qr_u16
1522	UINT64_C(`4263518048`), // MVE_VQSUB_qr_u32
1523	UINT64_C(`4261420896`), // MVE_VQSUB_qr_u8
1524	UINT64_C(`4010803792`), // MVE_VQSUBs16
1525	UINT64_C(`4011852368`), // MVE_VQSUBs32
1526	UINT64_C(`4009755216`), // MVE_VQSUBs8
1527	UINT64_C(`4279239248`), // MVE_VQSUBu16
1528	UINT64_C(`4280287824`), // MVE_VQSUBu32
1529	UINT64_C(`4278190672`), // MVE_VQSUBu8
1530	UINT64_C(`4289724736`), // MVE_VREV16_8
1531	UINT64_C(`4289986752`), // MVE_VREV32_16
1532	UINT64_C(`4289724608`), // MVE_VREV32_8
1533	UINT64_C(`4289986624`), // MVE_VREV64_16
1534	UINT64_C(`4290248768`), // MVE_VREV64_32
1535	UINT64_C(`4289724480`), // MVE_VREV64_8
1536	UINT64_C(`4010803520`), // MVE_VRHADDs16
1537	UINT64_C(`4011852096`), // MVE_VRHADDs32
1538	UINT64_C(`4009754944`), // MVE_VRHADDs8
1539	UINT64_C(`4279238976`), // MVE_VRHADDu16
1540	UINT64_C(`4280287552`), // MVE_VRHADDu32
1541	UINT64_C(`4278190400`), // MVE_VRHADDu8
1542	UINT64_C(`4290118976`), // MVE_VRINTf16A
1543	UINT64_C(`4290119360`), // MVE_VRINTf16M
1544	UINT64_C(`4290118720`), // MVE_VRINTf16N
1545	UINT64_C(`4290119616`), // MVE_VRINTf16P
1546	UINT64_C(`4290118848`), // MVE_VRINTf16X
1547	UINT64_C(`4290119104`), // MVE_VRINTf16Z
1548	UINT64_C(`4290381120`), // MVE_VRINTf32A
1549	UINT64_C(`4290381504`), // MVE_VRINTf32M
1550	UINT64_C(`4290380864`), // MVE_VRINTf32N
1551	UINT64_C(`4290381760`), // MVE_VRINTf32P
1552	UINT64_C(`4290380992`), // MVE_VRINTf32X
1553	UINT64_C(`4290381248`), // MVE_VRINTf32Z
1554	UINT64_C(`4001369888`), // MVE_VRMLALDAVHas32
1555	UINT64_C(`4269805344`), // MVE_VRMLALDAVHau32
1556	UINT64_C(`4001373984`), // MVE_VRMLALDAVHaxs32
1557	UINT64_C(`4001369856`), // MVE_VRMLALDAVHs32
1558	UINT64_C(`4269805312`), // MVE_VRMLALDAVHu32
1559	UINT64_C(`4001373952`), // MVE_VRMLALDAVHxs32
1560	UINT64_C(`4269805089`), // MVE_VRMLSLDAVHas32
1561	UINT64_C(`4269809185`), // MVE_VRMLSLDAVHaxs32
1562	UINT64_C(`4269805057`), // MVE_VRMLSLDAVHs32
1563	UINT64_C(`4269809153`), // MVE_VRMLSLDAVHxs32
1564	UINT64_C(`3994099201`), // MVE_VRMULHs16
1565	UINT64_C(`3995147777`), // MVE_VRMULHs32
1566	UINT64_C(`3993050625`), // MVE_VRMULHs8
1567	UINT64_C(`4262534657`), // MVE_VRMULHu16
1568	UINT64_C(`4263583233`), // MVE_VRMULHu32
1569	UINT64_C(`4261486081`), // MVE_VRMULHu8
1570	UINT64_C(`4010804544`), // MVE_VRSHL_by_vecs16
1571	UINT64_C(`4011853120`), // MVE_VRSHL_by_vecs32
1572	UINT64_C(`4009755968`), // MVE_VRSHL_by_vecs8
1573	UINT64_C(`4279240000`), // MVE_VRSHL_by_vecu16
1574	UINT64_C(`4280288576`), // MVE_VRSHL_by_vecu32
1575	UINT64_C(`4278191424`), // MVE_VRSHL_by_vecu8
1576	UINT64_C(`3996589664`), // MVE_VRSHL_qrs16
1577	UINT64_C(`3996851808`), // MVE_VRSHL_qrs32
1578	UINT64_C(`3996327520`), // MVE_VRSHL_qrs8
1579	UINT64_C(`4265025120`), // MVE_VRSHL_qru16
1580	UINT64_C(`4265287264`), // MVE_VRSHL_qru32
1581	UINT64_C(`4264762976`), // MVE_VRSHL_qru8
1582	UINT64_C(`4270329793`), // MVE_VRSHRNi16bh
1583	UINT64_C(`4270333889`), // MVE_VRSHRNi16th
1584	UINT64_C(`4270854081`), // MVE_VRSHRNi32bh
1585	UINT64_C(`4270858177`), // MVE_VRSHRNi32th
1586	UINT64_C(`4019192400`), // MVE_VRSHR_imms16
1587	UINT64_C(`4020240976`), // MVE_VRSHR_imms32
1588	UINT64_C(`4018668112`), // MVE_VRSHR_imms8
1589	UINT64_C(`4287627856`), // MVE_VRSHR_immu16
1590	UINT64_C(`4288676432`), // MVE_VRSHR_immu32
1591	UINT64_C(`4287103568`), // MVE_VRSHR_immu8
1592	UINT64_C(`4264562432`), // MVE_VSBC
1593	UINT64_C(`4264566528`), // MVE_VSBCI
1594	UINT64_C(`4003467200`), // MVE_VSHLC
1595	UINT64_C(`4004515648`), // MVE_VSHLL_imms16bh
1596	UINT64_C(`4004519744`), // MVE_VSHLL_imms16th
1597	UINT64_C(`4003991360`), // MVE_VSHLL_imms8bh
1598	UINT64_C(`4003995456`), // MVE_VSHLL_imms8th
1599	UINT64_C(`4272951104`), // MVE_VSHLL_immu16bh
1600	UINT64_C(`4272955200`), // MVE_VSHLL_immu16th
1601	UINT64_C(`4272426816`), // MVE_VSHLL_immu8bh
1602	UINT64_C(`4272430912`), // MVE_VSHLL_immu8th
1603	UINT64_C(`3996454401`), // MVE_VSHLL_lws16bh
1604	UINT64_C(`3996458497`), // MVE_VSHLL_lws16th
1605	UINT64_C(`3996192257`), // MVE_VSHLL_lws8bh
1606	UINT64_C(`3996196353`), // MVE_VSHLL_lws8th
1607	UINT64_C(`4264889857`), // MVE_VSHLL_lwu16bh
1608	UINT64_C(`4264893953`), // MVE_VSHLL_lwu16th
1609	UINT64_C(`4264627713`), // MVE_VSHLL_lwu8bh
1610	UINT64_C(`4264631809`), // MVE_VSHLL_lwu8th
1611	UINT64_C(`4010804288`), // MVE_VSHL_by_vecs16
1612	UINT64_C(`4011852864`), // MVE_VSHL_by_vecs32
1613	UINT64_C(`4009755712`), // MVE_VSHL_by_vecs8
1614	UINT64_C(`4279239744`), // MVE_VSHL_by_vecu16
1615	UINT64_C(`4280288320`), // MVE_VSHL_by_vecu32
1616	UINT64_C(`4278191168`), // MVE_VSHL_by_vecu8
1617	UINT64_C(`4019193168`), // MVE_VSHL_immi16
1618	UINT64_C(`4020241744`), // MVE_VSHL_immi32
1619	UINT64_C(`4018668880`), // MVE_VSHL_immi8
1620	UINT64_C(`3996458592`), // MVE_VSHL_qrs16
1621	UINT64_C(`3996720736`), // MVE_VSHL_qrs32
1622	UINT64_C(`3996196448`), // MVE_VSHL_qrs8
1623	UINT64_C(`4264894048`), // MVE_VSHL_qru16
1624	UINT64_C(`4265156192`), // MVE_VSHL_qru32
1625	UINT64_C(`4264631904`), // MVE_VSHL_qru8
1626	UINT64_C(`4001894337`), // MVE_VSHRNi16bh
1627	UINT64_C(`4001898433`), // MVE_VSHRNi16th
1628	UINT64_C(`4002418625`), // MVE_VSHRNi32bh
1629	UINT64_C(`4002422721`), // MVE_VSHRNi32th
1630	UINT64_C(`4019191888`), // MVE_VSHR_imms16
1631	UINT64_C(`4020240464`), // MVE_VSHR_imms32
1632	UINT64_C(`4018667600`), // MVE_VSHR_imms8
1633	UINT64_C(`4287627344`), // MVE_VSHR_immu16
1634	UINT64_C(`4288675920`), // MVE_VSHR_immu32
1635	UINT64_C(`4287103056`), // MVE_VSHR_immu8
1636	UINT64_C(`4287628624`), // MVE_VSLIimm16
1637	UINT64_C(`4288677200`), // MVE_VSLIimm32
1638	UINT64_C(`4287104336`), // MVE_VSLIimm8
1639	UINT64_C(`4287628368`), // MVE_VSRIimm16
1640	UINT64_C(`4288676944`), // MVE_VSRIimm32
1641	UINT64_C(`4287104080`), // MVE_VSRIimm8
1642	UINT64_C(`4236254848`), // MVE_VST20_16
1643	UINT64_C(`4238352000`), // MVE_VST20_16_wb
1644	UINT64_C(`4236254976`), // MVE_VST20_32
1645	UINT64_C(`4238352128`), // MVE_VST20_32_wb
1646	UINT64_C(`4236254720`), // MVE_VST20_8
1647	UINT64_C(`4238351872`), // MVE_VST20_8_wb
1648	UINT64_C(`4236254880`), // MVE_VST21_16
1649	UINT64_C(`4238352032`), // MVE_VST21_16_wb
1650	UINT64_C(`4236255008`), // MVE_VST21_32
1651	UINT64_C(`4238352160`), // MVE_VST21_32_wb
1652	UINT64_C(`4236254752`), // MVE_VST21_8
1653	UINT64_C(`4238351904`), // MVE_VST21_8_wb
1654	UINT64_C(`4236254849`), // MVE_VST40_16
1655	UINT64_C(`4238352001`), // MVE_VST40_16_wb
1656	UINT64_C(`4236254977`), // MVE_VST40_32
1657	UINT64_C(`4238352129`), // MVE_VST40_32_wb
1658	UINT64_C(`4236254721`), // MVE_VST40_8
1659	UINT64_C(`4238351873`), // MVE_VST40_8_wb
1660	UINT64_C(`4236254881`), // MVE_VST41_16
1661	UINT64_C(`4238352033`), // MVE_VST41_16_wb
1662	UINT64_C(`4236255009`), // MVE_VST41_32
1663	UINT64_C(`4238352161`), // MVE_VST41_32_wb
1664	UINT64_C(`4236254753`), // MVE_VST41_8
1665	UINT64_C(`4238351905`), // MVE_VST41_8_wb
1666	UINT64_C(`4236254913`), // MVE_VST42_16
1667	UINT64_C(`4238352065`), // MVE_VST42_16_wb
1668	UINT64_C(`4236255041`), // MVE_VST42_32
1669	UINT64_C(`4238352193`), // MVE_VST42_32_wb
1670	UINT64_C(`4236254785`), // MVE_VST42_8
1671	UINT64_C(`4238351937`), // MVE_VST42_8_wb
1672	UINT64_C(`4236254945`), // MVE_VST43_16
1673	UINT64_C(`4238352097`), // MVE_VST43_16_wb
1674	UINT64_C(`4236255073`), // MVE_VST43_32
1675	UINT64_C(`4238352225`), // MVE_VST43_32_wb
1676	UINT64_C(`4236254817`), // MVE_VST43_8
1677	UINT64_C(`4238351969`), // MVE_VST43_8_wb
1678	UINT64_C(`3976203904`), // MVE_VSTRB16
1679	UINT64_C(`3961523840`), // MVE_VSTRB16_post
1680	UINT64_C(`3978301056`), // MVE_VSTRB16_pre
1681	UINT64_C(`3967815296`), // MVE_VSTRB16_rq
1682	UINT64_C(`3976204032`), // MVE_VSTRB32
1683	UINT64_C(`3961523968`), // MVE_VSTRB32_post
1684	UINT64_C(`3978301184`), // MVE_VSTRB32_pre
1685	UINT64_C(`3967815424`), // MVE_VSTRB32_rq
1686	UINT64_C(`3967815168`), // MVE_VSTRB8_rq
1687	UINT64_C(`3976207872`), // MVE_VSTRBU8
1688	UINT64_C(`3961527808`), // MVE_VSTRBU8_post
1689	UINT64_C(`3978305024`), // MVE_VSTRBU8_pre
1690	UINT64_C(`4244643584`), // MVE_VSTRD64_qi
1691	UINT64_C(`4246740736`), // MVE_VSTRD64_qi_pre
1692	UINT64_C(`3967815633`), // MVE_VSTRD64_rq
1693	UINT64_C(`3967815632`), // MVE_VSTRD64_rq_u
1694	UINT64_C(`3967815313`), // MVE_VSTRH16_rq
1695	UINT64_C(`3967815312`), // MVE_VSTRH16_rq_u
1696	UINT64_C(`3976728320`), // MVE_VSTRH32
1697	UINT64_C(`3962048256`), // MVE_VSTRH32_post
1698	UINT64_C(`3978825472`), // MVE_VSTRH32_pre
1699	UINT64_C(`3967815441`), // MVE_VSTRH32_rq
1700	UINT64_C(`3967815440`), // MVE_VSTRH32_rq_u
1701	UINT64_C(`3976208000`), // MVE_VSTRHU16
1702	UINT64_C(`3961527936`), // MVE_VSTRHU16_post
1703	UINT64_C(`3978305152`), // MVE_VSTRHU16_pre
1704	UINT64_C(`4244643328`), // MVE_VSTRW32_qi
1705	UINT64_C(`4246740480`), // MVE_VSTRW32_qi_pre
1706	UINT64_C(`3967815489`), // MVE_VSTRW32_rq
1707	UINT64_C(`3967815488`), // MVE_VSTRW32_rq_u
1708	UINT64_C(`3976208128`), // MVE_VSTRWU32
1709	UINT64_C(`3961528064`), // MVE_VSTRWU32_post
1710	UINT64_C(`3978305280`), // MVE_VSTRWU32_pre
1711	UINT64_C(`4264566592`), // MVE_VSUB_qr_f16
1712	UINT64_C(`3996131136`), // MVE_VSUB_qr_f32
1713	UINT64_C(`3994099520`), // MVE_VSUB_qr_i16
1714	UINT64_C(`3995148096`), // MVE_VSUB_qr_i32
1715	UINT64_C(`3993050944`), // MVE_VSUB_qr_i8
1716	UINT64_C(`4012903744`), // MVE_VSUBf16
1717	UINT64_C(`4011855168`), // MVE_VSUBf32
1718	UINT64_C(`4279240768`), // MVE_VSUBi16
1719	UINT64_C(`4280289344`), // MVE_VSUBi32
1720	UINT64_C(`4278192192`), // MVE_VSUBi8
1721	UINT64_C(`4027629569`), // MVE_WLSTP_16
1722	UINT64_C(`4028678145`), // MVE_WLSTP_32
1723	UINT64_C(`4029726721`), // MVE_WLSTP_64
1724	UINT64_C(`4026580993`), // MVE_WLSTP_8
1725	UINT64_C(`65011712`), // MVNi
1726	UINT64_C(`31457280`), // MVNr
1727	UINT64_C(`31457280`), // MVNsi
1728	UINT64_C(`31457296`), // MVNsr
1729	UINT64_C(`4076867344`), // NEON_VMAXNMNDf
1730	UINT64_C(`4077915920`), // NEON_VMAXNMNDh
1731	UINT64_C(`4076867408`), // NEON_VMAXNMNQf
1732	UINT64_C(`4077915984`), // NEON_VMAXNMNQh
1733	UINT64_C(`4078964496`), // NEON_VMINNMNDf
1734	UINT64_C(`4080013072`), // NEON_VMINNMNDh
1735	UINT64_C(`4078964560`), // NEON_VMINNMNQf
1736	UINT64_C(`4080013136`), // NEON_VMINNMNQh
1737	UINT64_C(`58720256`), // ORRri
1738	UINT64_C(`25165824`), // ORRrr
1739	UINT64_C(`25165824`), // ORRrsi
1740	UINT64_C(`25165840`), // ORRrsr
1741	UINT64_C(`109051920`), // PKHBT
1742	UINT64_C(`109051984`), // PKHTB
1743	UINT64_C(`4111527936`), // PLDWi12
1744	UINT64_C(`4145082368`), // PLDWrs
1745	UINT64_C(`4115722240`), // PLDi12
1746	UINT64_C(`4149276672`), // PLDrs
1747	UINT64_C(`4098945024`), // PLIi12
1748	UINT64_C(`4132499456`), // PLIrs
1749	UINT64_C(`16777296`), // QADD
1750	UINT64_C(`102764304`), // QADD16
1751	UINT64_C(`102764432`), // QADD8
1752	UINT64_C(`102764336`), // QASX
1753	UINT64_C(`20971600`), // QDADD
1754	UINT64_C(`23068752`), // QDSUB
1755	UINT64_C(`102764368`), // QSAX
1756	UINT64_C(`18874448`), // QSUB
1757	UINT64_C(`102764400`), // QSUB16
1758	UINT64_C(`102764528`), // QSUB8
1759	UINT64_C(`117378864`), // RBIT
1760	UINT64_C(`113184560`), // REV
1761	UINT64_C(`113184688`), // REV16
1762	UINT64_C(`117378992`), // REVSH
1763	UINT64_C(`4161800704`), // RFEDA
1764	UINT64_C(`4163897856`), // RFEDA_UPD
1765	UINT64_C(`4178577920`), // RFEDB
1766	UINT64_C(`4180675072`), // RFEDB_UPD
1767	UINT64_C(`4170189312`), // RFEIA
1768	UINT64_C(`4172286464`), // RFEIA_UPD
1769	UINT64_C(`4186966528`), // RFEIB
1770	UINT64_C(`4189063680`), // RFEIB_UPD
1771	UINT64_C(`39845888`), // RSBri
1772	UINT64_C(`6291456`), // RSBrr
1773	UINT64_C(`6291456`), // RSBrsi
1774	UINT64_C(`6291472`), // RSBrsr
1775	UINT64_C(`48234496`), // RSCri
1776	UINT64_C(`14680064`), // RSCrr
1777	UINT64_C(`14680064`), // RSCrsi
1778	UINT64_C(`14680080`), // RSCrsr
1779	UINT64_C(`101715728`), // SADD16
1780	UINT64_C(`101715856`), // SADD8
1781	UINT64_C(`101715760`), // SASX
1782	UINT64_C(`4118802544`), // SB
1783	UINT64_C(`46137344`), // SBCri
1784	UINT64_C(`12582912`), // SBCrr
1785	UINT64_C(`12582912`), // SBCrsi
1786	UINT64_C(`12582928`), // SBCrsr
1787	UINT64_C(`127926352`), // SBFX
1788	UINT64_C(`118550544`), // SDIV
1789	UINT64_C(`109055920`), // SEL
1790	UINT64_C(`4043374592`), // SETEND
1791	UINT64_C(`4044357632`), // SETPAN
1792	UINT64_C(`4060089408`), // SHA1C
1793	UINT64_C(`4088988352`), // SHA1H
1794	UINT64_C(`4062186560`), // SHA1M
1795	UINT64_C(`4061137984`), // SHA1P
1796	UINT64_C(`4063235136`), // SHA1SU0
1797	UINT64_C(`4089054080`), // SHA1SU1
1798	UINT64_C(`4076866624`), // SHA256H
1799	UINT64_C(`4077915200`), // SHA256H2
1800	UINT64_C(`4089054144`), // SHA256SU0
1801	UINT64_C(`4078963776`), // SHA256SU1
1802	UINT64_C(`103812880`), // SHADD16
1803	UINT64_C(`103813008`), // SHADD8
1804	UINT64_C(`103812912`), // SHASX
1805	UINT64_C(`103812944`), // SHSAX
1806	UINT64_C(`103812976`), // SHSUB16
1807	UINT64_C(`103813104`), // SHSUB8
1808	UINT64_C(`23068784`), // SMC
1809	UINT64_C(`16777344`), // SMLABB
1810	UINT64_C(`16777408`), // SMLABT
1811	UINT64_C(`117440528`), // SMLAD
1812	UINT64_C(`117440560`), // SMLADX
1813	UINT64_C(`14680208`), // SMLAL
1814	UINT64_C(`20971648`), // SMLALBB
1815	UINT64_C(`20971712`), // SMLALBT
1816	UINT64_C(`121634832`), // SMLALD
1817	UINT64_C(`121634864`), // SMLALDX
1818	UINT64_C(`20971680`), // SMLALTB
1819	UINT64_C(`20971744`), // SMLALTT
1820	UINT64_C(`16777376`), // SMLATB
1821	UINT64_C(`16777440`), // SMLATT
1822	UINT64_C(`18874496`), // SMLAWB
1823	UINT64_C(`18874560`), // SMLAWT
1824	UINT64_C(`117440592`), // SMLSD
1825	UINT64_C(`117440624`), // SMLSDX
1826	UINT64_C(`121634896`), // SMLSLD
1827	UINT64_C(`121634928`), // SMLSLDX
1828	UINT64_C(`122683408`), // SMMLA
1829	UINT64_C(`122683440`), // SMMLAR
1830	UINT64_C(`122683600`), // SMMLS
1831	UINT64_C(`122683632`), // SMMLSR
1832	UINT64_C(`122744848`), // SMMUL
1833	UINT64_C(`122744880`), // SMMULR
1834	UINT64_C(`117501968`), // SMUAD
1835	UINT64_C(`117502000`), // SMUADX
1836	UINT64_C(`23068800`), // SMULBB
1837	UINT64_C(`23068864`), // SMULBT
1838	UINT64_C(`12583056`), // SMULL
1839	UINT64_C(`23068832`), // SMULTB
1840	UINT64_C(`23068896`), // SMULTT
1841	UINT64_C(`18874528`), // SMULWB
1842	UINT64_C(`18874592`), // SMULWT
1843	UINT64_C(`117502032`), // SMUSD
1844	UINT64_C(`117502064`), // SMUSDX
1845	UINT64_C(`4165797120`), // SRSDA
1846	UINT64_C(`4167894272`), // SRSDA_UPD
1847	UINT64_C(`4182574336`), // SRSDB
1848	UINT64_C(`4184671488`), // SRSDB_UPD
1849	UINT64_C(`4174185728`), // SRSIA
1850	UINT64_C(`4176282880`), // SRSIA_UPD
1851	UINT64_C(`4190962944`), // SRSIB
1852	UINT64_C(`4193060096`), // SRSIB_UPD
1853	UINT64_C(`111149072`), // SSAT
1854	UINT64_C(`111152944`), // SSAT16
1855	UINT64_C(`101715792`), // SSAX
1856	UINT64_C(`101715824`), // SSUB16
1857	UINT64_C(`101715952`), // SSUB8
1858	UINT64_C(`4248829952`), // STC2L_OFFSET
1859	UINT64_C(`4240441344`), // STC2L_OPTION
1860	UINT64_C(`4234149888`), // STC2L_POST
1861	UINT64_C(`4250927104`), // STC2L_PRE
1862	UINT64_C(`4244635648`), // STC2_OFFSET
1863	UINT64_C(`4236247040`), // STC2_OPTION
1864	UINT64_C(`4229955584`), // STC2_POST
1865	UINT64_C(`4246732800`), // STC2_PRE
1866	UINT64_C(`222298112`), // STCL_OFFSET
1867	UINT64_C(`213909504`), // STCL_OPTION
1868	UINT64_C(`207618048`), // STCL_POST
1869	UINT64_C(`224395264`), // STCL_PRE
1870	UINT64_C(`218103808`), // STC_OFFSET
1871	UINT64_C(`209715200`), // STC_OPTION
1872	UINT64_C(`203423744`), // STC_POST
1873	UINT64_C(`220200960`), // STC_PRE
1874	UINT64_C(`25230480`), // STL
1875	UINT64_C(`29424784`), // STLB
1876	UINT64_C(`25169552`), // STLEX
1877	UINT64_C(`29363856`), // STLEXB
1878	UINT64_C(`27266704`), // STLEXD
1879	UINT64_C(`31461008`), // STLEXH
1880	UINT64_C(`31521936`), // STLH
1881	UINT64_C(`134217728`), // STMDA
1882	UINT64_C(`136314880`), // STMDA_UPD
1883	UINT64_C(`150994944`), // STMDB
1884	UINT64_C(`153092096`), // STMDB_UPD
1885	UINT64_C(`142606336`), // STMIA
1886	UINT64_C(`144703488`), // STMIA_UPD
1887	UINT64_C(`159383552`), // STMIB
1888	UINT64_C(`161480704`), // STMIB_UPD
1889	UINT64_C(`73400320`), // STRBT_POST_IMM
1890	UINT64_C(`106954752`), // STRBT_POST_REG
1891	UINT64_C(`71303168`), // STRB_POST_IMM
1892	UINT64_C(`104857600`), // STRB_POST_REG
1893	UINT64_C(`90177536`), // STRB_PRE_IMM
1894	UINT64_C(`123731968`), // STRB_PRE_REG
1895	UINT64_C(`88080384`), // STRBi12
1896	UINT64_C(`121634816`), // STRBrs
1897	UINT64_C(`16777456`), // STRD
1898	UINT64_C(`240`), // STRD_POST
1899	UINT64_C(`18874608`), // STRD_PRE
1900	UINT64_C(`25169808`), // STREX
1901	UINT64_C(`29364112`), // STREXB
1902	UINT64_C(`27266960`), // STREXD
1903	UINT64_C(`31461264`), // STREXH
1904	UINT64_C(`16777392`), // STRH
1905	UINT64_C(`6291632`), // STRHTi
1906	UINT64_C(`2097328`), // STRHTr
1907	UINT64_C(`176`), // STRH_POST
1908	UINT64_C(`18874544`), // STRH_PRE
1909	UINT64_C(`69206016`), // STRT_POST_IMM
1910	UINT64_C(`102760448`), // STRT_POST_REG
1911	UINT64_C(`67108864`), // STR_POST_IMM
1912	UINT64_C(`100663296`), // STR_POST_REG
1913	UINT64_C(`85983232`), // STR_PRE_IMM
1914	UINT64_C(`119537664`), // STR_PRE_REG
1915	UINT64_C(`83886080`), // STRi12
1916	UINT64_C(`117440512`), // STRrs
1917	UINT64_C(`37748736`), // SUBri
1918	UINT64_C(`4194304`), // SUBrr
1919	UINT64_C(`4194304`), // SUBrsi
1920	UINT64_C(`4194320`), // SUBrsr
1921	UINT64_C(`251658240`), // SVC
1922	UINT64_C(`16777360`), // SWP
1923	UINT64_C(`20971664`), // SWPB
1924	UINT64_C(`111149168`), // SXTAB
1925	UINT64_C(`109052016`), // SXTAB16
1926	UINT64_C(`112197744`), // SXTAH
1927	UINT64_C(`112132208`), // SXTB
1928	UINT64_C(`110035056`), // SXTB16
1929	UINT64_C(`113180784`), // SXTH
1930	UINT64_C(`53477376`), // TEQri
1931	UINT64_C(`19922944`), // TEQrr
1932	UINT64_C(`19922944`), // TEQrsi
1933	UINT64_C(`19922960`), // TEQrsr
1934	UINT64_C(`3892305662`), // TRAP
1935	UINT64_C(`3892240112`), // TRAPNaCl
1936	UINT64_C(`3810586642`), // TSB
1937	UINT64_C(`51380224`), // TSTri
1938	UINT64_C(`17825792`), // TSTrr
1939	UINT64_C(`17825792`), // TSTrsi
1940	UINT64_C(`17825808`), // TSTrsr
1941	UINT64_C(`105910032`), // UADD16
1942	UINT64_C(`105910160`), // UADD8
1943	UINT64_C(`105910064`), // UASX
1944	UINT64_C(`132120656`), // UBFX
1945	UINT64_C(`3891265776`), // UDF
1946	UINT64_C(`120647696`), // UDIV
1947	UINT64_C(`108007184`), // UHADD16
1948	UINT64_C(`108007312`), // UHADD8
1949	UINT64_C(`108007216`), // UHASX
1950	UINT64_C(`108007248`), // UHSAX
1951	UINT64_C(`108007280`), // UHSUB16
1952	UINT64_C(`108007408`), // UHSUB8
1953	UINT64_C(`4194448`), // UMAAL
1954	UINT64_C(`10485904`), // UMLAL
1955	UINT64_C(`8388752`), // UMULL
1956	UINT64_C(`106958608`), // UQADD16
1957	UINT64_C(`106958736`), // UQADD8
1958	UINT64_C(`106958640`), // UQASX
1959	UINT64_C(`106958672`), // UQSAX
1960	UINT64_C(`106958704`), // UQSUB16
1961	UINT64_C(`106958832`), // UQSUB8
1962	UINT64_C(`125890576`), // USAD8
1963	UINT64_C(`125829136`), // USADA8
1964	UINT64_C(`115343376`), // USAT
1965	UINT64_C(`115347248`), // USAT16
1966	UINT64_C(`105910096`), // USAX
1967	UINT64_C(`105910128`), // USUB16
1968	UINT64_C(`105910256`), // USUB8
1969	UINT64_C(`115343472`), // UXTAB
1970	UINT64_C(`113246320`), // UXTAB16
1971	UINT64_C(`116392048`), // UXTAH
1972	UINT64_C(`116326512`), // UXTB
1973	UINT64_C(`114229360`), // UXTB16
1974	UINT64_C(`117375088`), // UXTH
1975	UINT64_C(`4070573312`), // VABALsv2i64
1976	UINT64_C(`4069524736`), // VABALsv4i32
1977	UINT64_C(`4068476160`), // VABALsv8i16
1978	UINT64_C(`4087350528`), // VABALuv2i64
1979	UINT64_C(`4086301952`), // VABALuv4i32
1980	UINT64_C(`4085253376`), // VABALuv8i16
1981	UINT64_C(`4060088144`), // VABAsv16i8
1982	UINT64_C(`4062185232`), // VABAsv2i32
1983	UINT64_C(`4061136656`), // VABAsv4i16
1984	UINT64_C(`4062185296`), // VABAsv4i32
1985	UINT64_C(`4061136720`), // VABAsv8i16
1986	UINT64_C(`4060088080`), // VABAsv8i8
1987	UINT64_C(`4076865360`), // VABAuv16i8
1988	UINT64_C(`4078962448`), // VABAuv2i32
1989	UINT64_C(`4077913872`), // VABAuv4i16
1990	UINT64_C(`4078962512`), // VABAuv4i32
1991	UINT64_C(`4077913936`), // VABAuv8i16
1992	UINT64_C(`4076865296`), // VABAuv8i8
1993	UINT64_C(`4070573824`), // VABDLsv2i64
1994	UINT64_C(`4069525248`), // VABDLsv4i32
1995	UINT64_C(`4068476672`), // VABDLsv8i16
1996	UINT64_C(`4087351040`), // VABDLuv2i64
1997	UINT64_C(`4086302464`), // VABDLuv4i32
1998	UINT64_C(`4085253888`), // VABDLuv8i16
1999	UINT64_C(`4078963968`), // VABDfd
2000	UINT64_C(`4078964032`), // VABDfq
2001	UINT64_C(`4080012544`), // VABDhd
2002	UINT64_C(`4080012608`), // VABDhq
2003	UINT64_C(`4060088128`), // VABDsv16i8
2004	UINT64_C(`4062185216`), // VABDsv2i32
2005	UINT64_C(`4061136640`), // VABDsv4i16
2006	UINT64_C(`4062185280`), // VABDsv4i32
2007	UINT64_C(`4061136704`), // VABDsv8i16
2008	UINT64_C(`4060088064`), // VABDsv8i8
2009	UINT64_C(`4076865344`), // VABDuv16i8
2010	UINT64_C(`4078962432`), // VABDuv2i32
2011	UINT64_C(`4077913856`), // VABDuv4i16
2012	UINT64_C(`4078962496`), // VABDuv4i32
2013	UINT64_C(`4077913920`), // VABDuv8i16
2014	UINT64_C(`4076865280`), // VABDuv8i8
2015	UINT64_C(`246418368`), // VABSD
2016	UINT64_C(`246417856`), // VABSH
2017	UINT64_C(`246418112`), // VABSS
2018	UINT64_C(`4088989440`), // VABSfd
2019	UINT64_C(`4088989504`), // VABSfq
2020	UINT64_C(`4088727296`), // VABShd
2021	UINT64_C(`4088727360`), // VABShq
2022	UINT64_C(`4088464192`), // VABSv16i8
2023	UINT64_C(`4088988416`), // VABSv2i32
2024	UINT64_C(`4088726272`), // VABSv4i16
2025	UINT64_C(`4088988480`), // VABSv4i32
2026	UINT64_C(`4088726336`), // VABSv8i16
2027	UINT64_C(`4088464128`), // VABSv8i8
2028	UINT64_C(`4076867088`), // VACGEfd
2029	UINT64_C(`4076867152`), // VACGEfq
2030	UINT64_C(`4077915664`), // VACGEhd
2031	UINT64_C(`4077915728`), // VACGEhq
2032	UINT64_C(`4078964240`), // VACGTfd
2033	UINT64_C(`4078964304`), // VACGTfq
2034	UINT64_C(`4080012816`), // VACGThd
2035	UINT64_C(`4080012880`), // VACGThq
2036	UINT64_C(`238029568`), // VADDD
2037	UINT64_C(`238029056`), // VADDH
2038	UINT64_C(`4070573056`), // VADDHNv2i32
2039	UINT64_C(`4069524480`), // VADDHNv4i16
2040	UINT64_C(`4068475904`), // VADDHNv8i8
2041	UINT64_C(`4070572032`), // VADDLsv2i64
2042	UINT64_C(`4069523456`), // VADDLsv4i32
2043	UINT64_C(`4068474880`), // VADDLsv8i16
2044	UINT64_C(`4087349248`), // VADDLuv2i64
2045	UINT64_C(`4086300672`), // VADDLuv4i32
2046	UINT64_C(`4085252096`), // VADDLuv8i16
2047	UINT64_C(`238029312`), // VADDS
2048	UINT64_C(`4070572288`), // VADDWsv2i64
2049	UINT64_C(`4069523712`), // VADDWsv4i32
2050	UINT64_C(`4068475136`), // VADDWsv8i16
2051	UINT64_C(`4087349504`), // VADDWuv2i64
2052	UINT64_C(`4086300928`), // VADDWuv4i32
2053	UINT64_C(`4085252352`), // VADDWuv8i16
2054	UINT64_C(`4060089600`), // VADDfd
2055	UINT64_C(`4060089664`), // VADDfq
2056	UINT64_C(`4061138176`), // VADDhd
2057	UINT64_C(`4061138240`), // VADDhq
2058	UINT64_C(`4060088384`), // VADDv16i8
2059	UINT64_C(`4063234048`), // VADDv1i64
2060	UINT64_C(`4062185472`), // VADDv2i32
2061	UINT64_C(`4063234112`), // VADDv2i64
2062	UINT64_C(`4061136896`), // VADDv4i16
2063	UINT64_C(`4062185536`), // VADDv4i32
2064	UINT64_C(`4061136960`), // VADDv8i16
2065	UINT64_C(`4060088320`), // VADDv8i8
2066	UINT64_C(`4060086544`), // VANDd
2067	UINT64_C(`4060086608`), // VANDq
2068	UINT64_C(`4231006224`), // VBF16MALBQ
2069	UINT64_C(`4264560656`), // VBF16MALBQI
2070	UINT64_C(`4231006288`), // VBF16MALTQ
2071	UINT64_C(`4264560720`), // VBF16MALTQI
2072	UINT64_C(`4061135120`), // VBICd
2073	UINT64_C(`4068475184`), // VBICiv2i32
2074	UINT64_C(`4068477232`), // VBICiv4i16
2075	UINT64_C(`4068475248`), // VBICiv4i32
2076	UINT64_C(`4068477296`), // VBICiv8i16
2077	UINT64_C(`4061135184`), // VBICq
2078	UINT64_C(`4080009488`), // VBIFd
2079	UINT64_C(`4080009552`), // VBIFq
2080	UINT64_C(`4078960912`), // VBITd
2081	UINT64_C(`4078960976`), // VBITq
2082	UINT64_C(`4077912336`), // VBSLd
2083	UINT64_C(`4077912400`), // VBSLq
2084	UINT64_C(`0`), // VBSPd
2085	UINT64_C(`0`), // VBSPq
2086	UINT64_C(`4237297664`), // VCADDv2f32
2087	UINT64_C(`4236249088`), // VCADDv4f16
2088	UINT64_C(`4237297728`), // VCADDv4f32
2089	UINT64_C(`4236249152`), // VCADDv8f16
2090	UINT64_C(`4060089856`), // VCEQfd
2091	UINT64_C(`4060089920`), // VCEQfq
2092	UINT64_C(`4061138432`), // VCEQhd
2093	UINT64_C(`4061138496`), // VCEQhq
2094	UINT64_C(`4076865616`), // VCEQv16i8
2095	UINT64_C(`4078962704`), // VCEQv2i32
2096	UINT64_C(`4077914128`), // VCEQv4i16
2097	UINT64_C(`4078962768`), // VCEQv4i32
2098	UINT64_C(`4077914192`), // VCEQv8i16
2099	UINT64_C(`4076865552`), // VCEQv8i8
2100	UINT64_C(`4088463680`), // VCEQzv16i8
2101	UINT64_C(`4088988928`), // VCEQzv2f32
2102	UINT64_C(`4088987904`), // VCEQzv2i32
2103	UINT64_C(`4088726784`), // VCEQzv4f16
2104	UINT64_C(`4088988992`), // VCEQzv4f32
2105	UINT64_C(`4088725760`), // VCEQzv4i16
2106	UINT64_C(`4088987968`), // VCEQzv4i32
2107	UINT64_C(`4088726848`), // VCEQzv8f16
2108	UINT64_C(`4088725824`), // VCEQzv8i16
2109	UINT64_C(`4088463616`), // VCEQzv8i8
2110	UINT64_C(`4076867072`), // VCGEfd
2111	UINT64_C(`4076867136`), // VCGEfq
2112	UINT64_C(`4077915648`), // VCGEhd
2113	UINT64_C(`4077915712`), // VCGEhq
2114	UINT64_C(`4060087120`), // VCGEsv16i8
2115	UINT64_C(`4062184208`), // VCGEsv2i32
2116	UINT64_C(`4061135632`), // VCGEsv4i16
2117	UINT64_C(`4062184272`), // VCGEsv4i32
2118	UINT64_C(`4061135696`), // VCGEsv8i16
2119	UINT64_C(`4060087056`), // VCGEsv8i8
2120	UINT64_C(`4076864336`), // VCGEuv16i8
2121	UINT64_C(`4078961424`), // VCGEuv2i32
2122	UINT64_C(`4077912848`), // VCGEuv4i16
2123	UINT64_C(`4078961488`), // VCGEuv4i32
2124	UINT64_C(`4077912912`), // VCGEuv8i16
2125	UINT64_C(`4076864272`), // VCGEuv8i8
2126	UINT64_C(`4088463552`), // VCGEzv16i8
2127	UINT64_C(`4088988800`), // VCGEzv2f32
2128	UINT64_C(`4088987776`), // VCGEzv2i32
2129	UINT64_C(`4088726656`), // VCGEzv4f16
2130	UINT64_C(`4088988864`), // VCGEzv4f32
2131	UINT64_C(`4088725632`), // VCGEzv4i16
2132	UINT64_C(`4088987840`), // VCGEzv4i32
2133	UINT64_C(`4088726720`), // VCGEzv8f16
2134	UINT64_C(`4088725696`), // VCGEzv8i16
2135	UINT64_C(`4088463488`), // VCGEzv8i8
2136	UINT64_C(`4078964224`), // VCGTfd
2137	UINT64_C(`4078964288`), // VCGTfq
2138	UINT64_C(`4080012800`), // VCGThd
2139	UINT64_C(`4080012864`), // VCGThq
2140	UINT64_C(`4060087104`), // VCGTsv16i8
2141	UINT64_C(`4062184192`), // VCGTsv2i32
2142	UINT64_C(`4061135616`), // VCGTsv4i16
2143	UINT64_C(`4062184256`), // VCGTsv4i32
2144	UINT64_C(`4061135680`), // VCGTsv8i16
2145	UINT64_C(`4060087040`), // VCGTsv8i8
2146	UINT64_C(`4076864320`), // VCGTuv16i8
2147	UINT64_C(`4078961408`), // VCGTuv2i32
2148	UINT64_C(`4077912832`), // VCGTuv4i16
2149	UINT64_C(`4078961472`), // VCGTuv4i32
2150	UINT64_C(`4077912896`), // VCGTuv8i16
2151	UINT64_C(`4076864256`), // VCGTuv8i8
2152	UINT64_C(`4088463424`), // VCGTzv16i8
2153	UINT64_C(`4088988672`), // VCGTzv2f32
2154	UINT64_C(`4088987648`), // VCGTzv2i32
2155	UINT64_C(`4088726528`), // VCGTzv4f16
2156	UINT64_C(`4088988736`), // VCGTzv4f32
2157	UINT64_C(`4088725504`), // VCGTzv4i16
2158	UINT64_C(`4088987712`), // VCGTzv4i32
2159	UINT64_C(`4088726592`), // VCGTzv8f16
2160	UINT64_C(`4088725568`), // VCGTzv8i16
2161	UINT64_C(`4088463360`), // VCGTzv8i8
2162	UINT64_C(`4088463808`), // VCLEzv16i8
2163	UINT64_C(`4088989056`), // VCLEzv2f32
2164	UINT64_C(`4088988032`), // VCLEzv2i32
2165	UINT64_C(`4088726912`), // VCLEzv4f16
2166	UINT64_C(`4088989120`), // VCLEzv4f32
2167	UINT64_C(`4088725888`), // VCLEzv4i16
2168	UINT64_C(`4088988096`), // VCLEzv4i32
2169	UINT64_C(`4088726976`), // VCLEzv8f16
2170	UINT64_C(`4088725952`), // VCLEzv8i16
2171	UINT64_C(`4088463744`), // VCLEzv8i8
2172	UINT64_C(`4088398912`), // VCLSv16i8
2173	UINT64_C(`4088923136`), // VCLSv2i32
2174	UINT64_C(`4088660992`), // VCLSv4i16
2175	UINT64_C(`4088923200`), // VCLSv4i32
2176	UINT64_C(`4088661056`), // VCLSv8i16
2177	UINT64_C(`4088398848`), // VCLSv8i8
2178	UINT64_C(`4088463936`), // VCLTzv16i8
2179	UINT64_C(`4088989184`), // VCLTzv2f32
2180	UINT64_C(`4088988160`), // VCLTzv2i32
2181	UINT64_C(`4088727040`), // VCLTzv4f16
2182	UINT64_C(`4088989248`), // VCLTzv4f32
2183	UINT64_C(`4088726016`), // VCLTzv4i16
2184	UINT64_C(`4088988224`), // VCLTzv4i32
2185	UINT64_C(`4088727104`), // VCLTzv8f16
2186	UINT64_C(`4088726080`), // VCLTzv8i16
2187	UINT64_C(`4088463872`), // VCLTzv8i8
2188	UINT64_C(`4088399040`), // VCLZv16i8
2189	UINT64_C(`4088923264`), // VCLZv2i32
2190	UINT64_C(`4088661120`), // VCLZv4i16
2191	UINT64_C(`4088923328`), // VCLZv4i32
2192	UINT64_C(`4088661184`), // VCLZv8i16
2193	UINT64_C(`4088398976`), // VCLZv8i8
2194	UINT64_C(`4231006208`), // VCMLAv2f32
2195	UINT64_C(`4269803520`), // VCMLAv2f32_indexed
2196	UINT64_C(`4229957632`), // VCMLAv4f16
2197	UINT64_C(`4261414912`), // VCMLAv4f16_indexed
2198	UINT64_C(`4231006272`), // VCMLAv4f32
2199	UINT64_C(`4269803584`), // VCMLAv4f32_indexed
2200	UINT64_C(`4229957696`), // VCMLAv8f16
2201	UINT64_C(`4261414976`), // VCMLAv8f16_indexed
2202	UINT64_C(`246680384`), // VCMPD
2203	UINT64_C(`246680512`), // VCMPED
2204	UINT64_C(`246680000`), // VCMPEH
2205	UINT64_C(`246680256`), // VCMPES
2206	UINT64_C(`246746048`), // VCMPEZD
2207	UINT64_C(`246745536`), // VCMPEZH
2208	UINT64_C(`246745792`), // VCMPEZS
2209	UINT64_C(`246679872`), // VCMPH
2210	UINT64_C(`246680128`), // VCMPS
2211	UINT64_C(`246745920`), // VCMPZD
2212	UINT64_C(`246745408`), // VCMPZH
2213	UINT64_C(`246745664`), // VCMPZS
2214	UINT64_C(`4088399104`), // VCNTd
2215	UINT64_C(`4088399168`), // VCNTq
2216	UINT64_C(`4089118720`), // VCVTANSDf
2217	UINT64_C(`4088856576`), // VCVTANSDh
2218	UINT64_C(`4089118784`), // VCVTANSQf
2219	UINT64_C(`4088856640`), // VCVTANSQh
2220	UINT64_C(`4089118848`), // VCVTANUDf
2221	UINT64_C(`4088856704`), // VCVTANUDh
2222	UINT64_C(`4089118912`), // VCVTANUQf
2223	UINT64_C(`4088856768`), // VCVTANUQh
2224	UINT64_C(`4273736640`), // VCVTASD
2225	UINT64_C(`4273736128`), // VCVTASH
2226	UINT64_C(`4273736384`), // VCVTASS
2227	UINT64_C(`4273736512`), // VCVTAUD
2228	UINT64_C(`4273736000`), // VCVTAUH
2229	UINT64_C(`4273736256`), // VCVTAUS
2230	UINT64_C(`246614848`), // VCVTBDH
2231	UINT64_C(`246549312`), // VCVTBHD
2232	UINT64_C(`246549056`), // VCVTBHS
2233	UINT64_C(`246614592`), // VCVTBSH
2234	UINT64_C(`246876864`), // VCVTDS
2235	UINT64_C(`4089119488`), // VCVTMNSDf
2236	UINT64_C(`4088857344`), // VCVTMNSDh
2237	UINT64_C(`4089119552`), // VCVTMNSQf
2238	UINT64_C(`4088857408`), // VCVTMNSQh
2239	UINT64_C(`4089119616`), // VCVTMNUDf
2240	UINT64_C(`4088857472`), // VCVTMNUDh
2241	UINT64_C(`4089119680`), // VCVTMNUQf
2242	UINT64_C(`4088857536`), // VCVTMNUQh
2243	UINT64_C(`4273933248`), // VCVTMSD
2244	UINT64_C(`4273932736`), // VCVTMSH
2245	UINT64_C(`4273932992`), // VCVTMSS
2246	UINT64_C(`4273933120`), // VCVTMUD
2247	UINT64_C(`4273932608`), // VCVTMUH
2248	UINT64_C(`4273932864`), // VCVTMUS
2249	UINT64_C(`4089118976`), // VCVTNNSDf
2250	UINT64_C(`4088856832`), // VCVTNNSDh
2251	UINT64_C(`4089119040`), // VCVTNNSQf
2252	UINT64_C(`4088856896`), // VCVTNNSQh
2253	UINT64_C(`4089119104`), // VCVTNNUDf
2254	UINT64_C(`4088856960`), // VCVTNNUDh
2255	UINT64_C(`4089119168`), // VCVTNNUQf
2256	UINT64_C(`4088857024`), // VCVTNNUQh
2257	UINT64_C(`4273802176`), // VCVTNSD
2258	UINT64_C(`4273801664`), // VCVTNSH
2259	UINT64_C(`4273801920`), // VCVTNSS
2260	UINT64_C(`4273802048`), // VCVTNUD
2261	UINT64_C(`4273801536`), // VCVTNUH
2262	UINT64_C(`4273801792`), // VCVTNUS
2263	UINT64_C(`4089119232`), // VCVTPNSDf
2264	UINT64_C(`4088857088`), // VCVTPNSDh
2265	UINT64_C(`4089119296`), // VCVTPNSQf
2266	UINT64_C(`4088857152`), // VCVTPNSQh
2267	UINT64_C(`4089119360`), // VCVTPNUDf
2268	UINT64_C(`4088857216`), // VCVTPNUDh
2269	UINT64_C(`4089119424`), // VCVTPNUQf
2270	UINT64_C(`4088857280`), // VCVTPNUQh
2271	UINT64_C(`4273867712`), // VCVTPSD
2272	UINT64_C(`4273867200`), // VCVTPSH
2273	UINT64_C(`4273867456`), // VCVTPSS
2274	UINT64_C(`4273867584`), // VCVTPUD
2275	UINT64_C(`4273867072`), // VCVTPUH
2276	UINT64_C(`4273867328`), // VCVTPUS
2277	UINT64_C(`246877120`), // VCVTSD
2278	UINT64_C(`246614976`), // VCVTTDH
2279	UINT64_C(`246549440`), // VCVTTHD
2280	UINT64_C(`246549184`), // VCVTTHS
2281	UINT64_C(`246614720`), // VCVTTSH
2282	UINT64_C(`4088792576`), // VCVTf2h
2283	UINT64_C(`4089120512`), // VCVTf2sd
2284	UINT64_C(`4089120576`), // VCVTf2sq
2285	UINT64_C(`4089120640`), // VCVTf2ud
2286	UINT64_C(`4089120704`), // VCVTf2uq
2287	UINT64_C(`4068478736`), // VCVTf2xsd
2288	UINT64_C(`4068478800`), // VCVTf2xsq
2289	UINT64_C(`4085255952`), // VCVTf2xud
2290	UINT64_C(`4085256016`), // VCVTf2xuq
2291	UINT64_C(`4088792832`), // VCVTh2f
2292	UINT64_C(`4088858368`), // VCVTh2sd
2293	UINT64_C(`4088858432`), // VCVTh2sq
2294	UINT64_C(`4088858496`), // VCVTh2ud
2295	UINT64_C(`4088858560`), // VCVTh2uq
2296	UINT64_C(`4068478224`), // VCVTh2xsd
2297	UINT64_C(`4068478288`), // VCVTh2xsq
2298	UINT64_C(`4085255440`), // VCVTh2xud
2299	UINT64_C(`4085255504`), // VCVTh2xuq
2300	UINT64_C(`4089120256`), // VCVTs2fd
2301	UINT64_C(`4089120320`), // VCVTs2fq
2302	UINT64_C(`4088858112`), // VCVTs2hd
2303	UINT64_C(`4088858176`), // VCVTs2hq
2304	UINT64_C(`4089120384`), // VCVTu2fd
2305	UINT64_C(`4089120448`), // VCVTu2fq
2306	UINT64_C(`4088858240`), // VCVTu2hd
2307	UINT64_C(`4088858304`), // VCVTu2hq
2308	UINT64_C(`4068478480`), // VCVTxs2fd
2309	UINT64_C(`4068478544`), // VCVTxs2fq
2310	UINT64_C(`4068477968`), // VCVTxs2hd
2311	UINT64_C(`4068478032`), // VCVTxs2hq
2312	UINT64_C(`4085255696`), // VCVTxu2fd
2313	UINT64_C(`4085255760`), // VCVTxu2fq
2314	UINT64_C(`4085255184`), // VCVTxu2hd
2315	UINT64_C(`4085255248`), // VCVTxu2hq
2316	UINT64_C(`243272448`), // VDIVD
2317	UINT64_C(`243271936`), // VDIVH
2318	UINT64_C(`243272192`), // VDIVS
2319	UINT64_C(`243272496`), // VDUP16d
2320	UINT64_C(`245369648`), // VDUP16q
2321	UINT64_C(`243272464`), // VDUP32d
2322	UINT64_C(`245369616`), // VDUP32q
2323	UINT64_C(`247466768`), // VDUP8d
2324	UINT64_C(`249563920`), // VDUP8q
2325	UINT64_C(`4088531968`), // VDUPLN16d
2326	UINT64_C(`4088532032`), // VDUPLN16q
2327	UINT64_C(`4088663040`), // VDUPLN32d
2328	UINT64_C(`4088663104`), // VDUPLN32q
2329	UINT64_C(`4088466432`), // VDUPLN8d
2330	UINT64_C(`4088466496`), // VDUPLN8q
2331	UINT64_C(`4076863760`), // VEORd
2332	UINT64_C(`4076863824`), // VEORq
2333	UINT64_C(`4071620608`), // VEXTd16
2334	UINT64_C(`4071620608`), // VEXTd32
2335	UINT64_C(`4071620608`), // VEXTd8
2336	UINT64_C(`4071620672`), // VEXTq16
2337	UINT64_C(`4071620672`), // VEXTq32
2338	UINT64_C(`4071620672`), // VEXTq64
2339	UINT64_C(`4071620672`), // VEXTq8
2340	UINT64_C(`245369600`), // VFMAD
2341	UINT64_C(`245369088`), // VFMAH
2342	UINT64_C(`4229957648`), // VFMALD
2343	UINT64_C(`4261414928`), // VFMALDI
2344	UINT64_C(`4229957712`), // VFMALQ
2345	UINT64_C(`4261414992`), // VFMALQI
2346	UINT64_C(`245369344`), // VFMAS
2347	UINT64_C(`4060089360`), // VFMAfd
2348	UINT64_C(`4060089424`), // VFMAfq
2349	UINT64_C(`4061137936`), // VFMAhd
2350	UINT64_C(`4061138000`), // VFMAhq
2351	UINT64_C(`245369664`), // VFMSD
2352	UINT64_C(`245369152`), // VFMSH
2353	UINT64_C(`4238346256`), // VFMSLD
2354	UINT64_C(`4262463504`), // VFMSLDI
2355	UINT64_C(`4238346320`), // VFMSLQ
2356	UINT64_C(`4262463568`), // VFMSLQI
2357	UINT64_C(`245369408`), // VFMSS
2358	UINT64_C(`4062186512`), // VFMSfd
2359	UINT64_C(`4062186576`), // VFMSfq
2360	UINT64_C(`4063235088`), // VFMShd
2361	UINT64_C(`4063235152`), // VFMShq
2362	UINT64_C(`244321088`), // VFNMAD
2363	UINT64_C(`244320576`), // VFNMAH
2364	UINT64_C(`244320832`), // VFNMAS
2365	UINT64_C(`244321024`), // VFNMSD
2366	UINT64_C(`244320512`), // VFNMSH
2367	UINT64_C(`244320768`), // VFNMSS
2368	UINT64_C(`4269804288`), // VFP_VMAXNMD
2369	UINT64_C(`4269803776`), // VFP_VMAXNMH
2370	UINT64_C(`4269804032`), // VFP_VMAXNMS
2371	UINT64_C(`4269804352`), // VFP_VMINNMD
2372	UINT64_C(`4269803840`), // VFP_VMINNMH
2373	UINT64_C(`4269804096`), // VFP_VMINNMS
2374	UINT64_C(`235932432`), // VGETLNi32
2375	UINT64_C(`235932464`), // VGETLNs16
2376	UINT64_C(`240126736`), // VGETLNs8
2377	UINT64_C(`244321072`), // VGETLNu16
2378	UINT64_C(`248515344`), // VGETLNu8
2379	UINT64_C(`4060086336`), // VHADDsv16i8
2380	UINT64_C(`4062183424`), // VHADDsv2i32
2381	UINT64_C(`4061134848`), // VHADDsv4i16
2382	UINT64_C(`4062183488`), // VHADDsv4i32
2383	UINT64_C(`4061134912`), // VHADDsv8i16
2384	UINT64_C(`4060086272`), // VHADDsv8i8
2385	UINT64_C(`4076863552`), // VHADDuv16i8
2386	UINT64_C(`4078960640`), // VHADDuv2i32
2387	UINT64_C(`4077912064`), // VHADDuv4i16
2388	UINT64_C(`4078960704`), // VHADDuv4i32
2389	UINT64_C(`4077912128`), // VHADDuv8i16
2390	UINT64_C(`4076863488`), // VHADDuv8i8
2391	UINT64_C(`4060086848`), // VHSUBsv16i8
2392	UINT64_C(`4062183936`), // VHSUBsv2i32
2393	UINT64_C(`4061135360`), // VHSUBsv4i16
2394	UINT64_C(`4062184000`), // VHSUBsv4i32
2395	UINT64_C(`4061135424`), // VHSUBsv8i16
2396	UINT64_C(`4060086784`), // VHSUBsv8i8
2397	UINT64_C(`4076864064`), // VHSUBuv16i8
2398	UINT64_C(`4078961152`), // VHSUBuv2i32
2399	UINT64_C(`4077912576`), // VHSUBuv4i16
2400	UINT64_C(`4078961216`), // VHSUBuv4i32
2401	UINT64_C(`4077912640`), // VHSUBuv8i16
2402	UINT64_C(`4076864000`), // VHSUBuv8i8
2403	UINT64_C(`4272949952`), // VINSH
2404	UINT64_C(`247008192`), // VJCVT
2405	UINT64_C(`4104129615`), // VLD1DUPd16
2406	UINT64_C(`4104129613`), // VLD1DUPd16wb_fixed
2407	UINT64_C(`4104129600`), // VLD1DUPd16wb_register
2408	UINT64_C(`4104129679`), // VLD1DUPd32
2409	UINT64_C(`4104129677`), // VLD1DUPd32wb_fixed
2410	UINT64_C(`4104129664`), // VLD1DUPd32wb_register
2411	UINT64_C(`4104129551`), // VLD1DUPd8
2412	UINT64_C(`4104129549`), // VLD1DUPd8wb_fixed
2413	UINT64_C(`4104129536`), // VLD1DUPd8wb_register
2414	UINT64_C(`4104129647`), // VLD1DUPq16
2415	UINT64_C(`4104129645`), // VLD1DUPq16wb_fixed
2416	UINT64_C(`4104129632`), // VLD1DUPq16wb_register
2417	UINT64_C(`4104129711`), // VLD1DUPq32
2418	UINT64_C(`4104129709`), // VLD1DUPq32wb_fixed
2419	UINT64_C(`4104129696`), // VLD1DUPq32wb_register
2420	UINT64_C(`4104129583`), // VLD1DUPq8
2421	UINT64_C(`4104129581`), // VLD1DUPq8wb_fixed
2422	UINT64_C(`4104129568`), // VLD1DUPq8wb_register
2423	UINT64_C(`4104127503`), // VLD1LNd16
2424	UINT64_C(`4104127488`), // VLD1LNd16_UPD
2425	UINT64_C(`4104128527`), // VLD1LNd32
2426	UINT64_C(`4104128512`), // VLD1LNd32_UPD
2427	UINT64_C(`4104126479`), // VLD1LNd8
2428	UINT64_C(`4104126464`), // VLD1LNd8_UPD
2429	UINT64_C(`0`), // VLD1LNq16Pseudo
2430	UINT64_C(`0`), // VLD1LNq16Pseudo_UPD
2431	UINT64_C(`0`), // VLD1LNq32Pseudo
2432	UINT64_C(`0`), // VLD1LNq32Pseudo_UPD
2433	UINT64_C(`0`), // VLD1LNq8Pseudo
2434	UINT64_C(`0`), // VLD1LNq8Pseudo_UPD
2435	UINT64_C(`4095739727`), // VLD1d16
2436	UINT64_C(`4095738447`), // VLD1d16Q
2437	UINT64_C(`0`), // VLD1d16QPseudo
2438	UINT64_C(`4095738445`), // VLD1d16Qwb_fixed
2439	UINT64_C(`4095738432`), // VLD1d16Qwb_register
2440	UINT64_C(`4095739471`), // VLD1d16T
2441	UINT64_C(`0`), // VLD1d16TPseudo
2442	UINT64_C(`4095739469`), // VLD1d16Twb_fixed
2443	UINT64_C(`4095739456`), // VLD1d16Twb_register
2444	UINT64_C(`4095739725`), // VLD1d16wb_fixed
2445	UINT64_C(`4095739712`), // VLD1d16wb_register
2446	UINT64_C(`4095739791`), // VLD1d32
2447	UINT64_C(`4095738511`), // VLD1d32Q
2448	UINT64_C(`0`), // VLD1d32QPseudo
2449	UINT64_C(`4095738509`), // VLD1d32Qwb_fixed
2450	UINT64_C(`4095738496`), // VLD1d32Qwb_register
2451	UINT64_C(`4095739535`), // VLD1d32T
2452	UINT64_C(`0`), // VLD1d32TPseudo
2453	UINT64_C(`4095739533`), // VLD1d32Twb_fixed
2454	UINT64_C(`4095739520`), // VLD1d32Twb_register
2455	UINT64_C(`4095739789`), // VLD1d32wb_fixed
2456	UINT64_C(`4095739776`), // VLD1d32wb_register
2457	UINT64_C(`4095739855`), // VLD1d64
2458	UINT64_C(`4095738575`), // VLD1d64Q
2459	UINT64_C(`0`), // VLD1d64QPseudo
2460	UINT64_C(`0`), // VLD1d64QPseudoWB_fixed
2461	UINT64_C(`0`), // VLD1d64QPseudoWB_register
2462	UINT64_C(`4095738573`), // VLD1d64Qwb_fixed
2463	UINT64_C(`4095738560`), // VLD1d64Qwb_register
2464	UINT64_C(`4095739599`), // VLD1d64T
2465	UINT64_C(`0`), // VLD1d64TPseudo
2466	UINT64_C(`0`), // VLD1d64TPseudoWB_fixed
2467	UINT64_C(`0`), // VLD1d64TPseudoWB_register
2468	UINT64_C(`4095739597`), // VLD1d64Twb_fixed
2469	UINT64_C(`4095739584`), // VLD1d64Twb_register
2470	UINT64_C(`4095739853`), // VLD1d64wb_fixed
2471	UINT64_C(`4095739840`), // VLD1d64wb_register
2472	UINT64_C(`4095739663`), // VLD1d8
2473	UINT64_C(`4095738383`), // VLD1d8Q
2474	UINT64_C(`0`), // VLD1d8QPseudo
2475	UINT64_C(`4095738381`), // VLD1d8Qwb_fixed
2476	UINT64_C(`4095738368`), // VLD1d8Qwb_register
2477	UINT64_C(`4095739407`), // VLD1d8T
2478	UINT64_C(`0`), // VLD1d8TPseudo
2479	UINT64_C(`4095739405`), // VLD1d8Twb_fixed
2480	UINT64_C(`4095739392`), // VLD1d8Twb_register
2481	UINT64_C(`4095739661`), // VLD1d8wb_fixed
2482	UINT64_C(`4095739648`), // VLD1d8wb_register
2483	UINT64_C(`4095740495`), // VLD1q16
2484	UINT64_C(`0`), // VLD1q16HighQPseudo
2485	UINT64_C(`0`), // VLD1q16HighTPseudo
2486	UINT64_C(`0`), // VLD1q16LowQPseudo_UPD
2487	UINT64_C(`0`), // VLD1q16LowTPseudo_UPD
2488	UINT64_C(`4095740493`), // VLD1q16wb_fixed
2489	UINT64_C(`4095740480`), // VLD1q16wb_register
2490	UINT64_C(`4095740559`), // VLD1q32
2491	UINT64_C(`0`), // VLD1q32HighQPseudo
2492	UINT64_C(`0`), // VLD1q32HighTPseudo
2493	UINT64_C(`0`), // VLD1q32LowQPseudo_UPD
2494	UINT64_C(`0`), // VLD1q32LowTPseudo_UPD
2495	UINT64_C(`4095740557`), // VLD1q32wb_fixed
2496	UINT64_C(`4095740544`), // VLD1q32wb_register
2497	UINT64_C(`4095740623`), // VLD1q64
2498	UINT64_C(`0`), // VLD1q64HighQPseudo
2499	UINT64_C(`0`), // VLD1q64HighTPseudo
2500	UINT64_C(`0`), // VLD1q64LowQPseudo_UPD
2501	UINT64_C(`0`), // VLD1q64LowTPseudo_UPD
2502	UINT64_C(`4095740621`), // VLD1q64wb_fixed
2503	UINT64_C(`4095740608`), // VLD1q64wb_register
2504	UINT64_C(`4095740431`), // VLD1q8
2505	UINT64_C(`0`), // VLD1q8HighQPseudo
2506	UINT64_C(`0`), // VLD1q8HighTPseudo
2507	UINT64_C(`0`), // VLD1q8LowQPseudo_UPD
2508	UINT64_C(`0`), // VLD1q8LowTPseudo_UPD
2509	UINT64_C(`4095740429`), // VLD1q8wb_fixed
2510	UINT64_C(`4095740416`), // VLD1q8wb_register
2511	UINT64_C(`4104129871`), // VLD2DUPd16
2512	UINT64_C(`4104129869`), // VLD2DUPd16wb_fixed
2513	UINT64_C(`4104129856`), // VLD2DUPd16wb_register
2514	UINT64_C(`4104129903`), // VLD2DUPd16x2
2515	UINT64_C(`4104129901`), // VLD2DUPd16x2wb_fixed
2516	UINT64_C(`4104129888`), // VLD2DUPd16x2wb_register
2517	UINT64_C(`4104129935`), // VLD2DUPd32
2518	UINT64_C(`4104129933`), // VLD2DUPd32wb_fixed
2519	UINT64_C(`4104129920`), // VLD2DUPd32wb_register
2520	UINT64_C(`4104129967`), // VLD2DUPd32x2
2521	UINT64_C(`4104129965`), // VLD2DUPd32x2wb_fixed
2522	UINT64_C(`4104129952`), // VLD2DUPd32x2wb_register
2523	UINT64_C(`4104129807`), // VLD2DUPd8
2524	UINT64_C(`4104129805`), // VLD2DUPd8wb_fixed
2525	UINT64_C(`4104129792`), // VLD2DUPd8wb_register
2526	UINT64_C(`4104129839`), // VLD2DUPd8x2
2527	UINT64_C(`4104129837`), // VLD2DUPd8x2wb_fixed
2528	UINT64_C(`4104129824`), // VLD2DUPd8x2wb_register
2529	UINT64_C(`0`), // VLD2DUPq16EvenPseudo
2530	UINT64_C(`0`), // VLD2DUPq16OddPseudo
2531	UINT64_C(`0`), // VLD2DUPq32EvenPseudo
2532	UINT64_C(`0`), // VLD2DUPq32OddPseudo
2533	UINT64_C(`0`), // VLD2DUPq8EvenPseudo
2534	UINT64_C(`0`), // VLD2DUPq8OddPseudo
2535	UINT64_C(`4104127759`), // VLD2LNd16
2536	UINT64_C(`0`), // VLD2LNd16Pseudo
2537	UINT64_C(`0`), // VLD2LNd16Pseudo_UPD
2538	UINT64_C(`4104127744`), // VLD2LNd16_UPD
2539	UINT64_C(`4104128783`), // VLD2LNd32
2540	UINT64_C(`0`), // VLD2LNd32Pseudo
2541	UINT64_C(`0`), // VLD2LNd32Pseudo_UPD
2542	UINT64_C(`4104128768`), // VLD2LNd32_UPD
2543	UINT64_C(`4104126735`), // VLD2LNd8
2544	UINT64_C(`0`), // VLD2LNd8Pseudo
2545	UINT64_C(`0`), // VLD2LNd8Pseudo_UPD
2546	UINT64_C(`4104126720`), // VLD2LNd8_UPD
2547	UINT64_C(`4104127791`), // VLD2LNq16
2548	UINT64_C(`0`), // VLD2LNq16Pseudo
2549	UINT64_C(`0`), // VLD2LNq16Pseudo_UPD
2550	UINT64_C(`4104127776`), // VLD2LNq16_UPD
2551	UINT64_C(`4104128847`), // VLD2LNq32
2552	UINT64_C(`0`), // VLD2LNq32Pseudo
2553	UINT64_C(`0`), // VLD2LNq32Pseudo_UPD
2554	UINT64_C(`4104128832`), // VLD2LNq32_UPD
2555	UINT64_C(`4095740239`), // VLD2b16
2556	UINT64_C(`4095740237`), // VLD2b16wb_fixed
2557	UINT64_C(`4095740224`), // VLD2b16wb_register
2558	UINT64_C(`4095740303`), // VLD2b32
2559	UINT64_C(`4095740301`), // VLD2b32wb_fixed
2560	UINT64_C(`4095740288`), // VLD2b32wb_register
2561	UINT64_C(`4095740175`), // VLD2b8
2562	UINT64_C(`4095740173`), // VLD2b8wb_fixed
2563	UINT64_C(`4095740160`), // VLD2b8wb_register
2564	UINT64_C(`4095739983`), // VLD2d16
2565	UINT64_C(`4095739981`), // VLD2d16wb_fixed
2566	UINT64_C(`4095739968`), // VLD2d16wb_register
2567	UINT64_C(`4095740047`), // VLD2d32
2568	UINT64_C(`4095740045`), // VLD2d32wb_fixed
2569	UINT64_C(`4095740032`), // VLD2d32wb_register
2570	UINT64_C(`4095739919`), // VLD2d8
2571	UINT64_C(`4095739917`), // VLD2d8wb_fixed
2572	UINT64_C(`4095739904`), // VLD2d8wb_register
2573	UINT64_C(`4095738703`), // VLD2q16
2574	UINT64_C(`0`), // VLD2q16Pseudo
2575	UINT64_C(`0`), // VLD2q16PseudoWB_fixed
2576	UINT64_C(`0`), // VLD2q16PseudoWB_register
2577	UINT64_C(`4095738701`), // VLD2q16wb_fixed
2578	UINT64_C(`4095738688`), // VLD2q16wb_register
2579	UINT64_C(`4095738767`), // VLD2q32
2580	UINT64_C(`0`), // VLD2q32Pseudo
2581	UINT64_C(`0`), // VLD2q32PseudoWB_fixed
2582	UINT64_C(`0`), // VLD2q32PseudoWB_register
2583	UINT64_C(`4095738765`), // VLD2q32wb_fixed
2584	UINT64_C(`4095738752`), // VLD2q32wb_register
2585	UINT64_C(`4095738639`), // VLD2q8
2586	UINT64_C(`0`), // VLD2q8Pseudo
2587	UINT64_C(`0`), // VLD2q8PseudoWB_fixed
2588	UINT64_C(`0`), // VLD2q8PseudoWB_register
2589	UINT64_C(`4095738637`), // VLD2q8wb_fixed
2590	UINT64_C(`4095738624`), // VLD2q8wb_register
2591	UINT64_C(`4104130127`), // VLD3DUPd16
2592	UINT64_C(`0`), // VLD3DUPd16Pseudo
2593	UINT64_C(`0`), // VLD3DUPd16Pseudo_UPD
2594	UINT64_C(`4104130112`), // VLD3DUPd16_UPD
2595	UINT64_C(`4104130191`), // VLD3DUPd32
2596	UINT64_C(`0`), // VLD3DUPd32Pseudo
2597	UINT64_C(`0`), // VLD3DUPd32Pseudo_UPD
2598	UINT64_C(`4104130176`), // VLD3DUPd32_UPD
2599	UINT64_C(`4104130063`), // VLD3DUPd8
2600	UINT64_C(`0`), // VLD3DUPd8Pseudo
2601	UINT64_C(`0`), // VLD3DUPd8Pseudo_UPD
2602	UINT64_C(`4104130048`), // VLD3DUPd8_UPD
2603	UINT64_C(`4104130159`), // VLD3DUPq16
2604	UINT64_C(`0`), // VLD3DUPq16EvenPseudo
2605	UINT64_C(`0`), // VLD3DUPq16OddPseudo
2606	UINT64_C(`4104130144`), // VLD3DUPq16_UPD
2607	UINT64_C(`4104130223`), // VLD3DUPq32
2608	UINT64_C(`0`), // VLD3DUPq32EvenPseudo
2609	UINT64_C(`0`), // VLD3DUPq32OddPseudo
2610	UINT64_C(`4104130208`), // VLD3DUPq32_UPD
2611	UINT64_C(`4104130095`), // VLD3DUPq8
2612	UINT64_C(`0`), // VLD3DUPq8EvenPseudo
2613	UINT64_C(`0`), // VLD3DUPq8OddPseudo
2614	UINT64_C(`4104130080`), // VLD3DUPq8_UPD
2615	UINT64_C(`4104128015`), // VLD3LNd16
2616	UINT64_C(`0`), // VLD3LNd16Pseudo
2617	UINT64_C(`0`), // VLD3LNd16Pseudo_UPD
2618	UINT64_C(`4104128000`), // VLD3LNd16_UPD
2619	UINT64_C(`4104129039`), // VLD3LNd32
2620	UINT64_C(`0`), // VLD3LNd32Pseudo
2621	UINT64_C(`0`), // VLD3LNd32Pseudo_UPD
2622	UINT64_C(`4104129024`), // VLD3LNd32_UPD
2623	UINT64_C(`4104126991`), // VLD3LNd8
2624	UINT64_C(`0`), // VLD3LNd8Pseudo
2625	UINT64_C(`0`), // VLD3LNd8Pseudo_UPD
2626	UINT64_C(`4104126976`), // VLD3LNd8_UPD
2627	UINT64_C(`4104128047`), // VLD3LNq16
2628	UINT64_C(`0`), // VLD3LNq16Pseudo
2629	UINT64_C(`0`), // VLD3LNq16Pseudo_UPD
2630	UINT64_C(`4104128032`), // VLD3LNq16_UPD
2631	UINT64_C(`4104129103`), // VLD3LNq32
2632	UINT64_C(`0`), // VLD3LNq32Pseudo
2633	UINT64_C(`0`), // VLD3LNq32Pseudo_UPD
2634	UINT64_C(`4104129088`), // VLD3LNq32_UPD
2635	UINT64_C(`4095738959`), // VLD3d16
2636	UINT64_C(`0`), // VLD3d16Pseudo
2637	UINT64_C(`0`), // VLD3d16Pseudo_UPD
2638	UINT64_C(`4095738944`), // VLD3d16_UPD
2639	UINT64_C(`4095739023`), // VLD3d32
2640	UINT64_C(`0`), // VLD3d32Pseudo
2641	UINT64_C(`0`), // VLD3d32Pseudo_UPD
2642	UINT64_C(`4095739008`), // VLD3d32_UPD
2643	UINT64_C(`4095738895`), // VLD3d8
2644	UINT64_C(`0`), // VLD3d8Pseudo
2645	UINT64_C(`0`), // VLD3d8Pseudo_UPD
2646	UINT64_C(`4095738880`), // VLD3d8_UPD
2647	UINT64_C(`4095739215`), // VLD3q16
2648	UINT64_C(`0`), // VLD3q16Pseudo_UPD
2649	UINT64_C(`4095739200`), // VLD3q16_UPD
2650	UINT64_C(`0`), // VLD3q16oddPseudo
2651	UINT64_C(`0`), // VLD3q16oddPseudo_UPD
2652	UINT64_C(`4095739279`), // VLD3q32
2653	UINT64_C(`0`), // VLD3q32Pseudo_UPD
2654	UINT64_C(`4095739264`), // VLD3q32_UPD
2655	UINT64_C(`0`), // VLD3q32oddPseudo
2656	UINT64_C(`0`), // VLD3q32oddPseudo_UPD
2657	UINT64_C(`4095739151`), // VLD3q8
2658	UINT64_C(`0`), // VLD3q8Pseudo_UPD
2659	UINT64_C(`4095739136`), // VLD3q8_UPD
2660	UINT64_C(`0`), // VLD3q8oddPseudo
2661	UINT64_C(`0`), // VLD3q8oddPseudo_UPD
2662	UINT64_C(`4104130383`), // VLD4DUPd16
2663	UINT64_C(`0`), // VLD4DUPd16Pseudo
2664	UINT64_C(`0`), // VLD4DUPd16Pseudo_UPD
2665	UINT64_C(`4104130368`), // VLD4DUPd16_UPD
2666	UINT64_C(`4104130447`), // VLD4DUPd32
2667	UINT64_C(`0`), // VLD4DUPd32Pseudo
2668	UINT64_C(`0`), // VLD4DUPd32Pseudo_UPD
2669	UINT64_C(`4104130432`), // VLD4DUPd32_UPD
2670	UINT64_C(`4104130319`), // VLD4DUPd8
2671	UINT64_C(`0`), // VLD4DUPd8Pseudo
2672	UINT64_C(`0`), // VLD4DUPd8Pseudo_UPD
2673	UINT64_C(`4104130304`), // VLD4DUPd8_UPD
2674	UINT64_C(`4104130415`), // VLD4DUPq16
2675	UINT64_C(`0`), // VLD4DUPq16EvenPseudo
2676	UINT64_C(`0`), // VLD4DUPq16OddPseudo
2677	UINT64_C(`4104130400`), // VLD4DUPq16_UPD
2678	UINT64_C(`4104130479`), // VLD4DUPq32
2679	UINT64_C(`0`), // VLD4DUPq32EvenPseudo
2680	UINT64_C(`0`), // VLD4DUPq32OddPseudo
2681	UINT64_C(`4104130464`), // VLD4DUPq32_UPD
2682	UINT64_C(`4104130351`), // VLD4DUPq8
2683	UINT64_C(`0`), // VLD4DUPq8EvenPseudo
2684	UINT64_C(`0`), // VLD4DUPq8OddPseudo
2685	UINT64_C(`4104130336`), // VLD4DUPq8_UPD
2686	UINT64_C(`4104128271`), // VLD4LNd16
2687	UINT64_C(`0`), // VLD4LNd16Pseudo
2688	UINT64_C(`0`), // VLD4LNd16Pseudo_UPD
2689	UINT64_C(`4104128256`), // VLD4LNd16_UPD
2690	UINT64_C(`4104129295`), // VLD4LNd32
2691	UINT64_C(`0`), // VLD4LNd32Pseudo
2692	UINT64_C(`0`), // VLD4LNd32Pseudo_UPD
2693	UINT64_C(`4104129280`), // VLD4LNd32_UPD
2694	UINT64_C(`4104127247`), // VLD4LNd8
2695	UINT64_C(`0`), // VLD4LNd8Pseudo
2696	UINT64_C(`0`), // VLD4LNd8Pseudo_UPD
2697	UINT64_C(`4104127232`), // VLD4LNd8_UPD
2698	UINT64_C(`4104128303`), // VLD4LNq16
2699	UINT64_C(`0`), // VLD4LNq16Pseudo
2700	UINT64_C(`0`), // VLD4LNq16Pseudo_UPD
2701	UINT64_C(`4104128288`), // VLD4LNq16_UPD
2702	UINT64_C(`4104129359`), // VLD4LNq32
2703	UINT64_C(`0`), // VLD4LNq32Pseudo
2704	UINT64_C(`0`), // VLD4LNq32Pseudo_UPD
2705	UINT64_C(`4104129344`), // VLD4LNq32_UPD
2706	UINT64_C(`4095737935`), // VLD4d16
2707	UINT64_C(`0`), // VLD4d16Pseudo
2708	UINT64_C(`0`), // VLD4d16Pseudo_UPD
2709	UINT64_C(`4095737920`), // VLD4d16_UPD
2710	UINT64_C(`4095737999`), // VLD4d32
2711	UINT64_C(`0`), // VLD4d32Pseudo
2712	UINT64_C(`0`), // VLD4d32Pseudo_UPD
2713	UINT64_C(`4095737984`), // VLD4d32_UPD
2714	UINT64_C(`4095737871`), // VLD4d8
2715	UINT64_C(`0`), // VLD4d8Pseudo
2716	UINT64_C(`0`), // VLD4d8Pseudo_UPD
2717	UINT64_C(`4095737856`), // VLD4d8_UPD
2718	UINT64_C(`4095738191`), // VLD4q16
2719	UINT64_C(`0`), // VLD4q16Pseudo_UPD
2720	UINT64_C(`4095738176`), // VLD4q16_UPD
2721	UINT64_C(`0`), // VLD4q16oddPseudo
2722	UINT64_C(`0`), // VLD4q16oddPseudo_UPD
2723	UINT64_C(`4095738255`), // VLD4q32
2724	UINT64_C(`0`), // VLD4q32Pseudo_UPD
2725	UINT64_C(`4095738240`), // VLD4q32_UPD
2726	UINT64_C(`0`), // VLD4q32oddPseudo
2727	UINT64_C(`0`), // VLD4q32oddPseudo_UPD
2728	UINT64_C(`4095738127`), // VLD4q8
2729	UINT64_C(`0`), // VLD4q8Pseudo_UPD
2730	UINT64_C(`4095738112`), // VLD4q8_UPD
2731	UINT64_C(`0`), // VLD4q8oddPseudo
2732	UINT64_C(`0`), // VLD4q8oddPseudo_UPD
2733	UINT64_C(`221252352`), // VLDMDDB_UPD
2734	UINT64_C(`210766592`), // VLDMDIA
2735	UINT64_C(`212863744`), // VLDMDIA_UPD
2736	UINT64_C(`0`), // VLDMQIA
2737	UINT64_C(`221252096`), // VLDMSDB_UPD
2738	UINT64_C(`210766336`), // VLDMSIA
2739	UINT64_C(`212863488`), // VLDMSIA_UPD
2740	UINT64_C(`219155200`), // VLDRD
2741	UINT64_C(`219154688`), // VLDRH
2742	UINT64_C(`219154944`), // VLDRS
2743	UINT64_C(`223399808`), // VLDR_FPCXTNS_off
2744	UINT64_C(`208719744`), // VLDR_FPCXTNS_post
2745	UINT64_C(`225496960`), // VLDR_FPCXTNS_pre
2746	UINT64_C(`223408000`), // VLDR_FPCXTS_off
2747	UINT64_C(`208727936`), // VLDR_FPCXTS_post
2748	UINT64_C(`225505152`), // VLDR_FPCXTS_pre
2749	UINT64_C(`219172736`), // VLDR_FPSCR_NZCVQC_off
2750	UINT64_C(`204492672`), // VLDR_FPSCR_NZCVQC_post
2751	UINT64_C(`221269888`), // VLDR_FPSCR_NZCVQC_pre
2752	UINT64_C(`219164544`), // VLDR_FPSCR_off
2753	UINT64_C(`204484480`), // VLDR_FPSCR_post
2754	UINT64_C(`221261696`), // VLDR_FPSCR_pre
2755	UINT64_C(`223391616`), // VLDR_P0_off
2756	UINT64_C(`208711552`), // VLDR_P0_post
2757	UINT64_C(`225488768`), // VLDR_P0_pre
2758	UINT64_C(`223383424`), // VLDR_VPR_off
2759	UINT64_C(`208703360`), // VLDR_VPR_post
2760	UINT64_C(`225480576`), // VLDR_VPR_pre
2761	UINT64_C(`204474880`), // VLLDM
2762	UINT64_C(`203426304`), // VLSTM
2763	UINT64_C(`4060090112`), // VMAXfd
2764	UINT64_C(`4060090176`), // VMAXfq
2765	UINT64_C(`4061138688`), // VMAXhd
2766	UINT64_C(`4061138752`), // VMAXhq
2767	UINT64_C(`4060087872`), // VMAXsv16i8
2768	UINT64_C(`4062184960`), // VMAXsv2i32
2769	UINT64_C(`4061136384`), // VMAXsv4i16
2770	UINT64_C(`4062185024`), // VMAXsv4i32
2771	UINT64_C(`4061136448`), // VMAXsv8i16
2772	UINT64_C(`4060087808`), // VMAXsv8i8
2773	UINT64_C(`4076865088`), // VMAXuv16i8
2774	UINT64_C(`4078962176`), // VMAXuv2i32
2775	UINT64_C(`4077913600`), // VMAXuv4i16
2776	UINT64_C(`4078962240`), // VMAXuv4i32
2777	UINT64_C(`4077913664`), // VMAXuv8i16
2778	UINT64_C(`4076865024`), // VMAXuv8i8
2779	UINT64_C(`4062187264`), // VMINfd
2780	UINT64_C(`4062187328`), // VMINfq
2781	UINT64_C(`4063235840`), // VMINhd
2782	UINT64_C(`4063235904`), // VMINhq
2783	UINT64_C(`4060087888`), // VMINsv16i8
2784	UINT64_C(`4062184976`), // VMINsv2i32
2785	UINT64_C(`4061136400`), // VMINsv4i16
2786	UINT64_C(`4062185040`), // VMINsv4i32
2787	UINT64_C(`4061136464`), // VMINsv8i16
2788	UINT64_C(`4060087824`), // VMINsv8i8
2789	UINT64_C(`4076865104`), // VMINuv16i8
2790	UINT64_C(`4078962192`), // VMINuv2i32
2791	UINT64_C(`4077913616`), // VMINuv4i16
2792	UINT64_C(`4078962256`), // VMINuv4i32
2793	UINT64_C(`4077913680`), // VMINuv8i16
2794	UINT64_C(`4076865040`), // VMINuv8i8
2795	UINT64_C(`234883840`), // VMLAD
2796	UINT64_C(`234883328`), // VMLAH
2797	UINT64_C(`4070572608`), // VMLALslsv2i32
2798	UINT64_C(`4069524032`), // VMLALslsv4i16
2799	UINT64_C(`4087349824`), // VMLALsluv2i32
2800	UINT64_C(`4086301248`), // VMLALsluv4i16
2801	UINT64_C(`4070574080`), // VMLALsv2i64
2802	UINT64_C(`4069525504`), // VMLALsv4i32
2803	UINT64_C(`4068476928`), // VMLALsv8i16
2804	UINT64_C(`4087351296`), // VMLALuv2i64
2805	UINT64_C(`4086302720`), // VMLALuv4i32
2806	UINT64_C(`4085254144`), // VMLALuv8i16
2807	UINT64_C(`234883584`), // VMLAS
2808	UINT64_C(`4060089616`), // VMLAfd
2809	UINT64_C(`4060089680`), // VMLAfq
2810	UINT64_C(`4061138192`), // VMLAhd
2811	UINT64_C(`4061138256`), // VMLAhq
2812	UINT64_C(`4070572352`), // VMLAslfd
2813	UINT64_C(`4087349568`), // VMLAslfq
2814	UINT64_C(`4069523776`), // VMLAslhd
2815	UINT64_C(`4086300992`), // VMLAslhq
2816	UINT64_C(`4070572096`), // VMLAslv2i32
2817	UINT64_C(`4069523520`), // VMLAslv4i16
2818	UINT64_C(`4087349312`), // VMLAslv4i32
2819	UINT64_C(`4086300736`), // VMLAslv8i16
2820	UINT64_C(`4060088640`), // VMLAv16i8
2821	UINT64_C(`4062185728`), // VMLAv2i32
2822	UINT64_C(`4061137152`), // VMLAv4i16
2823	UINT64_C(`4062185792`), // VMLAv4i32
2824	UINT64_C(`4061137216`), // VMLAv8i16
2825	UINT64_C(`4060088576`), // VMLAv8i8
2826	UINT64_C(`234883904`), // VMLSD
2827	UINT64_C(`234883392`), // VMLSH
2828	UINT64_C(`4070573632`), // VMLSLslsv2i32
2829	UINT64_C(`4069525056`), // VMLSLslsv4i16
2830	UINT64_C(`4087350848`), // VMLSLsluv2i32
2831	UINT64_C(`4086302272`), // VMLSLsluv4i16
2832	UINT64_C(`4070574592`), // VMLSLsv2i64
2833	UINT64_C(`4069526016`), // VMLSLsv4i32
2834	UINT64_C(`4068477440`), // VMLSLsv8i16
2835	UINT64_C(`4087351808`), // VMLSLuv2i64
2836	UINT64_C(`4086303232`), // VMLSLuv4i32
2837	UINT64_C(`4085254656`), // VMLSLuv8i16
2838	UINT64_C(`234883648`), // VMLSS
2839	UINT64_C(`4062186768`), // VMLSfd
2840	UINT64_C(`4062186832`), // VMLSfq
2841	UINT64_C(`4063235344`), // VMLShd
2842	UINT64_C(`4063235408`), // VMLShq
2843	UINT64_C(`4070573376`), // VMLSslfd
2844	UINT64_C(`4087350592`), // VMLSslfq
2845	UINT64_C(`4069524800`), // VMLSslhd
2846	UINT64_C(`4086302016`), // VMLSslhq
2847	UINT64_C(`4070573120`), // VMLSslv2i32
2848	UINT64_C(`4069524544`), // VMLSslv4i16
2849	UINT64_C(`4087350336`), // VMLSslv4i32
2850	UINT64_C(`4086301760`), // VMLSslv8i16
2851	UINT64_C(`4076865856`), // VMLSv16i8
2852	UINT64_C(`4078962944`), // VMLSv2i32
2853	UINT64_C(`4077914368`), // VMLSv4i16
2854	UINT64_C(`4078963008`), // VMLSv4i32
2855	UINT64_C(`4077914432`), // VMLSv8i16
2856	UINT64_C(`4076865792`), // VMLSv8i8
2857	UINT64_C(`4227861568`), // VMMLA
2858	UINT64_C(`246418240`), // VMOVD
2859	UINT64_C(`205523728`), // VMOVDRR
2860	UINT64_C(`4272949824`), // VMOVH
2861	UINT64_C(`234883344`), // VMOVHR
2862	UINT64_C(`4070574608`), // VMOVLsv2i64
2863	UINT64_C(`4069526032`), // VMOVLsv4i32
2864	UINT64_C(`4069001744`), // VMOVLsv8i16
2865	UINT64_C(`4087351824`), // VMOVLuv2i64
2866	UINT64_C(`4086303248`), // VMOVLuv4i32
2867	UINT64_C(`4085778960`), // VMOVLuv8i16
2868	UINT64_C(`4089053696`), // VMOVNv2i32
2869	UINT64_C(`4088791552`), // VMOVNv4i16
2870	UINT64_C(`4088529408`), // VMOVNv8i8
2871	UINT64_C(`235931920`), // VMOVRH
2872	UINT64_C(`206572304`), // VMOVRRD
2873	UINT64_C(`206572048`), // VMOVRRS
2874	UINT64_C(`235932176`), // VMOVRS
2875	UINT64_C(`246417984`), // VMOVS
2876	UINT64_C(`234883600`), // VMOVSR
2877	UINT64_C(`205523472`), // VMOVSRR
2878	UINT64_C(`4068478544`), // VMOVv16i8
2879	UINT64_C(`4068478512`), // VMOVv1i64
2880	UINT64_C(`4068478736`), // VMOVv2f32
2881	UINT64_C(`4068474896`), // VMOVv2i32
2882	UINT64_C(`4068478576`), // VMOVv2i64
2883	UINT64_C(`4068478800`), // VMOVv4f32
2884	UINT64_C(`4068476944`), // VMOVv4i16
2885	UINT64_C(`4068474960`), // VMOVv4i32
2886	UINT64_C(`4068477008`), // VMOVv8i16
2887	UINT64_C(`4068478480`), // VMOVv8i8
2888	UINT64_C(`250677776`), // VMRS
2889	UINT64_C(`251529744`), // VMRS_FPCXTNS
2890	UINT64_C(`251595280`), // VMRS_FPCXTS
2891	UINT64_C(`251136528`), // VMRS_FPEXC
2892	UINT64_C(`251202064`), // VMRS_FPINST
2893	UINT64_C(`251267600`), // VMRS_FPINST2
2894	UINT64_C(`250743312`), // VMRS_FPSCR_NZCVQC
2895	UINT64_C(`250612240`), // VMRS_FPSID
2896	UINT64_C(`251070992`), // VMRS_MVFR0
2897	UINT64_C(`251005456`), // VMRS_MVFR1
2898	UINT64_C(`250939920`), // VMRS_MVFR2
2899	UINT64_C(`251464208`), // VMRS_P0
2900	UINT64_C(`251398672`), // VMRS_VPR
2901	UINT64_C(`249629200`), // VMSR
2902	UINT64_C(`250481168`), // VMSR_FPCXTNS
2903	UINT64_C(`250546704`), // VMSR_FPCXTS
2904	UINT64_C(`250087952`), // VMSR_FPEXC
2905	UINT64_C(`250153488`), // VMSR_FPINST
2906	UINT64_C(`250219024`), // VMSR_FPINST2
2907	UINT64_C(`249694736`), // VMSR_FPSCR_NZCVQC
2908	UINT64_C(`249563664`), // VMSR_FPSID
2909	UINT64_C(`250415632`), // VMSR_P0
2910	UINT64_C(`250350096`), // VMSR_VPR
2911	UINT64_C(`236980992`), // VMULD
2912	UINT64_C(`236980480`), // VMULH
2913	UINT64_C(`4070575616`), // VMULLp64
2914	UINT64_C(`4068478464`), // VMULLp8
2915	UINT64_C(`4070574656`), // VMULLslsv2i32
2916	UINT64_C(`4069526080`), // VMULLslsv4i16
2917	UINT64_C(`4087351872`), // VMULLsluv2i32
2918	UINT64_C(`4086303296`), // VMULLsluv4i16
2919	UINT64_C(`4070575104`), // VMULLsv2i64
2920	UINT64_C(`4069526528`), // VMULLsv4i32
2921	UINT64_C(`4068477952`), // VMULLsv8i16
2922	UINT64_C(`4087352320`), // VMULLuv2i64
2923	UINT64_C(`4086303744`), // VMULLuv4i32
2924	UINT64_C(`4085255168`), // VMULLuv8i16
2925	UINT64_C(`236980736`), // VMULS
2926	UINT64_C(`4076866832`), // VMULfd
2927	UINT64_C(`4076866896`), // VMULfq
2928	UINT64_C(`4077915408`), // VMULhd
2929	UINT64_C(`4077915472`), // VMULhq
2930	UINT64_C(`4076865808`), // VMULpd
2931	UINT64_C(`4076865872`), // VMULpq
2932	UINT64_C(`4070574400`), // VMULslfd
2933	UINT64_C(`4087351616`), // VMULslfq
2934	UINT64_C(`4069525824`), // VMULslhd
2935	UINT64_C(`4086303040`), // VMULslhq
2936	UINT64_C(`4070574144`), // VMULslv2i32
2937	UINT64_C(`4069525568`), // VMULslv4i16
2938	UINT64_C(`4087351360`), // VMULslv4i32
2939	UINT64_C(`4086302784`), // VMULslv8i16
2940	UINT64_C(`4060088656`), // VMULv16i8
2941	UINT64_C(`4062185744`), // VMULv2i32
2942	UINT64_C(`4061137168`), // VMULv4i16
2943	UINT64_C(`4062185808`), // VMULv4i32
2944	UINT64_C(`4061137232`), // VMULv8i16
2945	UINT64_C(`4060088592`), // VMULv8i8
2946	UINT64_C(`4088399232`), // VMVNd
2947	UINT64_C(`4088399296`), // VMVNq
2948	UINT64_C(`4068474928`), // VMVNv2i32
2949	UINT64_C(`4068476976`), // VMVNv4i16
2950	UINT64_C(`4068474992`), // VMVNv4i32
2951	UINT64_C(`4068477040`), // VMVNv8i16
2952	UINT64_C(`246483776`), // VNEGD
2953	UINT64_C(`246483264`), // VNEGH
2954	UINT64_C(`246483520`), // VNEGS
2955	UINT64_C(`4088989632`), // VNEGf32q
2956	UINT64_C(`4088989568`), // VNEGfd
2957	UINT64_C(`4088727424`), // VNEGhd
2958	UINT64_C(`4088727488`), // VNEGhq
2959	UINT64_C(`4088726400`), // VNEGs16d
2960	UINT64_C(`4088726464`), // VNEGs16q
2961	UINT64_C(`4088988544`), // VNEGs32d
2962	UINT64_C(`4088988608`), // VNEGs32q
2963	UINT64_C(`4088464256`), // VNEGs8d
2964	UINT64_C(`4088464320`), // VNEGs8q
2965	UINT64_C(`235932480`), // VNMLAD
2966	UINT64_C(`235931968`), // VNMLAH
2967	UINT64_C(`235932224`), // VNMLAS
2968	UINT64_C(`235932416`), // VNMLSD
2969	UINT64_C(`235931904`), // VNMLSH
2970	UINT64_C(`235932160`), // VNMLSS
2971	UINT64_C(`236981056`), // VNMULD
2972	UINT64_C(`236980544`), // VNMULH
2973	UINT64_C(`236980800`), // VNMULS
2974	UINT64_C(`4063232272`), // VORNd
2975	UINT64_C(`4063232336`), // VORNq
2976	UINT64_C(`4062183696`), // VORRd
2977	UINT64_C(`4068475152`), // VORRiv2i32
2978	UINT64_C(`4068477200`), // VORRiv4i16
2979	UINT64_C(`4068475216`), // VORRiv4i32
2980	UINT64_C(`4068477264`), // VORRiv8i16
2981	UINT64_C(`4062183760`), // VORRq
2982	UINT64_C(`4088399424`), // VPADALsv16i8
2983	UINT64_C(`4088923648`), // VPADALsv2i32
2984	UINT64_C(`4088661504`), // VPADALsv4i16
2985	UINT64_C(`4088923712`), // VPADALsv4i32
2986	UINT64_C(`4088661568`), // VPADALsv8i16
2987	UINT64_C(`4088399360`), // VPADALsv8i8
2988	UINT64_C(`4088399552`), // VPADALuv16i8
2989	UINT64_C(`4088923776`), // VPADALuv2i32
2990	UINT64_C(`4088661632`), // VPADALuv4i16
2991	UINT64_C(`4088923840`), // VPADALuv4i32
2992	UINT64_C(`4088661696`), // VPADALuv8i16
2993	UINT64_C(`4088399488`), // VPADALuv8i8
2994	UINT64_C(`4088398400`), // VPADDLsv16i8
2995	UINT64_C(`4088922624`), // VPADDLsv2i32
2996	UINT64_C(`4088660480`), // VPADDLsv4i16
2997	UINT64_C(`4088922688`), // VPADDLsv4i32
2998	UINT64_C(`4088660544`), // VPADDLsv8i16
2999	UINT64_C(`4088398336`), // VPADDLsv8i8
3000	UINT64_C(`4088398528`), // VPADDLuv16i8
3001	UINT64_C(`4088922752`), // VPADDLuv2i32
3002	UINT64_C(`4088660608`), // VPADDLuv4i16
3003	UINT64_C(`4088922816`), // VPADDLuv4i32
3004	UINT64_C(`4088660672`), // VPADDLuv8i16
3005	UINT64_C(`4088398464`), // VPADDLuv8i8
3006	UINT64_C(`4076866816`), // VPADDf
3007	UINT64_C(`4077915392`), // VPADDh
3008	UINT64_C(`4061137680`), // VPADDi16
3009	UINT64_C(`4062186256`), // VPADDi32
3010	UINT64_C(`4060089104`), // VPADDi8
3011	UINT64_C(`4076867328`), // VPMAXf
3012	UINT64_C(`4077915904`), // VPMAXh
3013	UINT64_C(`4061137408`), // VPMAXs16
3014	UINT64_C(`4062185984`), // VPMAXs32
3015	UINT64_C(`4060088832`), // VPMAXs8
3016	UINT64_C(`4077914624`), // VPMAXu16
3017	UINT64_C(`4078963200`), // VPMAXu32
3018	UINT64_C(`4076866048`), // VPMAXu8
3019	UINT64_C(`4078964480`), // VPMINf
3020	UINT64_C(`4080013056`), // VPMINh
3021	UINT64_C(`4061137424`), // VPMINs16
3022	UINT64_C(`4062186000`), // VPMINs32
3023	UINT64_C(`4060088848`), // VPMINs8
3024	UINT64_C(`4077914640`), // VPMINu16
3025	UINT64_C(`4078963216`), // VPMINu32
3026	UINT64_C(`4076866064`), // VPMINu8
3027	UINT64_C(`4088399680`), // VQABSv16i8
3028	UINT64_C(`4088923904`), // VQABSv2i32
3029	UINT64_C(`4088661760`), // VQABSv4i16
3030	UINT64_C(`4088923968`), // VQABSv4i32
3031	UINT64_C(`4088661824`), // VQABSv8i16
3032	UINT64_C(`4088399616`), // VQABSv8i8
3033	UINT64_C(`4060086352`), // VQADDsv16i8
3034	UINT64_C(`4063232016`), // VQADDsv1i64
3035	UINT64_C(`4062183440`), // VQADDsv2i32
3036	UINT64_C(`4063232080`), // VQADDsv2i64
3037	UINT64_C(`4061134864`), // VQADDsv4i16
3038	UINT64_C(`4062183504`), // VQADDsv4i32
3039	UINT64_C(`4061134928`), // VQADDsv8i16
3040	UINT64_C(`4060086288`), // VQADDsv8i8
3041	UINT64_C(`4076863568`), // VQADDuv16i8
3042	UINT64_C(`4080009232`), // VQADDuv1i64
3043	UINT64_C(`4078960656`), // VQADDuv2i32
3044	UINT64_C(`4080009296`), // VQADDuv2i64
3045	UINT64_C(`4077912080`), // VQADDuv4i16
3046	UINT64_C(`4078960720`), // VQADDuv4i32
3047	UINT64_C(`4077912144`), // VQADDuv8i16
3048	UINT64_C(`4076863504`), // VQADDuv8i8
3049	UINT64_C(`4070572864`), // VQDMLALslv2i32
3050	UINT64_C(`4069524288`), // VQDMLALslv4i16
3051	UINT64_C(`4070574336`), // VQDMLALv2i64
3052	UINT64_C(`4069525760`), // VQDMLALv4i32
3053	UINT64_C(`4070573888`), // VQDMLSLslv2i32
3054	UINT64_C(`4069525312`), // VQDMLSLslv4i16
3055	UINT64_C(`4070574848`), // VQDMLSLv2i64
3056	UINT64_C(`4069526272`), // VQDMLSLv4i32
3057	UINT64_C(`4070575168`), // VQDMULHslv2i32
3058	UINT64_C(`4069526592`), // VQDMULHslv4i16
3059	UINT64_C(`4087352384`), // VQDMULHslv4i32
3060	UINT64_C(`4086303808`), // VQDMULHslv8i16
3061	UINT64_C(`4062186240`), // VQDMULHv2i32
3062	UINT64_C(`4061137664`), // VQDMULHv4i16
3063	UINT64_C(`4062186304`), // VQDMULHv4i32
3064	UINT64_C(`4061137728`), // VQDMULHv8i16
3065	UINT64_C(`4070574912`), // VQDMULLslv2i32
3066	UINT64_C(`4069526336`), // VQDMULLslv4i16
3067	UINT64_C(`4070575360`), // VQDMULLv2i64
3068	UINT64_C(`4069526784`), // VQDMULLv4i32
3069	UINT64_C(`4089053760`), // VQMOVNsuv2i32
3070	UINT64_C(`4088791616`), // VQMOVNsuv4i16
3071	UINT64_C(`4088529472`), // VQMOVNsuv8i8
3072	UINT64_C(`4089053824`), // VQMOVNsv2i32
3073	UINT64_C(`4088791680`), // VQMOVNsv4i16
3074	UINT64_C(`4088529536`), // VQMOVNsv8i8
3075	UINT64_C(`4089053888`), // VQMOVNuv2i32
3076	UINT64_C(`4088791744`), // VQMOVNuv4i16
3077	UINT64_C(`4088529600`), // VQMOVNuv8i8
3078	UINT64_C(`4088399808`), // VQNEGv16i8
3079	UINT64_C(`4088924032`), // VQNEGv2i32
3080	UINT64_C(`4088661888`), // VQNEGv4i16
3081	UINT64_C(`4088924096`), // VQNEGv4i32
3082	UINT64_C(`4088661952`), // VQNEGv8i16
3083	UINT64_C(`4088399744`), // VQNEGv8i8
3084	UINT64_C(`4070575680`), // VQRDMLAHslv2i32
3085	UINT64_C(`4069527104`), // VQRDMLAHslv4i16
3086	UINT64_C(`4087352896`), // VQRDMLAHslv4i32
3087	UINT64_C(`4086304320`), // VQRDMLAHslv8i16
3088	UINT64_C(`4078963472`), // VQRDMLAHv2i32
3089	UINT64_C(`4077914896`), // VQRDMLAHv4i16
3090	UINT64_C(`4078963536`), // VQRDMLAHv4i32
3091	UINT64_C(`4077914960`), // VQRDMLAHv8i16
3092	UINT64_C(`4070575936`), // VQRDMLSHslv2i32
3093	UINT64_C(`4069527360`), // VQRDMLSHslv4i16
3094	UINT64_C(`4087353152`), // VQRDMLSHslv4i32
3095	UINT64_C(`4086304576`), // VQRDMLSHslv8i16
3096	UINT64_C(`4078963728`), // VQRDMLSHv2i32
3097	UINT64_C(`4077915152`), // VQRDMLSHv4i16
3098	UINT64_C(`4078963792`), // VQRDMLSHv4i32
3099	UINT64_C(`4077915216`), // VQRDMLSHv8i16
3100	UINT64_C(`4070575424`), // VQRDMULHslv2i32
3101	UINT64_C(`4069526848`), // VQRDMULHslv4i16
3102	UINT64_C(`4087352640`), // VQRDMULHslv4i32
3103	UINT64_C(`4086304064`), // VQRDMULHslv8i16
3104	UINT64_C(`4078963456`), // VQRDMULHv2i32
3105	UINT64_C(`4077914880`), // VQRDMULHv4i16
3106	UINT64_C(`4078963520`), // VQRDMULHv4i32
3107	UINT64_C(`4077914944`), // VQRDMULHv8i16
3108	UINT64_C(`4060087632`), // VQRSHLsv16i8
3109	UINT64_C(`4063233296`), // VQRSHLsv1i64
3110	UINT64_C(`4062184720`), // VQRSHLsv2i32
3111	UINT64_C(`4063233360`), // VQRSHLsv2i64
3112	UINT64_C(`4061136144`), // VQRSHLsv4i16
3113	UINT64_C(`4062184784`), // VQRSHLsv4i32
3114	UINT64_C(`4061136208`), // VQRSHLsv8i16
3115	UINT64_C(`4060087568`), // VQRSHLsv8i8
3116	UINT64_C(`4076864848`), // VQRSHLuv16i8
3117	UINT64_C(`4080010512`), // VQRSHLuv1i64
3118	UINT64_C(`4078961936`), // VQRSHLuv2i32
3119	UINT64_C(`4080010576`), // VQRSHLuv2i64
3120	UINT64_C(`4077913360`), // VQRSHLuv4i16
3121	UINT64_C(`4078962000`), // VQRSHLuv4i32
3122	UINT64_C(`4077913424`), // VQRSHLuv8i16
3123	UINT64_C(`4076864784`), // VQRSHLuv8i8
3124	UINT64_C(`4070574416`), // VQRSHRNsv2i32
3125	UINT64_C(`4069525840`), // VQRSHRNsv4i16
3126	UINT64_C(`4069001552`), // VQRSHRNsv8i8
3127	UINT64_C(`4087351632`), // VQRSHRNuv2i32
3128	UINT64_C(`4086303056`), // VQRSHRNuv4i16
3129	UINT64_C(`4085778768`), // VQRSHRNuv8i8
3130	UINT64_C(`4087351376`), // VQRSHRUNv2i32
3131	UINT64_C(`4086302800`), // VQRSHRUNv4i16
3132	UINT64_C(`4085778512`), // VQRSHRUNv8i8
3133	UINT64_C(`4069001040`), // VQSHLsiv16i8
3134	UINT64_C(`4068476816`), // VQSHLsiv1i64
3135	UINT64_C(`4070573840`), // VQSHLsiv2i32
3136	UINT64_C(`4068476880`), // VQSHLsiv2i64
3137	UINT64_C(`4069525264`), // VQSHLsiv4i16
3138	UINT64_C(`4070573904`), // VQSHLsiv4i32
3139	UINT64_C(`4069525328`), // VQSHLsiv8i16
3140	UINT64_C(`4069000976`), // VQSHLsiv8i8
3141	UINT64_C(`4085778000`), // VQSHLsuv16i8
3142	UINT64_C(`4085253776`), // VQSHLsuv1i64
3143	UINT64_C(`4087350800`), // VQSHLsuv2i32
3144	UINT64_C(`4085253840`), // VQSHLsuv2i64
3145	UINT64_C(`4086302224`), // VQSHLsuv4i16
3146	UINT64_C(`4087350864`), // VQSHLsuv4i32
3147	UINT64_C(`4086302288`), // VQSHLsuv8i16
3148	UINT64_C(`4085777936`), // VQSHLsuv8i8
3149	UINT64_C(`4060087376`), // VQSHLsv16i8
3150	UINT64_C(`4063233040`), // VQSHLsv1i64
3151	UINT64_C(`4062184464`), // VQSHLsv2i32
3152	UINT64_C(`4063233104`), // VQSHLsv2i64
3153	UINT64_C(`4061135888`), // VQSHLsv4i16
3154	UINT64_C(`4062184528`), // VQSHLsv4i32
3155	UINT64_C(`4061135952`), // VQSHLsv8i16
3156	UINT64_C(`4060087312`), // VQSHLsv8i8
3157	UINT64_C(`4085778256`), // VQSHLuiv16i8
3158	UINT64_C(`4085254032`), // VQSHLuiv1i64
3159	UINT64_C(`4087351056`), // VQSHLuiv2i32
3160	UINT64_C(`4085254096`), // VQSHLuiv2i64
3161	UINT64_C(`4086302480`), // VQSHLuiv4i16
3162	UINT64_C(`4087351120`), // VQSHLuiv4i32
3163	UINT64_C(`4086302544`), // VQSHLuiv8i16
3164	UINT64_C(`4085778192`), // VQSHLuiv8i8
3165	UINT64_C(`4076864592`), // VQSHLuv16i8
3166	UINT64_C(`4080010256`), // VQSHLuv1i64
3167	UINT64_C(`4078961680`), // VQSHLuv2i32
3168	UINT64_C(`4080010320`), // VQSHLuv2i64
3169	UINT64_C(`4077913104`), // VQSHLuv4i16
3170	UINT64_C(`4078961744`), // VQSHLuv4i32
3171	UINT64_C(`4077913168`), // VQSHLuv8i16
3172	UINT64_C(`4076864528`), // VQSHLuv8i8
3173	UINT64_C(`4070574352`), // VQSHRNsv2i32
3174	UINT64_C(`4069525776`), // VQSHRNsv4i16
3175	UINT64_C(`4069001488`), // VQSHRNsv8i8
3176	UINT64_C(`4087351568`), // VQSHRNuv2i32
3177	UINT64_C(`4086302992`), // VQSHRNuv4i16
3178	UINT64_C(`4085778704`), // VQSHRNuv8i8
3179	UINT64_C(`4087351312`), // VQSHRUNv2i32
3180	UINT64_C(`4086302736`), // VQSHRUNv4i16
3181	UINT64_C(`4085778448`), // VQSHRUNv8i8
3182	UINT64_C(`4060086864`), // VQSUBsv16i8
3183	UINT64_C(`4063232528`), // VQSUBsv1i64
3184	UINT64_C(`4062183952`), // VQSUBsv2i32
3185	UINT64_C(`4063232592`), // VQSUBsv2i64
3186	UINT64_C(`4061135376`), // VQSUBsv4i16
3187	UINT64_C(`4062184016`), // VQSUBsv4i32
3188	UINT64_C(`4061135440`), // VQSUBsv8i16
3189	UINT64_C(`4060086800`), // VQSUBsv8i8
3190	UINT64_C(`4076864080`), // VQSUBuv16i8
3191	UINT64_C(`4080009744`), // VQSUBuv1i64
3192	UINT64_C(`4078961168`), // VQSUBuv2i32
3193	UINT64_C(`4080009808`), // VQSUBuv2i64
3194	UINT64_C(`4077912592`), // VQSUBuv4i16
3195	UINT64_C(`4078961232`), // VQSUBuv4i32
3196	UINT64_C(`4077912656`), // VQSUBuv8i16
3197	UINT64_C(`4076864016`), // VQSUBuv8i8
3198	UINT64_C(`4087350272`), // VRADDHNv2i32
3199	UINT64_C(`4086301696`), // VRADDHNv4i16
3200	UINT64_C(`4085253120`), // VRADDHNv8i8
3201	UINT64_C(`4089119744`), // VRECPEd
3202	UINT64_C(`4089120000`), // VRECPEfd
3203	UINT64_C(`4089120064`), // VRECPEfq
3204	UINT64_C(`4088857856`), // VRECPEhd
3205	UINT64_C(`4088857920`), // VRECPEhq
3206	UINT64_C(`4089119808`), // VRECPEq
3207	UINT64_C(`4060090128`), // VRECPSfd
3208	UINT64_C(`4060090192`), // VRECPSfq
3209	UINT64_C(`4061138704`), // VRECPShd
3210	UINT64_C(`4061138768`), // VRECPShq
3211	UINT64_C(`4088398080`), // VREV16d8
3212	UINT64_C(`4088398144`), // VREV16q8
3213	UINT64_C(`4088660096`), // VREV32d16
3214	UINT64_C(`4088397952`), // VREV32d8
3215	UINT64_C(`4088660160`), // VREV32q16
3216	UINT64_C(`4088398016`), // VREV32q8
3217	UINT64_C(`4088659968`), // VREV64d16
3218	UINT64_C(`4088922112`), // VREV64d32
3219	UINT64_C(`4088397824`), // VREV64d8
3220	UINT64_C(`4088660032`), // VREV64q16
3221	UINT64_C(`4088922176`), // VREV64q32
3222	UINT64_C(`4088397888`), // VREV64q8
3223	UINT64_C(`4060086592`), // VRHADDsv16i8
3224	UINT64_C(`4062183680`), // VRHADDsv2i32
3225	UINT64_C(`4061135104`), // VRHADDsv4i16
3226	UINT64_C(`4062183744`), // VRHADDsv4i32
3227	UINT64_C(`4061135168`), // VRHADDsv8i16
3228	UINT64_C(`4060086528`), // VRHADDsv8i8
3229	UINT64_C(`4076863808`), // VRHADDuv16i8
3230	UINT64_C(`4078960896`), // VRHADDuv2i32
3231	UINT64_C(`4077912320`), // VRHADDuv4i16
3232	UINT64_C(`4078960960`), // VRHADDuv4i32
3233	UINT64_C(`4077912384`), // VRHADDuv8i16
3234	UINT64_C(`4076863744`), // VRHADDuv8i8
3235	UINT64_C(`4273474368`), // VRINTAD
3236	UINT64_C(`4273473856`), // VRINTAH
3237	UINT64_C(`4089054464`), // VRINTANDf
3238	UINT64_C(`4088792320`), // VRINTANDh
3239	UINT64_C(`4089054528`), // VRINTANQf
3240	UINT64_C(`4088792384`), // VRINTANQh
3241	UINT64_C(`4273474112`), // VRINTAS
3242	UINT64_C(`4273670976`), // VRINTMD
3243	UINT64_C(`4273670464`), // VRINTMH
3244	UINT64_C(`4089054848`), // VRINTMNDf
3245	UINT64_C(`4088792704`), // VRINTMNDh
3246	UINT64_C(`4089054912`), // VRINTMNQf
3247	UINT64_C(`4088792768`), // VRINTMNQh
3248	UINT64_C(`4273670720`), // VRINTMS
3249	UINT64_C(`4273539904`), // VRINTND
3250	UINT64_C(`4273539392`), // VRINTNH
3251	UINT64_C(`4089054208`), // VRINTNNDf
3252	UINT64_C(`4088792064`), // VRINTNNDh
3253	UINT64_C(`4089054272`), // VRINTNNQf
3254	UINT64_C(`4088792128`), // VRINTNNQh
3255	UINT64_C(`4273539648`), // VRINTNS
3256	UINT64_C(`4273605440`), // VRINTPD
3257	UINT64_C(`4273604928`), // VRINTPH
3258	UINT64_C(`4089055104`), // VRINTPNDf
3259	UINT64_C(`4088792960`), // VRINTPNDh
3260	UINT64_C(`4089055168`), // VRINTPNQf
3261	UINT64_C(`4088793024`), // VRINTPNQh
3262	UINT64_C(`4273605184`), // VRINTPS
3263	UINT64_C(`246811456`), // VRINTRD
3264	UINT64_C(`246810944`), // VRINTRH
3265	UINT64_C(`246811200`), // VRINTRS
3266	UINT64_C(`246876992`), // VRINTXD
3267	UINT64_C(`246876480`), // VRINTXH
3268	UINT64_C(`4089054336`), // VRINTXNDf
3269	UINT64_C(`4088792192`), // VRINTXNDh
3270	UINT64_C(`4089054400`), // VRINTXNQf
3271	UINT64_C(`4088792256`), // VRINTXNQh
3272	UINT64_C(`246876736`), // VRINTXS
3273	UINT64_C(`246811584`), // VRINTZD
3274	UINT64_C(`246811072`), // VRINTZH
3275	UINT64_C(`4089054592`), // VRINTZNDf
3276	UINT64_C(`4088792448`), // VRINTZNDh
3277	UINT64_C(`4089054656`), // VRINTZNQf
3278	UINT64_C(`4088792512`), // VRINTZNQh
3279	UINT64_C(`246811328`), // VRINTZS
3280	UINT64_C(`4060087616`), // VRSHLsv16i8
3281	UINT64_C(`4063233280`), // VRSHLsv1i64
3282	UINT64_C(`4062184704`), // VRSHLsv2i32
3283	UINT64_C(`4063233344`), // VRSHLsv2i64
3284	UINT64_C(`4061136128`), // VRSHLsv4i16
3285	UINT64_C(`4062184768`), // VRSHLsv4i32
3286	UINT64_C(`4061136192`), // VRSHLsv8i16
3287	UINT64_C(`4060087552`), // VRSHLsv8i8
3288	UINT64_C(`4076864832`), // VRSHLuv16i8
3289	UINT64_C(`4080010496`), // VRSHLuv1i64
3290	UINT64_C(`4078961920`), // VRSHLuv2i32
3291	UINT64_C(`4080010560`), // VRSHLuv2i64
3292	UINT64_C(`4077913344`), // VRSHLuv4i16
3293	UINT64_C(`4078961984`), // VRSHLuv4i32
3294	UINT64_C(`4077913408`), // VRSHLuv8i16
3295	UINT64_C(`4076864768`), // VRSHLuv8i8
3296	UINT64_C(`4070574160`), // VRSHRNv2i32
3297	UINT64_C(`4069525584`), // VRSHRNv4i16
3298	UINT64_C(`4069001296`), // VRSHRNv8i8
3299	UINT64_C(`4068999760`), // VRSHRsv16i8
3300	UINT64_C(`4068475536`), // VRSHRsv1i64
3301	UINT64_C(`4070572560`), // VRSHRsv2i32
3302	UINT64_C(`4068475600`), // VRSHRsv2i64
3303	UINT64_C(`4069523984`), // VRSHRsv4i16
3304	UINT64_C(`4070572624`), // VRSHRsv4i32
3305	UINT64_C(`4069524048`), // VRSHRsv8i16
3306	UINT64_C(`4068999696`), // VRSHRsv8i8
3307	UINT64_C(`4085776976`), // VRSHRuv16i8
3308	UINT64_C(`4085252752`), // VRSHRuv1i64
3309	UINT64_C(`4087349776`), // VRSHRuv2i32
3310	UINT64_C(`4085252816`), // VRSHRuv2i64
3311	UINT64_C(`4086301200`), // VRSHRuv4i16
3312	UINT64_C(`4087349840`), // VRSHRuv4i32
3313	UINT64_C(`4086301264`), // VRSHRuv8i16
3314	UINT64_C(`4085776912`), // VRSHRuv8i8
3315	UINT64_C(`4089119872`), // VRSQRTEd
3316	UINT64_C(`4089120128`), // VRSQRTEfd
3317	UINT64_C(`4089120192`), // VRSQRTEfq
3318	UINT64_C(`4088857984`), // VRSQRTEhd
3319	UINT64_C(`4088858048`), // VRSQRTEhq
3320	UINT64_C(`4089119936`), // VRSQRTEq
3321	UINT64_C(`4062187280`), // VRSQRTSfd
3322	UINT64_C(`4062187344`), // VRSQRTSfq
3323	UINT64_C(`4063235856`), // VRSQRTShd
3324	UINT64_C(`4063235920`), // VRSQRTShq
3325	UINT64_C(`4069000016`), // VRSRAsv16i8
3326	UINT64_C(`4068475792`), // VRSRAsv1i64
3327	UINT64_C(`4070572816`), // VRSRAsv2i32
3328	UINT64_C(`4068475856`), // VRSRAsv2i64
3329	UINT64_C(`4069524240`), // VRSRAsv4i16
3330	UINT64_C(`4070572880`), // VRSRAsv4i32
3331	UINT64_C(`4069524304`), // VRSRAsv8i16
3332	UINT64_C(`4068999952`), // VRSRAsv8i8
3333	UINT64_C(`4085777232`), // VRSRAuv16i8
3334	UINT64_C(`4085253008`), // VRSRAuv1i64
3335	UINT64_C(`4087350032`), // VRSRAuv2i32
3336	UINT64_C(`4085253072`), // VRSRAuv2i64
3337	UINT64_C(`4086301456`), // VRSRAuv4i16
3338	UINT64_C(`4087350096`), // VRSRAuv4i32
3339	UINT64_C(`4086301520`), // VRSRAuv8i16
3340	UINT64_C(`4085777168`), // VRSRAuv8i8
3341	UINT64_C(`4087350784`), // VRSUBHNv2i32
3342	UINT64_C(`4086302208`), // VRSUBHNv4i16
3343	UINT64_C(`4085253632`), // VRSUBHNv8i8
3344	UINT64_C(`3969846016`), // VSCCLRMD
3345	UINT64_C(`3969845760`), // VSCCLRMS
3346	UINT64_C(`4229958912`), // VSDOTD
3347	UINT64_C(`4263513344`), // VSDOTDI
3348	UINT64_C(`4229958976`), // VSDOTQ
3349	UINT64_C(`4263513408`), // VSDOTQI
3350	UINT64_C(`4261415680`), // VSELEQD
3351	UINT64_C(`4261415168`), // VSELEQH
3352	UINT64_C(`4261415424`), // VSELEQS
3353	UINT64_C(`4263512832`), // VSELGED
3354	UINT64_C(`4263512320`), // VSELGEH
3355	UINT64_C(`4263512576`), // VSELGES
3356	UINT64_C(`4264561408`), // VSELGTD
3357	UINT64_C(`4264560896`), // VSELGTH
3358	UINT64_C(`4264561152`), // VSELGTS
3359	UINT64_C(`4262464256`), // VSELVSD
3360	UINT64_C(`4262463744`), // VSELVSH
3361	UINT64_C(`4262464000`), // VSELVSS
3362	UINT64_C(`234883888`), // VSETLNi16
3363	UINT64_C(`234883856`), // VSETLNi32
3364	UINT64_C(`239078160`), // VSETLNi8
3365	UINT64_C(`4088791808`), // VSHLLi16
3366	UINT64_C(`4089053952`), // VSHLLi32
3367	UINT64_C(`4088529664`), // VSHLLi8
3368	UINT64_C(`4070574608`), // VSHLLsv2i64
3369	UINT64_C(`4069526032`), // VSHLLsv4i32
3370	UINT64_C(`4069001744`), // VSHLLsv8i16
3371	UINT64_C(`4087351824`), // VSHLLuv2i64
3372	UINT64_C(`4086303248`), // VSHLLuv4i32
3373	UINT64_C(`4085778960`), // VSHLLuv8i16
3374	UINT64_C(`4069000528`), // VSHLiv16i8
3375	UINT64_C(`4068476304`), // VSHLiv1i64
3376	UINT64_C(`4070573328`), // VSHLiv2i32
3377	UINT64_C(`4068476368`), // VSHLiv2i64
3378	UINT64_C(`4069524752`), // VSHLiv4i16
3379	UINT64_C(`4070573392`), // VSHLiv4i32
3380	UINT64_C(`4069524816`), // VSHLiv8i16
3381	UINT64_C(`4069000464`), // VSHLiv8i8
3382	UINT64_C(`4060087360`), // VSHLsv16i8
3383	UINT64_C(`4063233024`), // VSHLsv1i64
3384	UINT64_C(`4062184448`), // VSHLsv2i32
3385	UINT64_C(`4063233088`), // VSHLsv2i64
3386	UINT64_C(`4061135872`), // VSHLsv4i16
3387	UINT64_C(`4062184512`), // VSHLsv4i32
3388	UINT64_C(`4061135936`), // VSHLsv8i16
3389	UINT64_C(`4060087296`), // VSHLsv8i8
3390	UINT64_C(`4076864576`), // VSHLuv16i8
3391	UINT64_C(`4080010240`), // VSHLuv1i64
3392	UINT64_C(`4078961664`), // VSHLuv2i32
3393	UINT64_C(`4080010304`), // VSHLuv2i64
3394	UINT64_C(`4077913088`), // VSHLuv4i16
3395	UINT64_C(`4078961728`), // VSHLuv4i32
3396	UINT64_C(`4077913152`), // VSHLuv8i16
3397	UINT64_C(`4076864512`), // VSHLuv8i8
3398	UINT64_C(`4070574096`), // VSHRNv2i32
3399	UINT64_C(`4069525520`), // VSHRNv4i16
3400	UINT64_C(`4069001232`), // VSHRNv8i8
3401	UINT64_C(`4068999248`), // VSHRsv16i8
3402	UINT64_C(`4068475024`), // VSHRsv1i64
3403	UINT64_C(`4070572048`), // VSHRsv2i32
3404	UINT64_C(`4068475088`), // VSHRsv2i64
3405	UINT64_C(`4069523472`), // VSHRsv4i16
3406	UINT64_C(`4070572112`), // VSHRsv4i32
3407	UINT64_C(`4069523536`), // VSHRsv8i16
3408	UINT64_C(`4068999184`), // VSHRsv8i8
3409	UINT64_C(`4085776464`), // VSHRuv16i8
3410	UINT64_C(`4085252240`), // VSHRuv1i64
3411	UINT64_C(`4087349264`), // VSHRuv2i32
3412	UINT64_C(`4085252304`), // VSHRuv2i64
3413	UINT64_C(`4086300688`), // VSHRuv4i16
3414	UINT64_C(`4087349328`), // VSHRuv4i32
3415	UINT64_C(`4086300752`), // VSHRuv8i16
3416	UINT64_C(`4085776400`), // VSHRuv8i8
3417	UINT64_C(`247073600`), // VSHTOD
3418	UINT64_C(`247073088`), // VSHTOH
3419	UINT64_C(`247073344`), // VSHTOS
3420	UINT64_C(`246942656`), // VSITOD
3421	UINT64_C(`246942144`), // VSITOH
3422	UINT64_C(`246942400`), // VSITOS
3423	UINT64_C(`4085777744`), // VSLIv16i8
3424	UINT64_C(`4085253520`), // VSLIv1i64
3425	UINT64_C(`4087350544`), // VSLIv2i32
3426	UINT64_C(`4085253584`), // VSLIv2i64
3427	UINT64_C(`4086301968`), // VSLIv4i16
3428	UINT64_C(`4087350608`), // VSLIv4i32
3429	UINT64_C(`4086302032`), // VSLIv8i16
3430	UINT64_C(`4085777680`), // VSLIv8i8
3431	UINT64_C(`247073728`), // VSLTOD
3432	UINT64_C(`247073216`), // VSLTOH
3433	UINT64_C(`247073472`), // VSLTOS
3434	UINT64_C(`4229958720`), // VSMMLA
3435	UINT64_C(`246483904`), // VSQRTD
3436	UINT64_C(`246483392`), // VSQRTH
3437	UINT64_C(`246483648`), // VSQRTS
3438	UINT64_C(`4068999504`), // VSRAsv16i8
3439	UINT64_C(`4068475280`), // VSRAsv1i64
3440	UINT64_C(`4070572304`), // VSRAsv2i32
3441	UINT64_C(`4068475344`), // VSRAsv2i64
3442	UINT64_C(`4069523728`), // VSRAsv4i16
3443	UINT64_C(`4070572368`), // VSRAsv4i32
3444	UINT64_C(`4069523792`), // VSRAsv8i16
3445	UINT64_C(`4068999440`), // VSRAsv8i8
3446	UINT64_C(`4085776720`), // VSRAuv16i8
3447	UINT64_C(`4085252496`), // VSRAuv1i64
3448	UINT64_C(`4087349520`), // VSRAuv2i32
3449	UINT64_C(`4085252560`), // VSRAuv2i64
3450	UINT64_C(`4086300944`), // VSRAuv4i16
3451	UINT64_C(`4087349584`), // VSRAuv4i32
3452	UINT64_C(`4086301008`), // VSRAuv8i16
3453	UINT64_C(`4085776656`), // VSRAuv8i8
3454	UINT64_C(`4085777488`), // VSRIv16i8
3455	UINT64_C(`4085253264`), // VSRIv1i64
3456	UINT64_C(`4087350288`), // VSRIv2i32
3457	UINT64_C(`4085253328`), // VSRIv2i64
3458	UINT64_C(`4086301712`), // VSRIv4i16
3459	UINT64_C(`4087350352`), // VSRIv4i32
3460	UINT64_C(`4086301776`), // VSRIv8i16
3461	UINT64_C(`4085777424`), // VSRIv8i8
3462	UINT64_C(`4102030351`), // VST1LNd16
3463	UINT64_C(`4102030336`), // VST1LNd16_UPD
3464	UINT64_C(`4102031375`), // VST1LNd32
3465	UINT64_C(`4102031360`), // VST1LNd32_UPD
3466	UINT64_C(`4102029327`), // VST1LNd8
3467	UINT64_C(`4102029312`), // VST1LNd8_UPD
3468	UINT64_C(`0`), // VST1LNq16Pseudo
3469	UINT64_C(`0`), // VST1LNq16Pseudo_UPD
3470	UINT64_C(`0`), // VST1LNq32Pseudo
3471	UINT64_C(`0`), // VST1LNq32Pseudo_UPD
3472	UINT64_C(`0`), // VST1LNq8Pseudo
3473	UINT64_C(`0`), // VST1LNq8Pseudo_UPD
3474	UINT64_C(`4093642575`), // VST1d16
3475	UINT64_C(`4093641295`), // VST1d16Q
3476	UINT64_C(`0`), // VST1d16QPseudo
3477	UINT64_C(`4093641293`), // VST1d16Qwb_fixed
3478	UINT64_C(`4093641280`), // VST1d16Qwb_register
3479	UINT64_C(`4093642319`), // VST1d16T
3480	UINT64_C(`0`), // VST1d16TPseudo
3481	UINT64_C(`4093642317`), // VST1d16Twb_fixed
3482	UINT64_C(`4093642304`), // VST1d16Twb_register
3483	UINT64_C(`4093642573`), // VST1d16wb_fixed
3484	UINT64_C(`4093642560`), // VST1d16wb_register
3485	UINT64_C(`4093642639`), // VST1d32
3486	UINT64_C(`4093641359`), // VST1d32Q
3487	UINT64_C(`0`), // VST1d32QPseudo
3488	UINT64_C(`4093641357`), // VST1d32Qwb_fixed
3489	UINT64_C(`4093641344`), // VST1d32Qwb_register
3490	UINT64_C(`4093642383`), // VST1d32T
3491	UINT64_C(`0`), // VST1d32TPseudo
3492	UINT64_C(`4093642381`), // VST1d32Twb_fixed
3493	UINT64_C(`4093642368`), // VST1d32Twb_register
3494	UINT64_C(`4093642637`), // VST1d32wb_fixed
3495	UINT64_C(`4093642624`), // VST1d32wb_register
3496	UINT64_C(`4093642703`), // VST1d64
3497	UINT64_C(`4093641423`), // VST1d64Q
3498	UINT64_C(`0`), // VST1d64QPseudo
3499	UINT64_C(`0`), // VST1d64QPseudoWB_fixed
3500	UINT64_C(`0`), // VST1d64QPseudoWB_register
3501	UINT64_C(`4093641421`), // VST1d64Qwb_fixed
3502	UINT64_C(`4093641408`), // VST1d64Qwb_register
3503	UINT64_C(`4093642447`), // VST1d64T
3504	UINT64_C(`0`), // VST1d64TPseudo
3505	UINT64_C(`0`), // VST1d64TPseudoWB_fixed
3506	UINT64_C(`0`), // VST1d64TPseudoWB_register
3507	UINT64_C(`4093642445`), // VST1d64Twb_fixed
3508	UINT64_C(`4093642432`), // VST1d64Twb_register
3509	UINT64_C(`4093642701`), // VST1d64wb_fixed
3510	UINT64_C(`4093642688`), // VST1d64wb_register
3511	UINT64_C(`4093642511`), // VST1d8
3512	UINT64_C(`4093641231`), // VST1d8Q
3513	UINT64_C(`0`), // VST1d8QPseudo
3514	UINT64_C(`4093641229`), // VST1d8Qwb_fixed
3515	UINT64_C(`4093641216`), // VST1d8Qwb_register
3516	UINT64_C(`4093642255`), // VST1d8T
3517	UINT64_C(`0`), // VST1d8TPseudo
3518	UINT64_C(`4093642253`), // VST1d8Twb_fixed
3519	UINT64_C(`4093642240`), // VST1d8Twb_register
3520	UINT64_C(`4093642509`), // VST1d8wb_fixed
3521	UINT64_C(`4093642496`), // VST1d8wb_register
3522	UINT64_C(`4093643343`), // VST1q16
3523	UINT64_C(`0`), // VST1q16HighQPseudo
3524	UINT64_C(`0`), // VST1q16HighTPseudo
3525	UINT64_C(`0`), // VST1q16LowQPseudo_UPD
3526	UINT64_C(`0`), // VST1q16LowTPseudo_UPD
3527	UINT64_C(`4093643341`), // VST1q16wb_fixed
3528	UINT64_C(`4093643328`), // VST1q16wb_register
3529	UINT64_C(`4093643407`), // VST1q32
3530	UINT64_C(`0`), // VST1q32HighQPseudo
3531	UINT64_C(`0`), // VST1q32HighTPseudo
3532	UINT64_C(`0`), // VST1q32LowQPseudo_UPD
3533	UINT64_C(`0`), // VST1q32LowTPseudo_UPD
3534	UINT64_C(`4093643405`), // VST1q32wb_fixed
3535	UINT64_C(`4093643392`), // VST1q32wb_register
3536	UINT64_C(`4093643471`), // VST1q64
3537	UINT64_C(`0`), // VST1q64HighQPseudo
3538	UINT64_C(`0`), // VST1q64HighTPseudo
3539	UINT64_C(`0`), // VST1q64LowQPseudo_UPD
3540	UINT64_C(`0`), // VST1q64LowTPseudo_UPD
3541	UINT64_C(`4093643469`), // VST1q64wb_fixed
3542	UINT64_C(`4093643456`), // VST1q64wb_register
3543	UINT64_C(`4093643279`), // VST1q8
3544	UINT64_C(`0`), // VST1q8HighQPseudo
3545	UINT64_C(`0`), // VST1q8HighTPseudo
3546	UINT64_C(`0`), // VST1q8LowQPseudo_UPD
3547	UINT64_C(`0`), // VST1q8LowTPseudo_UPD
3548	UINT64_C(`4093643277`), // VST1q8wb_fixed
3549	UINT64_C(`4093643264`), // VST1q8wb_register
3550	UINT64_C(`4102030607`), // VST2LNd16
3551	UINT64_C(`0`), // VST2LNd16Pseudo
3552	UINT64_C(`0`), // VST2LNd16Pseudo_UPD
3553	UINT64_C(`4102030592`), // VST2LNd16_UPD
3554	UINT64_C(`4102031631`), // VST2LNd32
3555	UINT64_C(`0`), // VST2LNd32Pseudo
3556	UINT64_C(`0`), // VST2LNd32Pseudo_UPD
3557	UINT64_C(`4102031616`), // VST2LNd32_UPD
3558	UINT64_C(`4102029583`), // VST2LNd8
3559	UINT64_C(`0`), // VST2LNd8Pseudo
3560	UINT64_C(`0`), // VST2LNd8Pseudo_UPD
3561	UINT64_C(`4102029568`), // VST2LNd8_UPD
3562	UINT64_C(`4102030639`), // VST2LNq16
3563	UINT64_C(`0`), // VST2LNq16Pseudo
3564	UINT64_C(`0`), // VST2LNq16Pseudo_UPD
3565	UINT64_C(`4102030624`), // VST2LNq16_UPD
3566	UINT64_C(`4102031695`), // VST2LNq32
3567	UINT64_C(`0`), // VST2LNq32Pseudo
3568	UINT64_C(`0`), // VST2LNq32Pseudo_UPD
3569	UINT64_C(`4102031680`), // VST2LNq32_UPD
3570	UINT64_C(`4093643087`), // VST2b16
3571	UINT64_C(`4093643085`), // VST2b16wb_fixed
3572	UINT64_C(`4093643072`), // VST2b16wb_register
3573	UINT64_C(`4093643151`), // VST2b32
3574	UINT64_C(`4093643149`), // VST2b32wb_fixed
3575	UINT64_C(`4093643136`), // VST2b32wb_register
3576	UINT64_C(`4093643023`), // VST2b8
3577	UINT64_C(`4093643021`), // VST2b8wb_fixed
3578	UINT64_C(`4093643008`), // VST2b8wb_register
3579	UINT64_C(`4093642831`), // VST2d16
3580	UINT64_C(`4093642829`), // VST2d16wb_fixed
3581	UINT64_C(`4093642816`), // VST2d16wb_register
3582	UINT64_C(`4093642895`), // VST2d32
3583	UINT64_C(`4093642893`), // VST2d32wb_fixed
3584	UINT64_C(`4093642880`), // VST2d32wb_register
3585	UINT64_C(`4093642767`), // VST2d8
3586	UINT64_C(`4093642765`), // VST2d8wb_fixed
3587	UINT64_C(`4093642752`), // VST2d8wb_register
3588	UINT64_C(`4093641551`), // VST2q16
3589	UINT64_C(`0`), // VST2q16Pseudo
3590	UINT64_C(`0`), // VST2q16PseudoWB_fixed
3591	UINT64_C(`0`), // VST2q16PseudoWB_register
3592	UINT64_C(`4093641549`), // VST2q16wb_fixed
3593	UINT64_C(`4093641536`), // VST2q16wb_register
3594	UINT64_C(`4093641615`), // VST2q32
3595	UINT64_C(`0`), // VST2q32Pseudo
3596	UINT64_C(`0`), // VST2q32PseudoWB_fixed
3597	UINT64_C(`0`), // VST2q32PseudoWB_register
3598	UINT64_C(`4093641613`), // VST2q32wb_fixed
3599	UINT64_C(`4093641600`), // VST2q32wb_register
3600	UINT64_C(`4093641487`), // VST2q8
3601	UINT64_C(`0`), // VST2q8Pseudo
3602	UINT64_C(`0`), // VST2q8PseudoWB_fixed
3603	UINT64_C(`0`), // VST2q8PseudoWB_register
3604	UINT64_C(`4093641485`), // VST2q8wb_fixed
3605	UINT64_C(`4093641472`), // VST2q8wb_register
3606	UINT64_C(`4102030863`), // VST3LNd16
3607	UINT64_C(`0`), // VST3LNd16Pseudo
3608	UINT64_C(`0`), // VST3LNd16Pseudo_UPD
3609	UINT64_C(`4102030848`), // VST3LNd16_UPD
3610	UINT64_C(`4102031887`), // VST3LNd32
3611	UINT64_C(`0`), // VST3LNd32Pseudo
3612	UINT64_C(`0`), // VST3LNd32Pseudo_UPD
3613	UINT64_C(`4102031872`), // VST3LNd32_UPD
3614	UINT64_C(`4102029839`), // VST3LNd8
3615	UINT64_C(`0`), // VST3LNd8Pseudo
3616	UINT64_C(`0`), // VST3LNd8Pseudo_UPD
3617	UINT64_C(`4102029824`), // VST3LNd8_UPD
3618	UINT64_C(`4102030895`), // VST3LNq16
3619	UINT64_C(`0`), // VST3LNq16Pseudo
3620	UINT64_C(`0`), // VST3LNq16Pseudo_UPD
3621	UINT64_C(`4102030880`), // VST3LNq16_UPD
3622	UINT64_C(`4102031951`), // VST3LNq32
3623	UINT64_C(`0`), // VST3LNq32Pseudo
3624	UINT64_C(`0`), // VST3LNq32Pseudo_UPD
3625	UINT64_C(`4102031936`), // VST3LNq32_UPD
3626	UINT64_C(`4093641807`), // VST3d16
3627	UINT64_C(`0`), // VST3d16Pseudo
3628	UINT64_C(`0`), // VST3d16Pseudo_UPD
3629	UINT64_C(`4093641792`), // VST3d16_UPD
3630	UINT64_C(`4093641871`), // VST3d32
3631	UINT64_C(`0`), // VST3d32Pseudo
3632	UINT64_C(`0`), // VST3d32Pseudo_UPD
3633	UINT64_C(`4093641856`), // VST3d32_UPD
3634	UINT64_C(`4093641743`), // VST3d8
3635	UINT64_C(`0`), // VST3d8Pseudo
3636	UINT64_C(`0`), // VST3d8Pseudo_UPD
3637	UINT64_C(`4093641728`), // VST3d8_UPD
3638	UINT64_C(`4093642063`), // VST3q16
3639	UINT64_C(`0`), // VST3q16Pseudo_UPD
3640	UINT64_C(`4093642048`), // VST3q16_UPD
3641	UINT64_C(`0`), // VST3q16oddPseudo
3642	UINT64_C(`0`), // VST3q16oddPseudo_UPD
3643	UINT64_C(`4093642127`), // VST3q32
3644	UINT64_C(`0`), // VST3q32Pseudo_UPD
3645	UINT64_C(`4093642112`), // VST3q32_UPD
3646	UINT64_C(`0`), // VST3q32oddPseudo
3647	UINT64_C(`0`), // VST3q32oddPseudo_UPD
3648	UINT64_C(`4093641999`), // VST3q8
3649	UINT64_C(`0`), // VST3q8Pseudo_UPD
3650	UINT64_C(`4093641984`), // VST3q8_UPD
3651	UINT64_C(`0`), // VST3q8oddPseudo
3652	UINT64_C(`0`), // VST3q8oddPseudo_UPD
3653	UINT64_C(`4102031119`), // VST4LNd16
3654	UINT64_C(`0`), // VST4LNd16Pseudo
3655	UINT64_C(`0`), // VST4LNd16Pseudo_UPD
3656	UINT64_C(`4102031104`), // VST4LNd16_UPD
3657	UINT64_C(`4102032143`), // VST4LNd32
3658	UINT64_C(`0`), // VST4LNd32Pseudo
3659	UINT64_C(`0`), // VST4LNd32Pseudo_UPD
3660	UINT64_C(`4102032128`), // VST4LNd32_UPD
3661	UINT64_C(`4102030095`), // VST4LNd8
3662	UINT64_C(`0`), // VST4LNd8Pseudo
3663	UINT64_C(`0`), // VST4LNd8Pseudo_UPD
3664	UINT64_C(`4102030080`), // VST4LNd8_UPD
3665	UINT64_C(`4102031151`), // VST4LNq16
3666	UINT64_C(`0`), // VST4LNq16Pseudo
3667	UINT64_C(`0`), // VST4LNq16Pseudo_UPD
3668	UINT64_C(`4102031136`), // VST4LNq16_UPD
3669	UINT64_C(`4102032207`), // VST4LNq32
3670	UINT64_C(`0`), // VST4LNq32Pseudo
3671	UINT64_C(`0`), // VST4LNq32Pseudo_UPD
3672	UINT64_C(`4102032192`), // VST4LNq32_UPD
3673	UINT64_C(`4093640783`), // VST4d16
3674	UINT64_C(`0`), // VST4d16Pseudo
3675	UINT64_C(`0`), // VST4d16Pseudo_UPD
3676	UINT64_C(`4093640768`), // VST4d16_UPD
3677	UINT64_C(`4093640847`), // VST4d32
3678	UINT64_C(`0`), // VST4d32Pseudo
3679	UINT64_C(`0`), // VST4d32Pseudo_UPD
3680	UINT64_C(`4093640832`), // VST4d32_UPD
3681	UINT64_C(`4093640719`), // VST4d8
3682	UINT64_C(`0`), // VST4d8Pseudo
3683	UINT64_C(`0`), // VST4d8Pseudo_UPD
3684	UINT64_C(`4093640704`), // VST4d8_UPD
3685	UINT64_C(`4093641039`), // VST4q16
3686	UINT64_C(`0`), // VST4q16Pseudo_UPD
3687	UINT64_C(`4093641024`), // VST4q16_UPD
3688	UINT64_C(`0`), // VST4q16oddPseudo
3689	UINT64_C(`0`), // VST4q16oddPseudo_UPD
3690	UINT64_C(`4093641103`), // VST4q32
3691	UINT64_C(`0`), // VST4q32Pseudo_UPD
3692	UINT64_C(`4093641088`), // VST4q32_UPD
3693	UINT64_C(`0`), // VST4q32oddPseudo
3694	UINT64_C(`0`), // VST4q32oddPseudo_UPD
3695	UINT64_C(`4093640975`), // VST4q8
3696	UINT64_C(`0`), // VST4q8Pseudo_UPD
3697	UINT64_C(`4093640960`), // VST4q8_UPD
3698	UINT64_C(`0`), // VST4q8oddPseudo
3699	UINT64_C(`0`), // VST4q8oddPseudo_UPD
3700	UINT64_C(`220203776`), // VSTMDDB_UPD
3701	UINT64_C(`209718016`), // VSTMDIA
3702	UINT64_C(`211815168`), // VSTMDIA_UPD
3703	UINT64_C(`0`), // VSTMQIA
3704	UINT64_C(`220203520`), // VSTMSDB_UPD
3705	UINT64_C(`209717760`), // VSTMSIA
3706	UINT64_C(`211814912`), // VSTMSIA_UPD
3707	UINT64_C(`218106624`), // VSTRD
3708	UINT64_C(`218106112`), // VSTRH
3709	UINT64_C(`218106368`), // VSTRS
3710	UINT64_C(`222351232`), // VSTR_FPCXTNS_off
3711	UINT64_C(`207671168`), // VSTR_FPCXTNS_post
3712	UINT64_C(`224448384`), // VSTR_FPCXTNS_pre
3713	UINT64_C(`222359424`), // VSTR_FPCXTS_off
3714	UINT64_C(`207679360`), // VSTR_FPCXTS_post
3715	UINT64_C(`224456576`), // VSTR_FPCXTS_pre
3716	UINT64_C(`218124160`), // VSTR_FPSCR_NZCVQC_off
3717	UINT64_C(`203444096`), // VSTR_FPSCR_NZCVQC_post
3718	UINT64_C(`220221312`), // VSTR_FPSCR_NZCVQC_pre
3719	UINT64_C(`218115968`), // VSTR_FPSCR_off
3720	UINT64_C(`203435904`), // VSTR_FPSCR_post
3721	UINT64_C(`220213120`), // VSTR_FPSCR_pre
3722	UINT64_C(`222343040`), // VSTR_P0_off
3723	UINT64_C(`207662976`), // VSTR_P0_post
3724	UINT64_C(`224440192`), // VSTR_P0_pre
3725	UINT64_C(`222334848`), // VSTR_VPR_off
3726	UINT64_C(`207654784`), // VSTR_VPR_post
3727	UINT64_C(`224432000`), // VSTR_VPR_pre
3728	UINT64_C(`238029632`), // VSUBD
3729	UINT64_C(`238029120`), // VSUBH
3730	UINT64_C(`4070573568`), // VSUBHNv2i32
3731	UINT64_C(`4069524992`), // VSUBHNv4i16
3732	UINT64_C(`4068476416`), // VSUBHNv8i8
3733	UINT64_C(`4070572544`), // VSUBLsv2i64
3734	UINT64_C(`4069523968`), // VSUBLsv4i32
3735	UINT64_C(`4068475392`), // VSUBLsv8i16
3736	UINT64_C(`4087349760`), // VSUBLuv2i64
3737	UINT64_C(`4086301184`), // VSUBLuv4i32
3738	UINT64_C(`4085252608`), // VSUBLuv8i16
3739	UINT64_C(`238029376`), // VSUBS
3740	UINT64_C(`4070572800`), // VSUBWsv2i64
3741	UINT64_C(`4069524224`), // VSUBWsv4i32
3742	UINT64_C(`4068475648`), // VSUBWsv8i16
3743	UINT64_C(`4087350016`), // VSUBWuv2i64
3744	UINT64_C(`4086301440`), // VSUBWuv4i32
3745	UINT64_C(`4085252864`), // VSUBWuv8i16
3746	UINT64_C(`4062186752`), // VSUBfd
3747	UINT64_C(`4062186816`), // VSUBfq
3748	UINT64_C(`4063235328`), // VSUBhd
3749	UINT64_C(`4063235392`), // VSUBhq
3750	UINT64_C(`4076865600`), // VSUBv16i8
3751	UINT64_C(`4080011264`), // VSUBv1i64
3752	UINT64_C(`4078962688`), // VSUBv2i32
3753	UINT64_C(`4080011328`), // VSUBv2i64
3754	UINT64_C(`4077914112`), // VSUBv4i16
3755	UINT64_C(`4078962752`), // VSUBv4i32
3756	UINT64_C(`4077914176`), // VSUBv8i16
3757	UINT64_C(`4076865536`), // VSUBv8i8
3758	UINT64_C(`4269804816`), // VSUDOTDI
3759	UINT64_C(`4269804880`), // VSUDOTQI
3760	UINT64_C(`4088528896`), // VSWPd
3761	UINT64_C(`4088528960`), // VSWPq
3762	UINT64_C(`4088399872`), // VTBL1
3763	UINT64_C(`4088400128`), // VTBL2
3764	UINT64_C(`4088400384`), // VTBL3
3765	UINT64_C(`0`), // VTBL3Pseudo
3766	UINT64_C(`4088400640`), // VTBL4
3767	UINT64_C(`0`), // VTBL4Pseudo
3768	UINT64_C(`4088399936`), // VTBX1
3769	UINT64_C(`4088400192`), // VTBX2
3770	UINT64_C(`4088400448`), // VTBX3
3771	UINT64_C(`0`), // VTBX3Pseudo
3772	UINT64_C(`4088400704`), // VTBX4
3773	UINT64_C(`0`), // VTBX4Pseudo
3774	UINT64_C(`247335744`), // VTOSHD
3775	UINT64_C(`247335232`), // VTOSHH
3776	UINT64_C(`247335488`), // VTOSHS
3777	UINT64_C(`247270208`), // VTOSIRD
3778	UINT64_C(`247269696`), // VTOSIRH
3779	UINT64_C(`247269952`), // VTOSIRS
3780	UINT64_C(`247270336`), // VTOSIZD
3781	UINT64_C(`247269824`), // VTOSIZH
3782	UINT64_C(`247270080`), // VTOSIZS
3783	UINT64_C(`247335872`), // VTOSLD
3784	UINT64_C(`247335360`), // VTOSLH
3785	UINT64_C(`247335616`), // VTOSLS
3786	UINT64_C(`247401280`), // VTOUHD
3787	UINT64_C(`247400768`), // VTOUHH
3788	UINT64_C(`247401024`), // VTOUHS
3789	UINT64_C(`247204672`), // VTOUIRD
3790	UINT64_C(`247204160`), // VTOUIRH
3791	UINT64_C(`247204416`), // VTOUIRS
3792	UINT64_C(`247204800`), // VTOUIZD
3793	UINT64_C(`247204288`), // VTOUIZH
3794	UINT64_C(`247204544`), // VTOUIZS
3795	UINT64_C(`247401408`), // VTOULD
3796	UINT64_C(`247400896`), // VTOULH
3797	UINT64_C(`247401152`), // VTOULS
3798	UINT64_C(`4088791168`), // VTRNd16
3799	UINT64_C(`4089053312`), // VTRNd32
3800	UINT64_C(`4088529024`), // VTRNd8
3801	UINT64_C(`4088791232`), // VTRNq16
3802	UINT64_C(`4089053376`), // VTRNq32
3803	UINT64_C(`4088529088`), // VTRNq8
3804	UINT64_C(`4060088400`), // VTSTv16i8
3805	UINT64_C(`4062185488`), // VTSTv2i32
3806	UINT64_C(`4061136912`), // VTSTv4i16
3807	UINT64_C(`4062185552`), // VTSTv4i32
3808	UINT64_C(`4061136976`), // VTSTv8i16
3809	UINT64_C(`4060088336`), // VTSTv8i8
3810	UINT64_C(`4229958928`), // VUDOTD
3811	UINT64_C(`4263513360`), // VUDOTDI
3812	UINT64_C(`4229958992`), // VUDOTQ
3813	UINT64_C(`4263513424`), // VUDOTQI
3814	UINT64_C(`247139136`), // VUHTOD
3815	UINT64_C(`247138624`), // VUHTOH
3816	UINT64_C(`247138880`), // VUHTOS
3817	UINT64_C(`246942528`), // VUITOD
3818	UINT64_C(`246942016`), // VUITOH
3819	UINT64_C(`246942272`), // VUITOS
3820	UINT64_C(`247139264`), // VULTOD
3821	UINT64_C(`247138752`), // VULTOH
3822	UINT64_C(`247139008`), // VULTOS
3823	UINT64_C(`4229958736`), // VUMMLA
3824	UINT64_C(`4238347520`), // VUSDOTD
3825	UINT64_C(`4269804800`), // VUSDOTDI
3826	UINT64_C(`4238347584`), // VUSDOTQ
3827	UINT64_C(`4269804864`), // VUSDOTQI
3828	UINT64_C(`4238347328`), // VUSMMLA
3829	UINT64_C(`4088791296`), // VUZPd16
3830	UINT64_C(`4088529152`), // VUZPd8
3831	UINT64_C(`4088791360`), // VUZPq16
3832	UINT64_C(`4089053504`), // VUZPq32
3833	UINT64_C(`4088529216`), // VUZPq8
3834	UINT64_C(`4088791424`), // VZIPd16
3835	UINT64_C(`4088529280`), // VZIPd8
3836	UINT64_C(`4088791488`), // VZIPq16
3837	UINT64_C(`4089053632`), // VZIPq32
3838	UINT64_C(`4088529344`), // VZIPq8
3839	UINT64_C(`139460608`), // sysLDMDA
3840	UINT64_C(`141557760`), // sysLDMDA_UPD
3841	UINT64_C(`156237824`), // sysLDMDB
3842	UINT64_C(`158334976`), // sysLDMDB_UPD
3843	UINT64_C(`147849216`), // sysLDMIA
3844	UINT64_C(`149946368`), // sysLDMIA_UPD
3845	UINT64_C(`164626432`), // sysLDMIB
3846	UINT64_C(`166723584`), // sysLDMIB_UPD
3847	UINT64_C(`138412032`), // sysSTMDA
3848	UINT64_C(`140509184`), // sysSTMDA_UPD
3849	UINT64_C(`155189248`), // sysSTMDB
3850	UINT64_C(`157286400`), // sysSTMDB_UPD
3851	UINT64_C(`146800640`), // sysSTMIA
3852	UINT64_C(`148897792`), // sysSTMIA_UPD
3853	UINT64_C(`163577856`), // sysSTMIB
3854	UINT64_C(`165675008`), // sysSTMIB_UPD
3855	UINT64_C(`4047503360`), // t2ADCri
3856	UINT64_C(`3946840064`), // t2ADCrr
3857	UINT64_C(`3946840064`), // t2ADCrs
3858	UINT64_C(`4043309056`), // t2ADDri
3859	UINT64_C(`4060086272`), // t2ADDri12
3860	UINT64_C(`3942645760`), // t2ADDrr
3861	UINT64_C(`3942645760`), // t2ADDrs
3862	UINT64_C(`4044164352`), // t2ADDspImm
3863	UINT64_C(`4060941568`), // t2ADDspImm12
3864	UINT64_C(`4061069312`), // t2ADR
3865	UINT64_C(`4026531840`), // t2ANDri
3866	UINT64_C(`3925868544`), // t2ANDrr
3867	UINT64_C(`3925868544`), // t2ANDrs
3868	UINT64_C(`3931045920`), // t2ASRri
3869	UINT64_C(`4198559744`), // t2ASRrr
3870	UINT64_C(`4026568704`), // t2B
3871	UINT64_C(`4084137984`), // t2BFC
3872	UINT64_C(`4083154944`), // t2BFI
3873	UINT64_C(`4026580993`), // t2BFLi
3874	UINT64_C(`4033929217`), // t2BFLr
3875	UINT64_C(`4030783489`), // t2BFi
3876	UINT64_C(`4026589185`), // t2BFic
3877	UINT64_C(`4032880641`), // t2BFr
3878	UINT64_C(`4028628992`), // t2BICri
3879	UINT64_C(`3927965696`), // t2BICrr
3880	UINT64_C(`3927965696`), // t2BICrs
3881	UINT64_C(`4089483008`), // t2BXJ
3882	UINT64_C(`4026564608`), // t2Bcc
3883	UINT64_C(`3992977408`), // t2CDP
3884	UINT64_C(`4261412864`), // t2CDP2
3885	UINT64_C(`4089417519`), // t2CLREX
3886	UINT64_C(`3902734336`), // t2CLRM
3887	UINT64_C(`4205899904`), // t2CLZ
3888	UINT64_C(`4044361472`), // t2CMNri
3889	UINT64_C(`3943698176`), // t2CMNzrr
3890	UINT64_C(`3943698176`), // t2CMNzrs
3891	UINT64_C(`4054847232`), // t2CMPri
3892	UINT64_C(`3954183936`), // t2CMPrr
3893	UINT64_C(`3954183936`), // t2CMPrs
3894	UINT64_C(`4088365312`), // t2CPS1p
3895	UINT64_C(`4088365056`), // t2CPS2p
3896	UINT64_C(`4088365312`), // t2CPS3p
3897	UINT64_C(`4206948480`), // t2CRC32B
3898	UINT64_C(`4207997056`), // t2CRC32CB
3899	UINT64_C(`4207997072`), // t2CRC32CH
3900	UINT64_C(`4207997088`), // t2CRC32CW
3901	UINT64_C(`4206948496`), // t2CRC32H
3902	UINT64_C(`4206948512`), // t2CRC32W
3903	UINT64_C(`3931144192`), // t2CSEL
3904	UINT64_C(`3931148288`), // t2CSINC
3905	UINT64_C(`3931152384`), // t2CSINV
3906	UINT64_C(`3931156480`), // t2CSNEG
3907	UINT64_C(`4088365296`), // t2DBG
3908	UINT64_C(`4153376769`), // t2DCPS1
3909	UINT64_C(`4153376770`), // t2DCPS2
3910	UINT64_C(`4153376771`), // t2DCPS3
3911	UINT64_C(`4030783489`), // t2DLS
3912	UINT64_C(`4089417552`), // t2DMB
3913	UINT64_C(`4089417536`), // t2DSB
3914	UINT64_C(`4034920448`), // t2EORri
3915	UINT64_C(`3934257152`), // t2EORrr
3916	UINT64_C(`3934257152`), // t2EORrs
3917	UINT64_C(`4088365056`), // t2HINT
3918	UINT64_C(`4158685184`), // t2HVC
3919	UINT64_C(`4089417568`), // t2ISB
3920	UINT64_C(`48896`), // t2IT
3921	UINT64_C(`0`), // t2Int_eh_sjlj_setjmp
3922	UINT64_C(`0`), // t2Int_eh_sjlj_setjmp_nofp
3923	UINT64_C(`3905949615`), // t2LDA
3924	UINT64_C(`3905949583`), // t2LDAB
3925	UINT64_C(`3905949679`), // t2LDAEX
3926	UINT64_C(`3905949647`), // t2LDAEXB
3927	UINT64_C(`3905945855`), // t2LDAEXD
3928	UINT64_C(`3905949663`), // t2LDAEXH
3929	UINT64_C(`3905949599`), // t2LDAH
3930	UINT64_C(`4249878528`), // t2LDC2L_OFFSET
3931	UINT64_C(`4241489920`), // t2LDC2L_OPTION
3932	UINT64_C(`4235198464`), // t2LDC2L_POST
3933	UINT64_C(`4251975680`), // t2LDC2L_PRE
3934	UINT64_C(`4245684224`), // t2LDC2_OFFSET
3935	UINT64_C(`4237295616`), // t2LDC2_OPTION
3936	UINT64_C(`4231004160`), // t2LDC2_POST
3937	UINT64_C(`4247781376`), // t2LDC2_PRE
3938	UINT64_C(`3981443072`), // t2LDCL_OFFSET
3939	UINT64_C(`3973054464`), // t2LDCL_OPTION
3940	UINT64_C(`3966763008`), // t2LDCL_POST
3941	UINT64_C(`3983540224`), // t2LDCL_PRE
3942	UINT64_C(`3977248768`), // t2LDC_OFFSET
3943	UINT64_C(`3968860160`), // t2LDC_OPTION
3944	UINT64_C(`3962568704`), // t2LDC_POST
3945	UINT64_C(`3979345920`), // t2LDC_PRE
3946	UINT64_C(`3910139904`), // t2LDMDB
3947	UINT64_C(`3912237056`), // t2LDMDB_UPD
3948	UINT64_C(`3901751296`), // t2LDMIA
3949	UINT64_C(`3903848448`), // t2LDMIA_UPD
3950	UINT64_C(`4161801728`), // t2LDRBT
3951	UINT64_C(`4161800448`), // t2LDRB_POST
3952	UINT64_C(`4161801472`), // t2LDRB_PRE
3953	UINT64_C(`4170186752`), // t2LDRBi12
3954	UINT64_C(`4161801216`), // t2LDRBi8
3955	UINT64_C(`4162781184`), // t2LDRBpci
3956	UINT64_C(`4161798144`), // t2LDRBs
3957	UINT64_C(`3899654144`), // t2LDRD_POST
3958	UINT64_C(`3916431360`), // t2LDRD_PRE
3959	UINT64_C(`3914334208`), // t2LDRDi8
3960	UINT64_C(`3897560832`), // t2LDREX
3961	UINT64_C(`3905949519`), // t2LDREXB
3962	UINT64_C(`3905945727`), // t2LDREXD
3963	UINT64_C(`3905949535`), // t2LDREXH
3964	UINT64_C(`4163898880`), // t2LDRHT
3965	UINT64_C(`4163897600`), // t2LDRH_POST
3966	UINT64_C(`4163898624`), // t2LDRH_PRE
3967	UINT64_C(`4172283904`), // t2LDRHi12
3968	UINT64_C(`4163898368`), // t2LDRHi8
3969	UINT64_C(`4164878336`), // t2LDRHpci
3970	UINT64_C(`4163895296`), // t2LDRHs
3971	UINT64_C(`4178578944`), // t2LDRSBT
3972	UINT64_C(`4178577664`), // t2LDRSB_POST
3973	UINT64_C(`4178578688`), // t2LDRSB_PRE
3974	UINT64_C(`4186963968`), // t2LDRSBi12
3975	UINT64_C(`4178578432`), // t2LDRSBi8
3976	UINT64_C(`4179558400`), // t2LDRSBpci
3977	UINT64_C(`4178575360`), // t2LDRSBs
3978	UINT64_C(`4180676096`), // t2LDRSHT
3979	UINT64_C(`4180674816`), // t2LDRSH_POST
3980	UINT64_C(`4180675840`), // t2LDRSH_PRE
3981	UINT64_C(`4189061120`), // t2LDRSHi12
3982	UINT64_C(`4180675584`), // t2LDRSHi8
3983	UINT64_C(`4181655552`), // t2LDRSHpci
3984	UINT64_C(`4180672512`), // t2LDRSHs
3985	UINT64_C(`4165996032`), // t2LDRT
3986	UINT64_C(`4165994752`), // t2LDR_POST
3987	UINT64_C(`4165995776`), // t2LDR_PRE
3988	UINT64_C(`4174381056`), // t2LDRi12
3989	UINT64_C(`4165995520`), // t2LDRi8
3990	UINT64_C(`4166975488`), // t2LDRpci
3991	UINT64_C(`4165992448`), // t2LDRs
3992	UINT64_C(`4029661185`), // t2LE
3993	UINT64_C(`4027564033`), // t2LEUpdate
3994	UINT64_C(`3931045888`), // t2LSLri
3995	UINT64_C(`4194365440`), // t2LSLrr
3996	UINT64_C(`3931045904`), // t2LSRri
3997	UINT64_C(`4196462592`), // t2LSRrr
3998	UINT64_C(`3992977424`), // t2MCR
3999	UINT64_C(`4261412880`), // t2MCR2
4000	UINT64_C(`3963617280`), // t2MCRR
4001	UINT64_C(`4232052736`), // t2MCRR2
4002	UINT64_C(`4211081216`), // t2MLA
4003	UINT64_C(`4211081232`), // t2MLS
4004	UINT64_C(`4072669184`), // t2MOVTi16
4005	UINT64_C(`4031709184`), // t2MOVi
4006	UINT64_C(`4064280576`), // t2MOVi16
4007	UINT64_C(`3931045888`), // t2MOVr
4008	UINT64_C(`3932094560`), // t2MOVsra_flag
4009	UINT64_C(`3932094544`), // t2MOVsrl_flag
4010	UINT64_C(`3994026000`), // t2MRC
4011	UINT64_C(`4262461456`), // t2MRC2
4012	UINT64_C(`3964665856`), // t2MRRC
4013	UINT64_C(`4233101312`), // t2MRRC2
4014	UINT64_C(`4092559360`), // t2MRS_AR
4015	UINT64_C(`4092559360`), // t2MRS_M
4016	UINT64_C(`4091576352`), // t2MRSbanked
4017	UINT64_C(`4093607936`), // t2MRSsys_AR
4018	UINT64_C(`4085284864`), // t2MSR_AR
4019	UINT64_C(`4085284864`), // t2MSR_M
4020	UINT64_C(`4085284896`), // t2MSRbanked
4021	UINT64_C(`4211142656`), // t2MUL
4022	UINT64_C(`4033806336`), // t2MVNi
4023	UINT64_C(`3933143040`), // t2MVNr
4024	UINT64_C(`3933143040`), // t2MVNs
4025	UINT64_C(`4032823296`), // t2ORNri
4026	UINT64_C(`3932160000`), // t2ORNrr
4027	UINT64_C(`3932160000`), // t2ORNrs
4028	UINT64_C(`4030726144`), // t2ORRri
4029	UINT64_C(`3930062848`), // t2ORRrr
4030	UINT64_C(`3930062848`), // t2ORRrs
4031	UINT64_C(`3938451456`), // t2PKHBT
4032	UINT64_C(`3938451488`), // t2PKHTB
4033	UINT64_C(`4172345344`), // t2PLDWi12
4034	UINT64_C(`4163959808`), // t2PLDWi8
4035	UINT64_C(`4163956736`), // t2PLDWs
4036	UINT64_C(`4170248192`), // t2PLDi12
4037	UINT64_C(`4161862656`), // t2PLDi8
4038	UINT64_C(`4162842624`), // t2PLDpci
4039	UINT64_C(`4161859584`), // t2PLDs
4040	UINT64_C(`4187025408`), // t2PLIi12
4041	UINT64_C(`4178639872`), // t2PLIi8
4042	UINT64_C(`4179619840`), // t2PLIpci
4043	UINT64_C(`4178636800`), // t2PLIs
4044	UINT64_C(`4202754176`), // t2QADD
4045	UINT64_C(`4203802640`), // t2QADD16
4046	UINT64_C(`4202754064`), // t2QADD8
4047	UINT64_C(`4204851216`), // t2QASX
4048	UINT64_C(`4202754192`), // t2QDADD
4049	UINT64_C(`4202754224`), // t2QDSUB
4050	UINT64_C(`4209045520`), // t2QSAX
4051	UINT64_C(`4202754208`), // t2QSUB
4052	UINT64_C(`4207996944`), // t2QSUB16
4053	UINT64_C(`4206948368`), // t2QSUB8
4054	UINT64_C(`4203802784`), // t2RBIT
4055	UINT64_C(`4203802752`), // t2REV
4056	UINT64_C(`4203802768`), // t2REV16
4057	UINT64_C(`4203802800`), // t2REVSH
4058	UINT64_C(`3893411840`), // t2RFEDB
4059	UINT64_C(`3895508992`), // t2RFEDBW
4060	UINT64_C(`3918577664`), // t2RFEIA
4061	UINT64_C(`3920674816`), // t2RFEIAW
4062	UINT64_C(`3931045936`), // t2RORri
4063	UINT64_C(`4200656896`), // t2RORrr
4064	UINT64_C(`3931045936`), // t2RRX
4065	UINT64_C(`4055891968`), // t2RSBri
4066	UINT64_C(`3955228672`), // t2RSBrr
4067	UINT64_C(`3955228672`), // t2RSBrs
4068	UINT64_C(`4203802624`), // t2SADD16
4069	UINT64_C(`4202754048`), // t2SADD8
4070	UINT64_C(`4204851200`), // t2SASX
4071	UINT64_C(`4089417584`), // t2SB
4072	UINT64_C(`4049600512`), // t2SBCri
4073	UINT64_C(`3948937216`), // t2SBCrr
4074	UINT64_C(`3948937216`), // t2SBCrs
4075	UINT64_C(`4081057792`), // t2SBFX
4076	UINT64_C(`4220580080`), // t2SDIV
4077	UINT64_C(`4204851328`), // t2SEL
4078	UINT64_C(`46608`), // t2SETPAN
4079	UINT64_C(`3917474175`), // t2SG
4080	UINT64_C(`4203802656`), // t2SHADD16
4081	UINT64_C(`4202754080`), // t2SHADD8
4082	UINT64_C(`4204851232`), // t2SHASX
4083	UINT64_C(`4209045536`), // t2SHSAX
4084	UINT64_C(`4207996960`), // t2SHSUB16
4085	UINT64_C(`4206948384`), // t2SHSUB8
4086	UINT64_C(`4159733760`), // t2SMC
4087	UINT64_C(`4212129792`), // t2SMLABB
4088	UINT64_C(`4212129808`), // t2SMLABT
4089	UINT64_C(`4213178368`), // t2SMLAD
4090	UINT64_C(`4213178384`), // t2SMLADX
4091	UINT64_C(`4223664128`), // t2SMLAL
4092	UINT64_C(`4223664256`), // t2SMLALBB
4093	UINT64_C(`4223664272`), // t2SMLALBT
4094	UINT64_C(`4223664320`), // t2SMLALD
4095	UINT64_C(`4223664336`), // t2SMLALDX
4096	UINT64_C(`4223664288`), // t2SMLALTB
4097	UINT64_C(`4223664304`), // t2SMLALTT
4098	UINT64_C(`4212129824`), // t2SMLATB
4099	UINT64_C(`4212129840`), // t2SMLATT
4100	UINT64_C(`4214226944`), // t2SMLAWB
4101	UINT64_C(`4214226960`), // t2SMLAWT
4102	UINT64_C(`4215275520`), // t2SMLSD
4103	UINT64_C(`4215275536`), // t2SMLSDX
4104	UINT64_C(`4224712896`), // t2SMLSLD
4105	UINT64_C(`4224712912`), // t2SMLSLDX
4106	UINT64_C(`4216324096`), // t2SMMLA
4107	UINT64_C(`4216324112`), // t2SMMLAR
4108	UINT64_C(`4217372672`), // t2SMMLS
4109	UINT64_C(`4217372688`), // t2SMMLSR
4110	UINT64_C(`4216385536`), // t2SMMUL
4111	UINT64_C(`4216385552`), // t2SMMULR
4112	UINT64_C(`4213239808`), // t2SMUAD
4113	UINT64_C(`4213239824`), // t2SMUADX
4114	UINT64_C(`4212191232`), // t2SMULBB
4115	UINT64_C(`4212191248`), // t2SMULBT
4116	UINT64_C(`4219469824`), // t2SMULL
4117	UINT64_C(`4212191264`), // t2SMULTB
4118	UINT64_C(`4212191280`), // t2SMULTT
4119	UINT64_C(`4214288384`), // t2SMULWB
4120	UINT64_C(`4214288400`), // t2SMULWT
4121	UINT64_C(`4215336960`), // t2SMUSD
4122	UINT64_C(`4215336976`), // t2SMUSDX
4123	UINT64_C(`3893215232`), // t2SRSDB
4124	UINT64_C(`3895312384`), // t2SRSDB_UPD
4125	UINT64_C(`3918381056`), // t2SRSIA
4126	UINT64_C(`3920478208`), // t2SRSIA_UPD
4127	UINT64_C(`4076863488`), // t2SSAT
4128	UINT64_C(`4078960640`), // t2SSAT16
4129	UINT64_C(`4209045504`), // t2SSAX
4130	UINT64_C(`4207996928`), // t2SSUB16
4131	UINT64_C(`4206948352`), // t2SSUB8
4132	UINT64_C(`4248829952`), // t2STC2L_OFFSET
4133	UINT64_C(`4240441344`), // t2STC2L_OPTION
4134	UINT64_C(`4234149888`), // t2STC2L_POST
4135	UINT64_C(`4250927104`), // t2STC2L_PRE
4136	UINT64_C(`4244635648`), // t2STC2_OFFSET
4137	UINT64_C(`4236247040`), // t2STC2_OPTION
4138	UINT64_C(`4229955584`), // t2STC2_POST
4139	UINT64_C(`4246732800`), // t2STC2_PRE
4140	UINT64_C(`3980394496`), // t2STCL_OFFSET
4141	UINT64_C(`3972005888`), // t2STCL_OPTION
4142	UINT64_C(`3965714432`), // t2STCL_POST
4143	UINT64_C(`3982491648`), // t2STCL_PRE
4144	UINT64_C(`3976200192`), // t2STC_OFFSET
4145	UINT64_C(`3967811584`), // t2STC_OPTION
4146	UINT64_C(`3961520128`), // t2STC_POST
4147	UINT64_C(`3978297344`), // t2STC_PRE
4148	UINT64_C(`3904901039`), // t2STL
4149	UINT64_C(`3904901007`), // t2STLB
4150	UINT64_C(`3904901088`), // t2STLEX
4151	UINT64_C(`3904901056`), // t2STLEXB
4152	UINT64_C(`3904897264`), // t2STLEXD
4153	UINT64_C(`3904901072`), // t2STLEXH
4154	UINT64_C(`3904901023`), // t2STLH
4155	UINT64_C(`3909091328`), // t2STMDB
4156	UINT64_C(`3911188480`), // t2STMDB_UPD
4157	UINT64_C(`3900702720`), // t2STMIA
4158	UINT64_C(`3902799872`), // t2STMIA_UPD
4159	UINT64_C(`4160753152`), // t2STRBT
4160	UINT64_C(`4160751872`), // t2STRB_POST
4161	UINT64_C(`4160752896`), // t2STRB_PRE
4162	UINT64_C(`4169138176`), // t2STRBi12
4163	UINT64_C(`4160752640`), // t2STRBi8
4164	UINT64_C(`4160749568`), // t2STRBs
4165	UINT64_C(`3898605568`), // t2STRD_POST
4166	UINT64_C(`3915382784`), // t2STRD_PRE
4167	UINT64_C(`3913285632`), // t2STRDi8
4168	UINT64_C(`3896508416`), // t2STREX
4169	UINT64_C(`3904900928`), // t2STREXB
4170	UINT64_C(`3904897136`), // t2STREXD
4171	UINT64_C(`3904900944`), // t2STREXH
4172	UINT64_C(`4162850304`), // t2STRHT
4173	UINT64_C(`4162849024`), // t2STRH_POST
4174	UINT64_C(`4162850048`), // t2STRH_PRE
4175	UINT64_C(`4171235328`), // t2STRHi12
4176	UINT64_C(`4162849792`), // t2STRHi8
4177	UINT64_C(`4162846720`), // t2STRHs
4178	UINT64_C(`4164947456`), // t2STRT
4179	UINT64_C(`4164946176`), // t2STR_POST
4180	UINT64_C(`4164947200`), // t2STR_PRE
4181	UINT64_C(`4173332480`), // t2STRi12
4182	UINT64_C(`4164946944`), // t2STRi8
4183	UINT64_C(`4164943872`), // t2STRs
4184	UINT64_C(`4091449088`), // t2SUBS_PC_LR
4185	UINT64_C(`4053794816`), // t2SUBri
4186	UINT64_C(`4070572032`), // t2SUBri12
4187	UINT64_C(`3953131520`), // t2SUBrr
4188	UINT64_C(`3953131520`), // t2SUBrs
4189	UINT64_C(`4054650112`), // t2SUBspImm
4190	UINT64_C(`4071427328`), // t2SUBspImm12
4191	UINT64_C(`4198559872`), // t2SXTAB
4192	UINT64_C(`4196462720`), // t2SXTAB16
4193	UINT64_C(`4194365568`), // t2SXTAH
4194	UINT64_C(`4199542912`), // t2SXTB
4195	UINT64_C(`4197445760`), // t2SXTB16
4196	UINT64_C(`4195348608`), // t2SXTH
4197	UINT64_C(`3906007040`), // t2TBB
4198	UINT64_C(`3906007056`), // t2TBH
4199	UINT64_C(`4035972864`), // t2TEQri
4200	UINT64_C(`3935309568`), // t2TEQrr
4201	UINT64_C(`3935309568`), // t2TEQrs
4202	UINT64_C(`4088365074`), // t2TSB
4203	UINT64_C(`4027584256`), // t2TSTri
4204	UINT64_C(`3926920960`), // t2TSTrr
4205	UINT64_C(`3926920960`), // t2TSTrs
4206	UINT64_C(`3896569856`), // t2TT
4207	UINT64_C(`3896569984`), // t2TTA
4208	UINT64_C(`3896570048`), // t2TTAT
4209	UINT64_C(`3896569920`), // t2TTT
4210	UINT64_C(`4203802688`), // t2UADD16
4211	UINT64_C(`4202754112`), // t2UADD8
4212	UINT64_C(`4204851264`), // t2UASX
4213	UINT64_C(`4089446400`), // t2UBFX
4214	UINT64_C(`4159741952`), // t2UDF
4215	UINT64_C(`4222677232`), // t2UDIV
4216	UINT64_C(`4203802720`), // t2UHADD16
4217	UINT64_C(`4202754144`), // t2UHADD8
4218	UINT64_C(`4204851296`), // t2UHASX
4219	UINT64_C(`4209045600`), // t2UHSAX
4220	UINT64_C(`4207997024`), // t2UHSUB16
4221	UINT64_C(`4206948448`), // t2UHSUB8
4222	UINT64_C(`4225761376`), // t2UMAAL
4223	UINT64_C(`4225761280`), // t2UMLAL
4224	UINT64_C(`4221566976`), // t2UMULL
4225	UINT64_C(`4203802704`), // t2UQADD16
4226	UINT64_C(`4202754128`), // t2UQADD8
4227	UINT64_C(`4204851280`), // t2UQASX
4228	UINT64_C(`4209045584`), // t2UQSAX
4229	UINT64_C(`4207997008`), // t2UQSUB16
4230	UINT64_C(`4206948432`), // t2UQSUB8
4231	UINT64_C(`4218482688`), // t2USAD8
4232	UINT64_C(`4218421248`), // t2USADA8
4233	UINT64_C(`4085252096`), // t2USAT
4234	UINT64_C(`4087349248`), // t2USAT16
4235	UINT64_C(`4209045568`), // t2USAX
4236	UINT64_C(`4207996992`), // t2USUB16
4237	UINT64_C(`4206948416`), // t2USUB8
4238	UINT64_C(`4199608448`), // t2UXTAB
4239	UINT64_C(`4197511296`), // t2UXTAB16
4240	UINT64_C(`4195414144`), // t2UXTAH
4241	UINT64_C(`4200591488`), // t2UXTB
4242	UINT64_C(`4198494336`), // t2UXTB16
4243	UINT64_C(`4196397184`), // t2UXTH
4244	UINT64_C(`4030775297`), // t2WLS
4245	UINT64_C(`16704`), // tADC
4246	UINT64_C(`17408`), // tADDhirr
4247	UINT64_C(`7168`), // tADDi3
4248	UINT64_C(`12288`), // tADDi8
4249	UINT64_C(`17512`), // tADDrSP
4250	UINT64_C(`43008`), // tADDrSPi
4251	UINT64_C(`6144`), // tADDrr
4252	UINT64_C(`45056`), // tADDspi
4253	UINT64_C(`17541`), // tADDspr
4254	UINT64_C(`40960`), // tADR
4255	UINT64_C(`16384`), // tAND
4256	UINT64_C(`4096`), // tASRri
4257	UINT64_C(`16640`), // tASRrr
4258	UINT64_C(`57344`), // tB
4259	UINT64_C(`17280`), // tBIC
4260	UINT64_C(`48640`), // tBKPT
4261	UINT64_C(`4026585088`), // tBL
4262	UINT64_C(`18308`), // tBLXNSr
4263	UINT64_C(`4026580992`), // tBLXi
4264	UINT64_C(`18304`), // tBLXr
4265	UINT64_C(`18176`), // tBX
4266	UINT64_C(`18180`), // tBXNS
4267	UINT64_C(`53248`), // tBcc
4268	UINT64_C(`47360`), // tCBNZ
4269	UINT64_C(`45312`), // tCBZ
4270	UINT64_C(`17088`), // tCMNz
4271	UINT64_C(`17664`), // tCMPhir
4272	UINT64_C(`10240`), // tCMPi8
4273	UINT64_C(`17024`), // tCMPr
4274	UINT64_C(`46688`), // tCPS
4275	UINT64_C(`16448`), // tEOR
4276	UINT64_C(`48896`), // tHINT
4277	UINT64_C(`47744`), // tHLT
4278	UINT64_C(`0`), // tInt_WIN_eh_sjlj_longjmp
4279	UINT64_C(`0`), // tInt_eh_sjlj_longjmp
4280	UINT64_C(`0`), // tInt_eh_sjlj_setjmp
4281	UINT64_C(`51200`), // tLDMIA
4282	UINT64_C(`30720`), // tLDRBi
4283	UINT64_C(`23552`), // tLDRBr
4284	UINT64_C(`34816`), // tLDRHi
4285	UINT64_C(`23040`), // tLDRHr
4286	UINT64_C(`22016`), // tLDRSB
4287	UINT64_C(`24064`), // tLDRSH
4288	UINT64_C(`26624`), // tLDRi
4289	UINT64_C(`18432`), // tLDRpci
4290	UINT64_C(`22528`), // tLDRr
4291	UINT64_C(`38912`), // tLDRspi
4292	UINT64_C(`0`), // tLSLri
4293	UINT64_C(`16512`), // tLSLrr
4294	UINT64_C(`2048`), // tLSRri
4295	UINT64_C(`16576`), // tLSRrr
4296	UINT64_C(`0`), // tMOVSr
4297	UINT64_C(`8192`), // tMOVi8
4298	UINT64_C(`17920`), // tMOVr
4299	UINT64_C(`17216`), // tMUL
4300	UINT64_C(`17344`), // tMVN
4301	UINT64_C(`17152`), // tORR
4302	UINT64_C(`17528`), // tPICADD
4303	UINT64_C(`48128`), // tPOP
4304	UINT64_C(`46080`), // tPUSH
4305	UINT64_C(`47616`), // tREV
4306	UINT64_C(`47680`), // tREV16
4307	UINT64_C(`47808`), // tREVSH
4308	UINT64_C(`16832`), // tROR
4309	UINT64_C(`16960`), // tRSB
4310	UINT64_C(`16768`), // tSBC
4311	UINT64_C(`46672`), // tSETEND
4312	UINT64_C(`49152`), // tSTMIA_UPD
4313	UINT64_C(`28672`), // tSTRBi
4314	UINT64_C(`21504`), // tSTRBr
4315	UINT64_C(`32768`), // tSTRHi
4316	UINT64_C(`20992`), // tSTRHr
4317	UINT64_C(`24576`), // tSTRi
4318	UINT64_C(`20480`), // tSTRr
4319	UINT64_C(`36864`), // tSTRspi
4320	UINT64_C(`7680`), // tSUBi3
4321	UINT64_C(`14336`), // tSUBi8
4322	UINT64_C(`6656`), // tSUBrr
4323	UINT64_C(`45184`), // tSUBspi
4324	UINT64_C(`57088`), // tSVC
4325	UINT64_C(`45632`), // tSXTB
4326	UINT64_C(`45568`), // tSXTH
4327	UINT64_C(`57086`), // tTRAP
4328	UINT64_C(`16896`), // tTST
4329	UINT64_C(`56832`), // tUDF
4330	UINT64_C(`45760`), // tUXTB
4331	UINT64_C(`45696`), // tUXTH
4332	UINT64_C(`57081`), // t__brkdiv0
4333	UINT64_C(`0`)
4334	};
4335	const unsigned opcode = MI.getOpcode();
4336	uint64_t Value = InstBits[opcode];
4337	uint64_t op = `0`;
4338	(void)op; // suppress warning
4339	switch (opcode) {
4340	case ARM::CLREX:
4341	case ARM::MVE_LCTP:
4342	case ARM::MVE_VPNOT:
4343	case ARM::SB:
4344	case ARM::TRAP:
4345	case ARM::TRAPNaCl:
4346	case ARM::TSB:
4347	case ARM::VBSPd:
4348	case ARM::VBSPq:
4349	case ARM::VLD1LNq16Pseudo:
4350	case ARM::VLD1LNq16Pseudo_UPD:
4351	case ARM::VLD1LNq32Pseudo:
4352	case ARM::VLD1LNq32Pseudo_UPD:
4353	case ARM::VLD1LNq8Pseudo:
4354	case ARM::VLD1LNq8Pseudo_UPD:
4355	case ARM::VLD1d16QPseudo:
4356	case ARM::VLD1d16TPseudo:
4357	case ARM::VLD1d32QPseudo:
4358	case ARM::VLD1d32TPseudo:
4359	case ARM::VLD1d64QPseudo:
4360	case ARM::VLD1d64QPseudoWB_fixed:
4361	case ARM::VLD1d64QPseudoWB_register:
4362	case ARM::VLD1d64TPseudo:
4363	case ARM::VLD1d64TPseudoWB_fixed:
4364	case ARM::VLD1d64TPseudoWB_register:
4365	case ARM::VLD1d8QPseudo:
4366	case ARM::VLD1d8TPseudo:
4367	case ARM::VLD1q16HighQPseudo:
4368	case ARM::VLD1q16HighTPseudo:
4369	case ARM::VLD1q16LowQPseudo_UPD:
4370	case ARM::VLD1q16LowTPseudo_UPD:
4371	case ARM::VLD1q32HighQPseudo:
4372	case ARM::VLD1q32HighTPseudo:
4373	case ARM::VLD1q32LowQPseudo_UPD:
4374	case ARM::VLD1q32LowTPseudo_UPD:
4375	case ARM::VLD1q64HighQPseudo:
4376	case ARM::VLD1q64HighTPseudo:
4377	case ARM::VLD1q64LowQPseudo_UPD:
4378	case ARM::VLD1q64LowTPseudo_UPD:
4379	case ARM::VLD1q8HighQPseudo:
4380	case ARM::VLD1q8HighTPseudo:
4381	case ARM::VLD1q8LowQPseudo_UPD:
4382	case ARM::VLD1q8LowTPseudo_UPD:
4383	case ARM::VLD2DUPq16EvenPseudo:
4384	case ARM::VLD2DUPq16OddPseudo:
4385	case ARM::VLD2DUPq32EvenPseudo:
4386	case ARM::VLD2DUPq32OddPseudo:
4387	case ARM::VLD2DUPq8EvenPseudo:
4388	case ARM::VLD2DUPq8OddPseudo:
4389	case ARM::VLD2LNd16Pseudo:
4390	case ARM::VLD2LNd16Pseudo_UPD:
4391	case ARM::VLD2LNd32Pseudo:
4392	case ARM::VLD2LNd32Pseudo_UPD:
4393	case ARM::VLD2LNd8Pseudo:
4394	case ARM::VLD2LNd8Pseudo_UPD:
4395	case ARM::VLD2LNq16Pseudo:
4396	case ARM::VLD2LNq16Pseudo_UPD:
4397	case ARM::VLD2LNq32Pseudo:
4398	case ARM::VLD2LNq32Pseudo_UPD:
4399	case ARM::VLD2q16Pseudo:
4400	case ARM::VLD2q16PseudoWB_fixed:
4401	case ARM::VLD2q16PseudoWB_register:
4402	case ARM::VLD2q32Pseudo:
4403	case ARM::VLD2q32PseudoWB_fixed:
4404	case ARM::VLD2q32PseudoWB_register:
4405	case ARM::VLD2q8Pseudo:
4406	case ARM::VLD2q8PseudoWB_fixed:
4407	case ARM::VLD2q8PseudoWB_register:
4408	case ARM::VLD3DUPd16Pseudo:
4409	case ARM::VLD3DUPd16Pseudo_UPD:
4410	case ARM::VLD3DUPd32Pseudo:
4411	case ARM::VLD3DUPd32Pseudo_UPD:
4412	case ARM::VLD3DUPd8Pseudo:
4413	case ARM::VLD3DUPd8Pseudo_UPD:
4414	case ARM::VLD3DUPq16EvenPseudo:
4415	case ARM::VLD3DUPq16OddPseudo:
4416	case ARM::VLD3DUPq32EvenPseudo:
4417	case ARM::VLD3DUPq32OddPseudo:
4418	case ARM::VLD3DUPq8EvenPseudo:
4419	case ARM::VLD3DUPq8OddPseudo:
4420	case ARM::VLD3LNd16Pseudo:
4421	case ARM::VLD3LNd16Pseudo_UPD:
4422	case ARM::VLD3LNd32Pseudo:
4423	case ARM::VLD3LNd32Pseudo_UPD:
4424	case ARM::VLD3LNd8Pseudo:
4425	case ARM::VLD3LNd8Pseudo_UPD:
4426	case ARM::VLD3LNq16Pseudo:
4427	case ARM::VLD3LNq16Pseudo_UPD:
4428	case ARM::VLD3LNq32Pseudo:
4429	case ARM::VLD3LNq32Pseudo_UPD:
4430	case ARM::VLD3d16Pseudo:
4431	case ARM::VLD3d16Pseudo_UPD:
4432	case ARM::VLD3d32Pseudo:
4433	case ARM::VLD3d32Pseudo_UPD:
4434	case ARM::VLD3d8Pseudo:
4435	case ARM::VLD3d8Pseudo_UPD:
4436	case ARM::VLD3q16Pseudo_UPD:
4437	case ARM::VLD3q16oddPseudo:
4438	case ARM::VLD3q16oddPseudo_UPD:
4439	case ARM::VLD3q32Pseudo_UPD:
4440	case ARM::VLD3q32oddPseudo:
4441	case ARM::VLD3q32oddPseudo_UPD:
4442	case ARM::VLD3q8Pseudo_UPD:
4443	case ARM::VLD3q8oddPseudo:
4444	case ARM::VLD3q8oddPseudo_UPD:
4445	case ARM::VLD4DUPd16Pseudo:
4446	case ARM::VLD4DUPd16Pseudo_UPD:
4447	case ARM::VLD4DUPd32Pseudo:
4448	case ARM::VLD4DUPd32Pseudo_UPD:
4449	case ARM::VLD4DUPd8Pseudo:
4450	case ARM::VLD4DUPd8Pseudo_UPD:
4451	case ARM::VLD4DUPq16EvenPseudo:
4452	case ARM::VLD4DUPq16OddPseudo:
4453	case ARM::VLD4DUPq32EvenPseudo:
4454	case ARM::VLD4DUPq32OddPseudo:
4455	case ARM::VLD4DUPq8EvenPseudo:
4456	case ARM::VLD4DUPq8OddPseudo:
4457	case ARM::VLD4LNd16Pseudo:
4458	case ARM::VLD4LNd16Pseudo_UPD:
4459	case ARM::VLD4LNd32Pseudo:
4460	case ARM::VLD4LNd32Pseudo_UPD:
4461	case ARM::VLD4LNd8Pseudo:
4462	case ARM::VLD4LNd8Pseudo_UPD:
4463	case ARM::VLD4LNq16Pseudo:
4464	case ARM::VLD4LNq16Pseudo_UPD:
4465	case ARM::VLD4LNq32Pseudo:
4466	case ARM::VLD4LNq32Pseudo_UPD:
4467	case ARM::VLD4d16Pseudo:
4468	case ARM::VLD4d16Pseudo_UPD:
4469	case ARM::VLD4d32Pseudo:
4470	case ARM::VLD4d32Pseudo_UPD:
4471	case ARM::VLD4d8Pseudo:
4472	case ARM::VLD4d8Pseudo_UPD:
4473	case ARM::VLD4q16Pseudo_UPD:
4474	case ARM::VLD4q16oddPseudo:
4475	case ARM::VLD4q16oddPseudo_UPD:
4476	case ARM::VLD4q32Pseudo_UPD:
4477	case ARM::VLD4q32oddPseudo:
4478	case ARM::VLD4q32oddPseudo_UPD:
4479	case ARM::VLD4q8Pseudo_UPD:
4480	case ARM::VLD4q8oddPseudo:
4481	case ARM::VLD4q8oddPseudo_UPD:
4482	case ARM::VLDMQIA:
4483	case ARM::VST1LNq16Pseudo:
4484	case ARM::VST1LNq16Pseudo_UPD:
4485	case ARM::VST1LNq32Pseudo:
4486	case ARM::VST1LNq32Pseudo_UPD:
4487	case ARM::VST1LNq8Pseudo:
4488	case ARM::VST1LNq8Pseudo_UPD:
4489	case ARM::VST1d16QPseudo:
4490	case ARM::VST1d16TPseudo:
4491	case ARM::VST1d32QPseudo:
4492	case ARM::VST1d32TPseudo:
4493	case ARM::VST1d64QPseudo:
4494	case ARM::VST1d64QPseudoWB_fixed:
4495	case ARM::VST1d64QPseudoWB_register:
4496	case ARM::VST1d64TPseudo:
4497	case ARM::VST1d64TPseudoWB_fixed:
4498	case ARM::VST1d64TPseudoWB_register:
4499	case ARM::VST1d8QPseudo:
4500	case ARM::VST1d8TPseudo:
4501	case ARM::VST1q16HighQPseudo:
4502	case ARM::VST1q16HighTPseudo:
4503	case ARM::VST1q16LowQPseudo_UPD:
4504	case ARM::VST1q16LowTPseudo_UPD:
4505	case ARM::VST1q32HighQPseudo:
4506	case ARM::VST1q32HighTPseudo:
4507	case ARM::VST1q32LowQPseudo_UPD:
4508	case ARM::VST1q32LowTPseudo_UPD:
4509	case ARM::VST1q64HighQPseudo:
4510	case ARM::VST1q64HighTPseudo:
4511	case ARM::VST1q64LowQPseudo_UPD:
4512	case ARM::VST1q64LowTPseudo_UPD:
4513	case ARM::VST1q8HighQPseudo:
4514	case ARM::VST1q8HighTPseudo:
4515	case ARM::VST1q8LowQPseudo_UPD:
4516	case ARM::VST1q8LowTPseudo_UPD:
4517	case ARM::VST2LNd16Pseudo:
4518	case ARM::VST2LNd16Pseudo_UPD:
4519	case ARM::VST2LNd32Pseudo:
4520	case ARM::VST2LNd32Pseudo_UPD:
4521	case ARM::VST2LNd8Pseudo:
4522	case ARM::VST2LNd8Pseudo_UPD:
4523	case ARM::VST2LNq16Pseudo:
4524	case ARM::VST2LNq16Pseudo_UPD:
4525	case ARM::VST2LNq32Pseudo:
4526	case ARM::VST2LNq32Pseudo_UPD:
4527	case ARM::VST2q16Pseudo:
4528	case ARM::VST2q16PseudoWB_fixed:
4529	case ARM::VST2q16PseudoWB_register:
4530	case ARM::VST2q32Pseudo:
4531	case ARM::VST2q32PseudoWB_fixed:
4532	case ARM::VST2q32PseudoWB_register:
4533	case ARM::VST2q8Pseudo:
4534	case ARM::VST2q8PseudoWB_fixed:
4535	case ARM::VST2q8PseudoWB_register:
4536	case ARM::VST3LNd16Pseudo:
4537	case ARM::VST3LNd16Pseudo_UPD:
4538	case ARM::VST3LNd32Pseudo:
4539	case ARM::VST3LNd32Pseudo_UPD:
4540	case ARM::VST3LNd8Pseudo:
4541	case ARM::VST3LNd8Pseudo_UPD:
4542	case ARM::VST3LNq16Pseudo:
4543	case ARM::VST3LNq16Pseudo_UPD:
4544	case ARM::VST3LNq32Pseudo:
4545	case ARM::VST3LNq32Pseudo_UPD:
4546	case ARM::VST3d16Pseudo:
4547	case ARM::VST3d16Pseudo_UPD:
4548	case ARM::VST3d32Pseudo:
4549	case ARM::VST3d32Pseudo_UPD:
4550	case ARM::VST3d8Pseudo:
4551	case ARM::VST3d8Pseudo_UPD:
4552	case ARM::VST3q16Pseudo_UPD:
4553	case ARM::VST3q16oddPseudo:
4554	case ARM::VST3q16oddPseudo_UPD:
4555	case ARM::VST3q32Pseudo_UPD:
4556	case ARM::VST3q32oddPseudo:
4557	case ARM::VST3q32oddPseudo_UPD:
4558	case ARM::VST3q8Pseudo_UPD:
4559	case ARM::VST3q8oddPseudo:
4560	case ARM::VST3q8oddPseudo_UPD:
4561	case ARM::VST4LNd16Pseudo:
4562	case ARM::VST4LNd16Pseudo_UPD:
4563	case ARM::VST4LNd32Pseudo:
4564	case ARM::VST4LNd32Pseudo_UPD:
4565	case ARM::VST4LNd8Pseudo:
4566	case ARM::VST4LNd8Pseudo_UPD:
4567	case ARM::VST4LNq16Pseudo:
4568	case ARM::VST4LNq16Pseudo_UPD:
4569	case ARM::VST4LNq32Pseudo:
4570	case ARM::VST4LNq32Pseudo_UPD:
4571	case ARM::VST4d16Pseudo:
4572	case ARM::VST4d16Pseudo_UPD:
4573	case ARM::VST4d32Pseudo:
4574	case ARM::VST4d32Pseudo_UPD:
4575	case ARM::VST4d8Pseudo:
4576	case ARM::VST4d8Pseudo_UPD:
4577	case ARM::VST4q16Pseudo_UPD:
4578	case ARM::VST4q16oddPseudo:
4579	case ARM::VST4q16oddPseudo_UPD:
4580	case ARM::VST4q32Pseudo_UPD:
4581	case ARM::VST4q32oddPseudo:
4582	case ARM::VST4q32oddPseudo_UPD:
4583	case ARM::VST4q8Pseudo_UPD:
4584	case ARM::VST4q8oddPseudo:
4585	case ARM::VST4q8oddPseudo_UPD:
4586	case ARM::VSTMQIA:
4587	case ARM::VTBL3Pseudo:
4588	case ARM::VTBL4Pseudo:
4589	case ARM::VTBX3Pseudo:
4590	case ARM::VTBX4Pseudo:
4591	case ARM::t2CLREX:
4592	case ARM::t2DCPS1:
4593	case ARM::t2DCPS2:
4594	case ARM::t2DCPS3:
4595	case ARM::t2Int_eh_sjlj_setjmp:
4596	case ARM::t2Int_eh_sjlj_setjmp_nofp:
4597	case ARM::t2SB:
4598	case ARM::t2SG:
4599	case ARM::t2TSB:
4600	case ARM::tInt_WIN_eh_sjlj_longjmp:
4601	case ARM::tInt_eh_sjlj_longjmp:
4602	case ARM::tInt_eh_sjlj_setjmp:
4603	case ARM::tTRAP:
4604	case ARM::t__brkdiv0: {
4605	break;
4606	}
4607	case ARM::VRINTAD:
4608	case ARM::VRINTMD:
4609	case ARM::VRINTND:
4610	case ARM::VRINTPD: {
4611	// op: Dd
4612	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
4613	Value \|= (op & UINT64_C(`16`)) << `18`;
4614	Value \|= (op & UINT64_C(`15`)) << `12`;
4615	// op: Dm
4616	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
4617	Value \|= (op & UINT64_C(`16`)) << `1`;
4618	Value \|= (op & UINT64_C(`15`));
4619	break;
4620	}
4621	case ARM::VFP_VMAXNMD:
4622	case ARM::VFP_VMINNMD:
4623	case ARM::VSELEQD:
4624	case ARM::VSELGED:
4625	case ARM::VSELGTD:
4626	case ARM::VSELVSD: {
4627	// op: Dd
4628	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
4629	Value \|= (op & UINT64_C(`16`)) << `18`;
4630	Value \|= (op & UINT64_C(`15`)) << `12`;
4631	// op: Dn
4632	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
4633	Value \|= (op & UINT64_C(`15`)) << `16`;
4634	Value \|= (op & UINT64_C(`16`)) << `3`;
4635	// op: Dm
4636	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
4637	Value \|= (op & UINT64_C(`16`)) << `1`;
4638	Value \|= (op & UINT64_C(`15`));
4639	break;
4640	}
4641	case ARM::MVE_VPST: {
4642	// op: Mk
4643	op = getVPTMaskOpValue(MI, `0`, Fixups, STI);
4644	Value \|= (op & UINT64_C(`8`)) << `19`;
4645	Value \|= (op & UINT64_C(`7`)) << `13`;
4646	break;
4647	}
4648	case ARM::MVE_VDUP16:
4649	case ARM::MVE_VDUP32:
4650	case ARM::MVE_VDUP8: {
4651	// op: Qd
4652	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
4653	Value \|= (op & UINT64_C(`7`)) << `17`;
4654	Value \|= (op & UINT64_C(`8`)) << `4`;
4655	// op: Rt
4656	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
4657	op &= UINT64_C(`15`);
4658	op <<= `12`;
4659	Value \|= op;
4660	break;
4661	}
4662	case ARM::MVE_VMOV_to_lane_32: {
4663	// op: Qd
4664	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
4665	Value \|= (op & UINT64_C(`7`)) << `17`;
4666	Value \|= (op & UINT64_C(`8`)) << `4`;
4667	// op: Rt
4668	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
4669	op &= UINT64_C(`15`);
4670	op <<= `12`;
4671	Value \|= op;
4672	// op: Idx
4673	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
4674	Value \|= (op & UINT64_C(`1`)) << `21`;
4675	Value \|= (op & UINT64_C(`2`)) << `15`;
4676	break;
4677	}
4678	case ARM::MVE_VMOV_to_lane_16: {
4679	// op: Qd
4680	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
4681	Value \|= (op & UINT64_C(`7`)) << `17`;
4682	Value \|= (op & UINT64_C(`8`)) << `4`;
4683	// op: Rt
4684	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
4685	op &= UINT64_C(`15`);
4686	op <<= `12`;
4687	Value \|= op;
4688	// op: Idx
4689	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
4690	Value \|= (op & UINT64_C(`2`)) << `20`;
4691	Value \|= (op & UINT64_C(`4`)) << `14`;
4692	Value \|= (op & UINT64_C(`1`)) << `6`;
4693	break;
4694	}
4695	case ARM::MVE_VMOV_to_lane_8: {
4696	// op: Qd
4697	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
4698	Value \|= (op & UINT64_C(`7`)) << `17`;
4699	Value \|= (op & UINT64_C(`8`)) << `4`;
4700	// op: Rt
4701	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
4702	op &= UINT64_C(`15`);
4703	op <<= `12`;
4704	Value \|= op;
4705	// op: Idx
4706	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
4707	Value \|= (op & UINT64_C(`4`)) << `19`;
4708	Value \|= (op & UINT64_C(`8`)) << `13`;
4709	Value \|= (op & UINT64_C(`3`)) << `5`;
4710	break;
4711	}
4712	case ARM::MVE_VABSs16:
4713	case ARM::MVE_VABSs32:
4714	case ARM::MVE_VABSs8:
4715	case ARM::MVE_VCLSs16:
4716	case ARM::MVE_VCLSs32:
4717	case ARM::MVE_VCLSs8:
4718	case ARM::MVE_VCLZs16:
4719	case ARM::MVE_VCLZs32:
4720	case ARM::MVE_VCLZs8:
4721	case ARM::MVE_VCVTf32f16bh:
4722	case ARM::MVE_VCVTf32f16th:
4723	case ARM::MVE_VMOVLs16bh:
4724	case ARM::MVE_VMOVLs16th:
4725	case ARM::MVE_VMOVLs8bh:
4726	case ARM::MVE_VMOVLs8th:
4727	case ARM::MVE_VMOVLu16bh:
4728	case ARM::MVE_VMOVLu16th:
4729	case ARM::MVE_VMOVLu8bh:
4730	case ARM::MVE_VMOVLu8th:
4731	case ARM::MVE_VMVN:
4732	case ARM::MVE_VNEGs16:
4733	case ARM::MVE_VNEGs32:
4734	case ARM::MVE_VNEGs8:
4735	case ARM::MVE_VQABSs16:
4736	case ARM::MVE_VQABSs32:
4737	case ARM::MVE_VQABSs8:
4738	case ARM::MVE_VQNEGs16:
4739	case ARM::MVE_VQNEGs32:
4740	case ARM::MVE_VQNEGs8:
4741	case ARM::MVE_VREV16_8:
4742	case ARM::MVE_VREV32_16:
4743	case ARM::MVE_VREV32_8:
4744	case ARM::MVE_VREV64_16:
4745	case ARM::MVE_VREV64_32:
4746	case ARM::MVE_VREV64_8:
4747	case ARM::MVE_VSHLL_lws16bh:
4748	case ARM::MVE_VSHLL_lws16th:
4749	case ARM::MVE_VSHLL_lws8bh:
4750	case ARM::MVE_VSHLL_lws8th:
4751	case ARM::MVE_VSHLL_lwu16bh:
4752	case ARM::MVE_VSHLL_lwu16th:
4753	case ARM::MVE_VSHLL_lwu8bh:
4754	case ARM::MVE_VSHLL_lwu8th: {
4755	// op: Qd
4756	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
4757	Value \|= (op & UINT64_C(`8`)) << `19`;
4758	Value \|= (op & UINT64_C(`7`)) << `13`;
4759	// op: Qm
4760	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
4761	Value \|= (op & UINT64_C(`8`)) << `2`;
4762	Value \|= (op & UINT64_C(`7`)) << `1`;
4763	break;
4764	}
4765	case ARM::MVE_VQRSHL_by_vecs16:
4766	case ARM::MVE_VQRSHL_by_vecs32:
4767	case ARM::MVE_VQRSHL_by_vecs8:
4768	case ARM::MVE_VQRSHL_by_vecu16:
4769	case ARM::MVE_VQRSHL_by_vecu32:
4770	case ARM::MVE_VQRSHL_by_vecu8:
4771	case ARM::MVE_VQSHL_by_vecs16:
4772	case ARM::MVE_VQSHL_by_vecs32:
4773	case ARM::MVE_VQSHL_by_vecs8:
4774	case ARM::MVE_VQSHL_by_vecu16:
4775	case ARM::MVE_VQSHL_by_vecu32:
4776	case ARM::MVE_VQSHL_by_vecu8:
4777	case ARM::MVE_VRSHL_by_vecs16:
4778	case ARM::MVE_VRSHL_by_vecs32:
4779	case ARM::MVE_VRSHL_by_vecs8:
4780	case ARM::MVE_VRSHL_by_vecu16:
4781	case ARM::MVE_VRSHL_by_vecu32:
4782	case ARM::MVE_VRSHL_by_vecu8:
4783	case ARM::MVE_VSHL_by_vecs16:
4784	case ARM::MVE_VSHL_by_vecs32:
4785	case ARM::MVE_VSHL_by_vecs8:
4786	case ARM::MVE_VSHL_by_vecu16:
4787	case ARM::MVE_VSHL_by_vecu32:
4788	case ARM::MVE_VSHL_by_vecu8: {
4789	// op: Qd
4790	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
4791	Value \|= (op & UINT64_C(`8`)) << `19`;
4792	Value \|= (op & UINT64_C(`7`)) << `13`;
4793	// op: Qm
4794	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
4795	Value \|= (op & UINT64_C(`8`)) << `2`;
4796	Value \|= (op & UINT64_C(`7`)) << `1`;
4797	// op: Qn
4798	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
4799	Value \|= (op & UINT64_C(`7`)) << `17`;
4800	Value \|= (op & UINT64_C(`8`)) << `4`;
4801	break;
4802	}
4803	case ARM::MVE_VSHLL_imms16bh:
4804	case ARM::MVE_VSHLL_imms16th:
4805	case ARM::MVE_VSHLL_immu16bh:
4806	case ARM::MVE_VSHLL_immu16th: {
4807	// op: Qd
4808	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
4809	Value \|= (op & UINT64_C(`8`)) << `19`;
4810	Value \|= (op & UINT64_C(`7`)) << `13`;
4811	// op: Qm
4812	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
4813	Value \|= (op & UINT64_C(`8`)) << `2`;
4814	Value \|= (op & UINT64_C(`7`)) << `1`;
4815	// op: imm
4816	op = getMVEShiftImmOpValue(MI, `2`, Fixups, STI);
4817	op &= UINT64_C(`15`);
4818	op <<= `16`;
4819	Value \|= op;
4820	break;
4821	}
4822	case ARM::MVE_VSHLL_imms8bh:
4823	case ARM::MVE_VSHLL_imms8th:
4824	case ARM::MVE_VSHLL_immu8bh:
4825	case ARM::MVE_VSHLL_immu8th: {
4826	// op: Qd
4827	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
4828	Value \|= (op & UINT64_C(`8`)) << `19`;
4829	Value \|= (op & UINT64_C(`7`)) << `13`;
4830	// op: Qm
4831	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
4832	Value \|= (op & UINT64_C(`8`)) << `2`;
4833	Value \|= (op & UINT64_C(`7`)) << `1`;
4834	// op: imm
4835	op = getMVEShiftImmOpValue(MI, `2`, Fixups, STI);
4836	op &= UINT64_C(`7`);
4837	op <<= `16`;
4838	Value \|= op;
4839	break;
4840	}
4841	case ARM::MVE_VQSHLU_imms16:
4842	case ARM::MVE_VQSHLimms16:
4843	case ARM::MVE_VQSHLimmu16:
4844	case ARM::MVE_VSHL_immi16: {
4845	// op: Qd
4846	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
4847	Value \|= (op & UINT64_C(`8`)) << `19`;
4848	Value \|= (op & UINT64_C(`7`)) << `13`;
4849	// op: Qm
4850	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
4851	Value \|= (op & UINT64_C(`8`)) << `2`;
4852	Value \|= (op & UINT64_C(`7`)) << `1`;
4853	// op: imm
4854	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
4855	op &= UINT64_C(`15`);
4856	op <<= `16`;
4857	Value \|= op;
4858	break;
4859	}
4860	case ARM::MVE_VQSHLU_imms32:
4861	case ARM::MVE_VQSHLimms32:
4862	case ARM::MVE_VQSHLimmu32:
4863	case ARM::MVE_VSHL_immi32: {
4864	// op: Qd
4865	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
4866	Value \|= (op & UINT64_C(`8`)) << `19`;
4867	Value \|= (op & UINT64_C(`7`)) << `13`;
4868	// op: Qm
4869	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
4870	Value \|= (op & UINT64_C(`8`)) << `2`;
4871	Value \|= (op & UINT64_C(`7`)) << `1`;
4872	// op: imm
4873	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
4874	op &= UINT64_C(`31`);
4875	op <<= `16`;
4876	Value \|= op;
4877	break;
4878	}
4879	case ARM::MVE_VQSHLU_imms8:
4880	case ARM::MVE_VQSHLimms8:
4881	case ARM::MVE_VQSHLimmu8:
4882	case ARM::MVE_VSHL_immi8: {
4883	// op: Qd
4884	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
4885	Value \|= (op & UINT64_C(`8`)) << `19`;
4886	Value \|= (op & UINT64_C(`7`)) << `13`;
4887	// op: Qm
4888	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
4889	Value \|= (op & UINT64_C(`8`)) << `2`;
4890	Value \|= (op & UINT64_C(`7`)) << `1`;
4891	// op: imm
4892	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
4893	op &= UINT64_C(`7`);
4894	op <<= `16`;
4895	Value \|= op;
4896	break;
4897	}
4898	case ARM::MVE_VRSHR_imms16:
4899	case ARM::MVE_VRSHR_immu16:
4900	case ARM::MVE_VSHR_imms16:
4901	case ARM::MVE_VSHR_immu16: {
4902	// op: Qd
4903	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
4904	Value \|= (op & UINT64_C(`8`)) << `19`;
4905	Value \|= (op & UINT64_C(`7`)) << `13`;
4906	// op: Qm
4907	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
4908	Value \|= (op & UINT64_C(`8`)) << `2`;
4909	Value \|= (op & UINT64_C(`7`)) << `1`;
4910	// op: imm
4911	op = getShiftRight16Imm(MI, `2`, Fixups, STI);
4912	op &= UINT64_C(`15`);
4913	op <<= `16`;
4914	Value \|= op;
4915	break;
4916	}
4917	case ARM::MVE_VRSHR_imms32:
4918	case ARM::MVE_VRSHR_immu32:
4919	case ARM::MVE_VSHR_imms32:
4920	case ARM::MVE_VSHR_immu32: {
4921	// op: Qd
4922	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
4923	Value \|= (op & UINT64_C(`8`)) << `19`;
4924	Value \|= (op & UINT64_C(`7`)) << `13`;
4925	// op: Qm
4926	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
4927	Value \|= (op & UINT64_C(`8`)) << `2`;
4928	Value \|= (op & UINT64_C(`7`)) << `1`;
4929	// op: imm
4930	op = getShiftRight32Imm(MI, `2`, Fixups, STI);
4931	op &= UINT64_C(`31`);
4932	op <<= `16`;
4933	Value \|= op;
4934	break;
4935	}
4936	case ARM::MVE_VRSHR_imms8:
4937	case ARM::MVE_VRSHR_immu8:
4938	case ARM::MVE_VSHR_imms8:
4939	case ARM::MVE_VSHR_immu8: {
4940	// op: Qd
4941	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
4942	Value \|= (op & UINT64_C(`8`)) << `19`;
4943	Value \|= (op & UINT64_C(`7`)) << `13`;
4944	// op: Qm
4945	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
4946	Value \|= (op & UINT64_C(`8`)) << `2`;
4947	Value \|= (op & UINT64_C(`7`)) << `1`;
4948	// op: imm
4949	op = getShiftRight8Imm(MI, `2`, Fixups, STI);
4950	op &= UINT64_C(`7`);
4951	op <<= `16`;
4952	Value \|= op;
4953	break;
4954	}
4955	case ARM::MVE_VCVTf16f32bh:
4956	case ARM::MVE_VCVTf16f32th:
4957	case ARM::MVE_VMAXAs16:
4958	case ARM::MVE_VMAXAs32:
4959	case ARM::MVE_VMAXAs8:
4960	case ARM::MVE_VMAXNMAf16:
4961	case ARM::MVE_VMAXNMAf32:
4962	case ARM::MVE_VMINAs16:
4963	case ARM::MVE_VMINAs32:
4964	case ARM::MVE_VMINAs8:
4965	case ARM::MVE_VMINNMAf16:
4966	case ARM::MVE_VMINNMAf32:
4967	case ARM::MVE_VMOVNi16bh:
4968	case ARM::MVE_VMOVNi16th:
4969	case ARM::MVE_VMOVNi32bh:
4970	case ARM::MVE_VMOVNi32th:
4971	case ARM::MVE_VQMOVNs16bh:
4972	case ARM::MVE_VQMOVNs16th:
4973	case ARM::MVE_VQMOVNs32bh:
4974	case ARM::MVE_VQMOVNs32th:
4975	case ARM::MVE_VQMOVNu16bh:
4976	case ARM::MVE_VQMOVNu16th:
4977	case ARM::MVE_VQMOVNu32bh:
4978	case ARM::MVE_VQMOVNu32th:
4979	case ARM::MVE_VQMOVUNs16bh:
4980	case ARM::MVE_VQMOVUNs16th:
4981	case ARM::MVE_VQMOVUNs32bh:
4982	case ARM::MVE_VQMOVUNs32th: {
4983	// op: Qd
4984	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
4985	Value \|= (op & UINT64_C(`8`)) << `19`;
4986	Value \|= (op & UINT64_C(`7`)) << `13`;
4987	// op: Qm
4988	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
4989	Value \|= (op & UINT64_C(`8`)) << `2`;
4990	Value \|= (op & UINT64_C(`7`)) << `1`;
4991	break;
4992	}
4993	case ARM::MVE_VAND:
4994	case ARM::MVE_VBIC:
4995	case ARM::MVE_VEOR:
4996	case ARM::MVE_VMULHs16:
4997	case ARM::MVE_VMULHs32:
4998	case ARM::MVE_VMULHs8:
4999	case ARM::MVE_VMULHu16:
5000	case ARM::MVE_VMULHu32:
5001	case ARM::MVE_VMULHu8:
5002	case ARM::MVE_VMULLBp16:
5003	case ARM::MVE_VMULLBp8:
5004	case ARM::MVE_VMULLBs16:
5005	case ARM::MVE_VMULLBs32:
5006	case ARM::MVE_VMULLBs8:
5007	case ARM::MVE_VMULLBu16:
5008	case ARM::MVE_VMULLBu32:
5009	case ARM::MVE_VMULLBu8:
5010	case ARM::MVE_VMULLTp16:
5011	case ARM::MVE_VMULLTp8:
5012	case ARM::MVE_VMULLTs16:
5013	case ARM::MVE_VMULLTs32:
5014	case ARM::MVE_VMULLTs8:
5015	case ARM::MVE_VMULLTu16:
5016	case ARM::MVE_VMULLTu32:
5017	case ARM::MVE_VMULLTu8:
5018	case ARM::MVE_VORN:
5019	case ARM::MVE_VORR:
5020	case ARM::MVE_VQDMULLs16bh:
5021	case ARM::MVE_VQDMULLs16th:
5022	case ARM::MVE_VQDMULLs32bh:
5023	case ARM::MVE_VQDMULLs32th:
5024	case ARM::MVE_VRMULHs16:
5025	case ARM::MVE_VRMULHs32:
5026	case ARM::MVE_VRMULHs8:
5027	case ARM::MVE_VRMULHu16:
5028	case ARM::MVE_VRMULHu32:
5029	case ARM::MVE_VRMULHu8: {
5030	// op: Qd
5031	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
5032	Value \|= (op & UINT64_C(`8`)) << `19`;
5033	Value \|= (op & UINT64_C(`7`)) << `13`;
5034	// op: Qm
5035	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
5036	Value \|= (op & UINT64_C(`8`)) << `2`;
5037	Value \|= (op & UINT64_C(`7`)) << `1`;
5038	// op: Qn
5039	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
5040	Value \|= (op & UINT64_C(`7`)) << `17`;
5041	Value \|= (op & UINT64_C(`8`)) << `4`;
5042	break;
5043	}
5044	case ARM::MVE_VCMULf16:
5045	case ARM::MVE_VCMULf32: {
5046	// op: Qd
5047	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
5048	Value \|= (op & UINT64_C(`8`)) << `19`;
5049	Value \|= (op & UINT64_C(`7`)) << `13`;
5050	// op: Qm
5051	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
5052	Value \|= (op & UINT64_C(`8`)) << `2`;
5053	Value \|= (op & UINT64_C(`7`)) << `1`;
5054	// op: Qn
5055	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
5056	Value \|= (op & UINT64_C(`7`)) << `17`;
5057	Value \|= (op & UINT64_C(`8`)) << `4`;
5058	// op: rot
5059	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
5060	Value \|= (op & UINT64_C(`2`)) << `11`;
5061	Value \|= (op & UINT64_C(`1`));
5062	break;
5063	}
5064	case ARM::MVE_VCADDi16:
5065	case ARM::MVE_VCADDi32:
5066	case ARM::MVE_VCADDi8:
5067	case ARM::MVE_VHCADDs16:
5068	case ARM::MVE_VHCADDs32:
5069	case ARM::MVE_VHCADDs8: {
5070	// op: Qd
5071	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
5072	Value \|= (op & UINT64_C(`8`)) << `19`;
5073	Value \|= (op & UINT64_C(`7`)) << `13`;
5074	// op: Qm
5075	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
5076	Value \|= (op & UINT64_C(`8`)) << `2`;
5077	Value \|= (op & UINT64_C(`7`)) << `1`;
5078	// op: Qn
5079	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
5080	Value \|= (op & UINT64_C(`7`)) << `17`;
5081	Value \|= (op & UINT64_C(`8`)) << `4`;
5082	// op: rot
5083	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
5084	op &= UINT64_C(`1`);
5085	op <<= `12`;
5086	Value \|= op;
5087	break;
5088	}
5089	case ARM::MVE_VSLIimm16: {
5090	// op: Qd
5091	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
5092	Value \|= (op & UINT64_C(`8`)) << `19`;
5093	Value \|= (op & UINT64_C(`7`)) << `13`;
5094	// op: Qm
5095	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
5096	Value \|= (op & UINT64_C(`8`)) << `2`;
5097	Value \|= (op & UINT64_C(`7`)) << `1`;
5098	// op: imm
5099	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
5100	op &= UINT64_C(`15`);
5101	op <<= `16`;
5102	Value \|= op;
5103	break;
5104	}
5105	case ARM::MVE_VSLIimm32: {
5106	// op: Qd
5107	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
5108	Value \|= (op & UINT64_C(`8`)) << `19`;
5109	Value \|= (op & UINT64_C(`7`)) << `13`;
5110	// op: Qm
5111	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
5112	Value \|= (op & UINT64_C(`8`)) << `2`;
5113	Value \|= (op & UINT64_C(`7`)) << `1`;
5114	// op: imm
5115	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
5116	op &= UINT64_C(`31`);
5117	op <<= `16`;
5118	Value \|= op;
5119	break;
5120	}
5121	case ARM::MVE_VSLIimm8: {
5122	// op: Qd
5123	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
5124	Value \|= (op & UINT64_C(`8`)) << `19`;
5125	Value \|= (op & UINT64_C(`7`)) << `13`;
5126	// op: Qm
5127	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
5128	Value \|= (op & UINT64_C(`8`)) << `2`;
5129	Value \|= (op & UINT64_C(`7`)) << `1`;
5130	// op: imm
5131	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
5132	op &= UINT64_C(`7`);
5133	op <<= `16`;
5134	Value \|= op;
5135	break;
5136	}
5137	case ARM::MVE_VQRSHRNbhs32:
5138	case ARM::MVE_VQRSHRNbhu32:
5139	case ARM::MVE_VQRSHRNths32:
5140	case ARM::MVE_VQRSHRNthu32:
5141	case ARM::MVE_VQRSHRUNs32bh:
5142	case ARM::MVE_VQRSHRUNs32th:
5143	case ARM::MVE_VQSHRNbhs32:
5144	case ARM::MVE_VQSHRNbhu32:
5145	case ARM::MVE_VQSHRNths32:
5146	case ARM::MVE_VQSHRNthu32:
5147	case ARM::MVE_VQSHRUNs32bh:
5148	case ARM::MVE_VQSHRUNs32th:
5149	case ARM::MVE_VRSHRNi32bh:
5150	case ARM::MVE_VRSHRNi32th:
5151	case ARM::MVE_VSHRNi32bh:
5152	case ARM::MVE_VSHRNi32th:
5153	case ARM::MVE_VSRIimm16: {
5154	// op: Qd
5155	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
5156	Value \|= (op & UINT64_C(`8`)) << `19`;
5157	Value \|= (op & UINT64_C(`7`)) << `13`;
5158	// op: Qm
5159	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
5160	Value \|= (op & UINT64_C(`8`)) << `2`;
5161	Value \|= (op & UINT64_C(`7`)) << `1`;
5162	// op: imm
5163	op = getShiftRight16Imm(MI, `3`, Fixups, STI);
5164	op &= UINT64_C(`15`);
5165	op <<= `16`;
5166	Value \|= op;
5167	break;
5168	}
5169	case ARM::MVE_VSRIimm32: {
5170	// op: Qd
5171	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
5172	Value \|= (op & UINT64_C(`8`)) << `19`;
5173	Value \|= (op & UINT64_C(`7`)) << `13`;
5174	// op: Qm
5175	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
5176	Value \|= (op & UINT64_C(`8`)) << `2`;
5177	Value \|= (op & UINT64_C(`7`)) << `1`;
5178	// op: imm
5179	op = getShiftRight32Imm(MI, `3`, Fixups, STI);
5180	op &= UINT64_C(`31`);
5181	op <<= `16`;
5182	Value \|= op;
5183	break;
5184	}
5185	case ARM::MVE_VQRSHRNbhs16:
5186	case ARM::MVE_VQRSHRNbhu16:
5187	case ARM::MVE_VQRSHRNths16:
5188	case ARM::MVE_VQRSHRNthu16:
5189	case ARM::MVE_VQRSHRUNs16bh:
5190	case ARM::MVE_VQRSHRUNs16th:
5191	case ARM::MVE_VQSHRNbhs16:
5192	case ARM::MVE_VQSHRNbhu16:
5193	case ARM::MVE_VQSHRNths16:
5194	case ARM::MVE_VQSHRNthu16:
5195	case ARM::MVE_VQSHRUNs16bh:
5196	case ARM::MVE_VQSHRUNs16th:
5197	case ARM::MVE_VRSHRNi16bh:
5198	case ARM::MVE_VRSHRNi16th:
5199	case ARM::MVE_VSHRNi16bh:
5200	case ARM::MVE_VSHRNi16th:
5201	case ARM::MVE_VSRIimm8: {
5202	// op: Qd
5203	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
5204	Value \|= (op & UINT64_C(`8`)) << `19`;
5205	Value \|= (op & UINT64_C(`7`)) << `13`;
5206	// op: Qm
5207	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
5208	Value \|= (op & UINT64_C(`8`)) << `2`;
5209	Value \|= (op & UINT64_C(`7`)) << `1`;
5210	// op: imm
5211	op = getShiftRight8Imm(MI, `3`, Fixups, STI);
5212	op &= UINT64_C(`7`);
5213	op <<= `16`;
5214	Value \|= op;
5215	break;
5216	}
5217	case ARM::MVE_VADC:
5218	case ARM::MVE_VADCI:
5219	case ARM::MVE_VQDMLADHXs16:
5220	case ARM::MVE_VQDMLADHXs32:
5221	case ARM::MVE_VQDMLADHXs8:
5222	case ARM::MVE_VQDMLADHs16:
5223	case ARM::MVE_VQDMLADHs32:
5224	case ARM::MVE_VQDMLADHs8:
5225	case ARM::MVE_VQDMLSDHXs16:
5226	case ARM::MVE_VQDMLSDHXs32:
5227	case ARM::MVE_VQDMLSDHXs8:
5228	case ARM::MVE_VQDMLSDHs16:
5229	case ARM::MVE_VQDMLSDHs32:
5230	case ARM::MVE_VQDMLSDHs8:
5231	case ARM::MVE_VQRDMLADHXs16:
5232	case ARM::MVE_VQRDMLADHXs32:
5233	case ARM::MVE_VQRDMLADHXs8:
5234	case ARM::MVE_VQRDMLADHs16:
5235	case ARM::MVE_VQRDMLADHs32:
5236	case ARM::MVE_VQRDMLADHs8:
5237	case ARM::MVE_VQRDMLSDHXs16:
5238	case ARM::MVE_VQRDMLSDHXs32:
5239	case ARM::MVE_VQRDMLSDHXs8:
5240	case ARM::MVE_VQRDMLSDHs16:
5241	case ARM::MVE_VQRDMLSDHs32:
5242	case ARM::MVE_VQRDMLSDHs8:
5243	case ARM::MVE_VSBC:
5244	case ARM::MVE_VSBCI: {
5245	// op: Qd
5246	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
5247	Value \|= (op & UINT64_C(`8`)) << `19`;
5248	Value \|= (op & UINT64_C(`7`)) << `13`;
5249	// op: Qm
5250	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
5251	Value \|= (op & UINT64_C(`8`)) << `2`;
5252	Value \|= (op & UINT64_C(`7`)) << `1`;
5253	// op: Qn
5254	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
5255	Value \|= (op & UINT64_C(`7`)) << `17`;
5256	Value \|= (op & UINT64_C(`8`)) << `4`;
5257	break;
5258	}
5259	case ARM::MVE_VABDs16:
5260	case ARM::MVE_VABDs32:
5261	case ARM::MVE_VABDs8:
5262	case ARM::MVE_VABDu16:
5263	case ARM::MVE_VABDu32:
5264	case ARM::MVE_VABDu8:
5265	case ARM::MVE_VADDi16:
5266	case ARM::MVE_VADDi32:
5267	case ARM::MVE_VADDi8:
5268	case ARM::MVE_VHADDs16:
5269	case ARM::MVE_VHADDs32:
5270	case ARM::MVE_VHADDs8:
5271	case ARM::MVE_VHADDu16:
5272	case ARM::MVE_VHADDu32:
5273	case ARM::MVE_VHADDu8:
5274	case ARM::MVE_VHSUBs16:
5275	case ARM::MVE_VHSUBs32:
5276	case ARM::MVE_VHSUBs8:
5277	case ARM::MVE_VHSUBu16:
5278	case ARM::MVE_VHSUBu32:
5279	case ARM::MVE_VHSUBu8:
5280	case ARM::MVE_VMAXNMf16:
5281	case ARM::MVE_VMAXNMf32:
5282	case ARM::MVE_VMAXs16:
5283	case ARM::MVE_VMAXs32:
5284	case ARM::MVE_VMAXs8:
5285	case ARM::MVE_VMAXu16:
5286	case ARM::MVE_VMAXu32:
5287	case ARM::MVE_VMAXu8:
5288	case ARM::MVE_VMINNMf16:
5289	case ARM::MVE_VMINNMf32:
5290	case ARM::MVE_VMINs16:
5291	case ARM::MVE_VMINs32:
5292	case ARM::MVE_VMINs8:
5293	case ARM::MVE_VMINu16:
5294	case ARM::MVE_VMINu32:
5295	case ARM::MVE_VMINu8:
5296	case ARM::MVE_VMULi16:
5297	case ARM::MVE_VMULi32:
5298	case ARM::MVE_VMULi8:
5299	case ARM::MVE_VQADDs16:
5300	case ARM::MVE_VQADDs32:
5301	case ARM::MVE_VQADDs8:
5302	case ARM::MVE_VQADDu16:
5303	case ARM::MVE_VQADDu32:
5304	case ARM::MVE_VQADDu8:
5305	case ARM::MVE_VQDMULHi16:
5306	case ARM::MVE_VQDMULHi32:
5307	case ARM::MVE_VQDMULHi8:
5308	case ARM::MVE_VQRDMULHi16:
5309	case ARM::MVE_VQRDMULHi32:
5310	case ARM::MVE_VQRDMULHi8:
5311	case ARM::MVE_VQSUBs16:
5312	case ARM::MVE_VQSUBs32:
5313	case ARM::MVE_VQSUBs8:
5314	case ARM::MVE_VQSUBu16:
5315	case ARM::MVE_VQSUBu32:
5316	case ARM::MVE_VQSUBu8:
5317	case ARM::MVE_VRHADDs16:
5318	case ARM::MVE_VRHADDs32:
5319	case ARM::MVE_VRHADDs8:
5320	case ARM::MVE_VRHADDu16:
5321	case ARM::MVE_VRHADDu32:
5322	case ARM::MVE_VRHADDu8:
5323	case ARM::MVE_VSUBi16:
5324	case ARM::MVE_VSUBi32:
5325	case ARM::MVE_VSUBi8: {
5326	// op: Qd
5327	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
5328	Value \|= (op & UINT64_C(`8`)) << `19`;
5329	Value \|= (op & UINT64_C(`7`)) << `13`;
5330	// op: Qn
5331	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
5332	Value \|= (op & UINT64_C(`7`)) << `17`;
5333	Value \|= (op & UINT64_C(`8`)) << `4`;
5334	// op: Qm
5335	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
5336	Value \|= (op & UINT64_C(`8`)) << `2`;
5337	Value \|= (op & UINT64_C(`7`)) << `1`;
5338	break;
5339	}
5340	case ARM::MVE_VADD_qr_f16:
5341	case ARM::MVE_VADD_qr_f32:
5342	case ARM::MVE_VADD_qr_i16:
5343	case ARM::MVE_VADD_qr_i32:
5344	case ARM::MVE_VADD_qr_i8:
5345	case ARM::MVE_VBRSR16:
5346	case ARM::MVE_VBRSR32:
5347	case ARM::MVE_VBRSR8:
5348	case ARM::MVE_VHADD_qr_s16:
5349	case ARM::MVE_VHADD_qr_s32:
5350	case ARM::MVE_VHADD_qr_s8:
5351	case ARM::MVE_VHADD_qr_u16:
5352	case ARM::MVE_VHADD_qr_u32:
5353	case ARM::MVE_VHADD_qr_u8:
5354	case ARM::MVE_VHSUB_qr_s16:
5355	case ARM::MVE_VHSUB_qr_s32:
5356	case ARM::MVE_VHSUB_qr_s8:
5357	case ARM::MVE_VHSUB_qr_u16:
5358	case ARM::MVE_VHSUB_qr_u32:
5359	case ARM::MVE_VHSUB_qr_u8:
5360	case ARM::MVE_VMUL_qr_f16:
5361	case ARM::MVE_VMUL_qr_f32:
5362	case ARM::MVE_VMUL_qr_i16:
5363	case ARM::MVE_VMUL_qr_i32:
5364	case ARM::MVE_VMUL_qr_i8:
5365	case ARM::MVE_VQADD_qr_s16:
5366	case ARM::MVE_VQADD_qr_s32:
5367	case ARM::MVE_VQADD_qr_s8:
5368	case ARM::MVE_VQADD_qr_u16:
5369	case ARM::MVE_VQADD_qr_u32:
5370	case ARM::MVE_VQADD_qr_u8:
5371	case ARM::MVE_VQDMULH_qr_s16:
5372	case ARM::MVE_VQDMULH_qr_s32:
5373	case ARM::MVE_VQDMULH_qr_s8:
5374	case ARM::MVE_VQDMULL_qr_s16bh:
5375	case ARM::MVE_VQDMULL_qr_s16th:
5376	case ARM::MVE_VQDMULL_qr_s32bh:
5377	case ARM::MVE_VQDMULL_qr_s32th:
5378	case ARM::MVE_VQRDMULH_qr_s16:
5379	case ARM::MVE_VQRDMULH_qr_s32:
5380	case ARM::MVE_VQRDMULH_qr_s8:
5381	case ARM::MVE_VQSUB_qr_s16:
5382	case ARM::MVE_VQSUB_qr_s32:
5383	case ARM::MVE_VQSUB_qr_s8:
5384	case ARM::MVE_VQSUB_qr_u16:
5385	case ARM::MVE_VQSUB_qr_u32:
5386	case ARM::MVE_VQSUB_qr_u8:
5387	case ARM::MVE_VSUB_qr_f16:
5388	case ARM::MVE_VSUB_qr_f32:
5389	case ARM::MVE_VSUB_qr_i16:
5390	case ARM::MVE_VSUB_qr_i32:
5391	case ARM::MVE_VSUB_qr_i8: {
5392	// op: Qd
5393	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
5394	Value \|= (op & UINT64_C(`8`)) << `19`;
5395	Value \|= (op & UINT64_C(`7`)) << `13`;
5396	// op: Qn
5397	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
5398	Value \|= (op & UINT64_C(`7`)) << `17`;
5399	Value \|= (op & UINT64_C(`8`)) << `4`;
5400	// op: Rm
5401	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
5402	op &= UINT64_C(`15`);
5403	Value \|= op;
5404	break;
5405	}
5406	case ARM::MVE_VFMA_qr_Sf16:
5407	case ARM::MVE_VFMA_qr_Sf32:
5408	case ARM::MVE_VFMA_qr_f16:
5409	case ARM::MVE_VFMA_qr_f32:
5410	case ARM::MVE_VMLAS_qr_s16:
5411	case ARM::MVE_VMLAS_qr_s32:
5412	case ARM::MVE_VMLAS_qr_s8:
5413	case ARM::MVE_VMLAS_qr_u16:
5414	case ARM::MVE_VMLAS_qr_u32:
5415	case ARM::MVE_VMLAS_qr_u8:
5416	case ARM::MVE_VMLA_qr_s16:
5417	case ARM::MVE_VMLA_qr_s32:
5418	case ARM::MVE_VMLA_qr_s8:
5419	case ARM::MVE_VMLA_qr_u16:
5420	case ARM::MVE_VMLA_qr_u32:
5421	case ARM::MVE_VMLA_qr_u8:
5422	case ARM::MVE_VQDMLAH_qrs16:
5423	case ARM::MVE_VQDMLAH_qrs32:
5424	case ARM::MVE_VQDMLAH_qrs8:
5425	case ARM::MVE_VQDMLASH_qrs16:
5426	case ARM::MVE_VQDMLASH_qrs32:
5427	case ARM::MVE_VQDMLASH_qrs8:
5428	case ARM::MVE_VQRDMLAH_qrs16:
5429	case ARM::MVE_VQRDMLAH_qrs32:
5430	case ARM::MVE_VQRDMLAH_qrs8:
5431	case ARM::MVE_VQRDMLASH_qrs16:
5432	case ARM::MVE_VQRDMLASH_qrs32:
5433	case ARM::MVE_VQRDMLASH_qrs8: {
5434	// op: Qd
5435	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
5436	Value \|= (op & UINT64_C(`8`)) << `19`;
5437	Value \|= (op & UINT64_C(`7`)) << `13`;
5438	// op: Qn
5439	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
5440	Value \|= (op & UINT64_C(`7`)) << `17`;
5441	Value \|= (op & UINT64_C(`8`)) << `4`;
5442	// op: Rm
5443	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
5444	op &= UINT64_C(`15`);
5445	Value \|= op;
5446	break;
5447	}
5448	case ARM::MVE_VQRSHL_qrs16:
5449	case ARM::MVE_VQRSHL_qrs32:
5450	case ARM::MVE_VQRSHL_qrs8:
5451	case ARM::MVE_VQRSHL_qru16:
5452	case ARM::MVE_VQRSHL_qru32:
5453	case ARM::MVE_VQRSHL_qru8:
5454	case ARM::MVE_VQSHL_qrs16:
5455	case ARM::MVE_VQSHL_qrs32:
5456	case ARM::MVE_VQSHL_qrs8:
5457	case ARM::MVE_VQSHL_qru16:
5458	case ARM::MVE_VQSHL_qru32:
5459	case ARM::MVE_VQSHL_qru8:
5460	case ARM::MVE_VRSHL_qrs16:
5461	case ARM::MVE_VRSHL_qrs32:
5462	case ARM::MVE_VRSHL_qrs8:
5463	case ARM::MVE_VRSHL_qru16:
5464	case ARM::MVE_VRSHL_qru32:
5465	case ARM::MVE_VRSHL_qru8:
5466	case ARM::MVE_VSHL_qrs16:
5467	case ARM::MVE_VSHL_qrs32:
5468	case ARM::MVE_VSHL_qrs8:
5469	case ARM::MVE_VSHL_qru16:
5470	case ARM::MVE_VSHL_qru32:
5471	case ARM::MVE_VSHL_qru8: {
5472	// op: Qd
5473	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
5474	Value \|= (op & UINT64_C(`8`)) << `19`;
5475	Value \|= (op & UINT64_C(`7`)) << `13`;
5476	// op: Rm
5477	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
5478	op &= UINT64_C(`15`);
5479	Value \|= op;
5480	break;
5481	}
5482	case ARM::MVE_VDWDUPu16:
5483	case ARM::MVE_VDWDUPu32:
5484	case ARM::MVE_VDWDUPu8:
5485	case ARM::MVE_VIWDUPu16:
5486	case ARM::MVE_VIWDUPu32:
5487	case ARM::MVE_VIWDUPu8: {
5488	// op: Qd
5489	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
5490	Value \|= (op & UINT64_C(`8`)) << `19`;
5491	Value \|= (op & UINT64_C(`7`)) << `13`;
5492	// op: Rm
5493	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
5494	op &= UINT64_C(`14`);
5495	Value \|= op;
5496	// op: Rn
5497	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
5498	op &= UINT64_C(`14`);
5499	op <<= `16`;
5500	Value \|= op;
5501	// op: imm
5502	op = getPowerTwoOpValue(MI, `4`, Fixups, STI);
5503	Value \|= (op & UINT64_C(`2`)) << `6`;
5504	Value \|= (op & UINT64_C(`1`));
5505	break;
5506	}
5507	case ARM::MVE_VDDUPu16:
5508	case ARM::MVE_VDDUPu32:
5509	case ARM::MVE_VDDUPu8:
5510	case ARM::MVE_VIDUPu16:
5511	case ARM::MVE_VIDUPu32:
5512	case ARM::MVE_VIDUPu8: {
5513	// op: Qd
5514	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
5515	Value \|= (op & UINT64_C(`8`)) << `19`;
5516	Value \|= (op & UINT64_C(`7`)) << `13`;
5517	// op: Rn
5518	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
5519	op &= UINT64_C(`14`);
5520	op <<= `16`;
5521	Value \|= op;
5522	// op: imm
5523	op = getPowerTwoOpValue(MI, `3`, Fixups, STI);
5524	Value \|= (op & UINT64_C(`2`)) << `6`;
5525	Value \|= (op & UINT64_C(`1`));
5526	break;
5527	}
5528	case ARM::MVE_VLDRWU32_qi:
5529	case ARM::MVE_VSTRW32_qi: {
5530	// op: Qd
5531	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
5532	op &= UINT64_C(`7`);
5533	op <<= `13`;
5534	Value \|= op;
5535	// op: addr
5536	op = getMveAddrModeQOpValue<`2`>(MI, `1`, Fixups, STI);
5537	Value \|= (op & UINT64_C(`128`)) << `16`;
5538	Value \|= (op & UINT64_C(`1792`)) << `9`;
5539	Value \|= (op & UINT64_C(`127`));
5540	break;
5541	}
5542	case ARM::MVE_VLDRDU64_qi:
5543	case ARM::MVE_VSTRD64_qi: {
5544	// op: Qd
5545	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
5546	op &= UINT64_C(`7`);
5547	op <<= `13`;
5548	Value \|= op;
5549	// op: addr
5550	op = getMveAddrModeQOpValue<`3`>(MI, `1`, Fixups, STI);
5551	Value \|= (op & UINT64_C(`128`)) << `16`;
5552	Value \|= (op & UINT64_C(`1792`)) << `9`;
5553	Value \|= (op & UINT64_C(`127`));
5554	break;
5555	}
5556	case ARM::MVE_VLDRBS16_rq:
5557	case ARM::MVE_VLDRBS32_rq:
5558	case ARM::MVE_VLDRBU16_rq:
5559	case ARM::MVE_VLDRBU32_rq:
5560	case ARM::MVE_VLDRBU8_rq:
5561	case ARM::MVE_VLDRDU64_rq:
5562	case ARM::MVE_VLDRDU64_rq_u:
5563	case ARM::MVE_VLDRHS32_rq:
5564	case ARM::MVE_VLDRHS32_rq_u:
5565	case ARM::MVE_VLDRHU16_rq:
5566	case ARM::MVE_VLDRHU16_rq_u:
5567	case ARM::MVE_VLDRHU32_rq:
5568	case ARM::MVE_VLDRHU32_rq_u:
5569	case ARM::MVE_VLDRWU32_rq:
5570	case ARM::MVE_VLDRWU32_rq_u:
5571	case ARM::MVE_VSTRB16_rq:
5572	case ARM::MVE_VSTRB32_rq:
5573	case ARM::MVE_VSTRB8_rq:
5574	case ARM::MVE_VSTRD64_rq:
5575	case ARM::MVE_VSTRD64_rq_u:
5576	case ARM::MVE_VSTRH16_rq:
5577	case ARM::MVE_VSTRH16_rq_u:
5578	case ARM::MVE_VSTRH32_rq:
5579	case ARM::MVE_VSTRH32_rq_u:
5580	case ARM::MVE_VSTRW32_rq:
5581	case ARM::MVE_VSTRW32_rq_u: {
5582	// op: Qd
5583	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
5584	op &= UINT64_C(`7`);
5585	op <<= `13`;
5586	Value \|= op;
5587	// op: addr
5588	op = getMveAddrModeRQOpValue(MI, `1`, Fixups, STI);
5589	Value \|= (op & UINT64_C(`120`)) << `13`;
5590	Value \|= (op & UINT64_C(`7`)) << `1`;
5591	break;
5592	}
5593	case ARM::MVE_VLDRBS16:
5594	case ARM::MVE_VLDRBS32:
5595	case ARM::MVE_VLDRBU16:
5596	case ARM::MVE_VLDRBU32:
5597	case ARM::MVE_VSTRB16:
5598	case ARM::MVE_VSTRB32: {
5599	// op: Qd
5600	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
5601	op &= UINT64_C(`7`);
5602	op <<= `13`;
5603	Value \|= op;
5604	// op: addr
5605	op = getT2AddrModeImmOpValue<`7`,`0`>(MI, `1`, Fixups, STI);
5606	Value \|= (op & UINT64_C(`128`)) << `16`;
5607	Value \|= (op & UINT64_C(`1792`)) << `8`;
5608	Value \|= (op & UINT64_C(`127`));
5609	break;
5610	}
5611	case ARM::MVE_VLDRBU8:
5612	case ARM::MVE_VSTRBU8: {
5613	// op: Qd
5614	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
5615	op &= UINT64_C(`7`);
5616	op <<= `13`;
5617	Value \|= op;
5618	// op: addr
5619	op = getT2AddrModeImmOpValue<`7`,`0`>(MI, `1`, Fixups, STI);
5620	Value \|= (op & UINT64_C(`128`)) << `16`;
5621	Value \|= (op & UINT64_C(`3840`)) << `8`;
5622	Value \|= (op & UINT64_C(`127`));
5623	break;
5624	}
5625	case ARM::MVE_VLDRHS32:
5626	case ARM::MVE_VLDRHU32:
5627	case ARM::MVE_VSTRH32: {
5628	// op: Qd
5629	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
5630	op &= UINT64_C(`7`);
5631	op <<= `13`;
5632	Value \|= op;
5633	// op: addr
5634	op = getT2AddrModeImmOpValue<`7`,`1`>(MI, `1`, Fixups, STI);
5635	Value \|= (op & UINT64_C(`128`)) << `16`;
5636	Value \|= (op & UINT64_C(`1792`)) << `8`;
5637	Value \|= (op & UINT64_C(`127`));
5638	break;
5639	}
5640	case ARM::MVE_VLDRHU16:
5641	case ARM::MVE_VSTRHU16: {
5642	// op: Qd
5643	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
5644	op &= UINT64_C(`7`);
5645	op <<= `13`;
5646	Value \|= op;
5647	// op: addr
5648	op = getT2AddrModeImmOpValue<`7`,`1`>(MI, `1`, Fixups, STI);
5649	Value \|= (op & UINT64_C(`128`)) << `16`;
5650	Value \|= (op & UINT64_C(`3840`)) << `8`;
5651	Value \|= (op & UINT64_C(`127`));
5652	break;
5653	}
5654	case ARM::MVE_VLDRWU32:
5655	case ARM::MVE_VSTRWU32: {
5656	// op: Qd
5657	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
5658	op &= UINT64_C(`7`);
5659	op <<= `13`;
5660	Value \|= op;
5661	// op: addr
5662	op = getT2AddrModeImmOpValue<`7`,`2`>(MI, `1`, Fixups, STI);
5663	Value \|= (op & UINT64_C(`128`)) << `16`;
5664	Value \|= (op & UINT64_C(`3840`)) << `8`;
5665	Value \|= (op & UINT64_C(`127`));
5666	break;
5667	}
5668	case ARM::MVE_VMOV_from_lane_32: {
5669	// op: Qd
5670	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
5671	Value \|= (op & UINT64_C(`7`)) << `17`;
5672	Value \|= (op & UINT64_C(`8`)) << `4`;
5673	// op: Rt
5674	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
5675	op &= UINT64_C(`15`);
5676	op <<= `12`;
5677	Value \|= op;
5678	// op: Idx
5679	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
5680	Value \|= (op & UINT64_C(`1`)) << `21`;
5681	Value \|= (op & UINT64_C(`2`)) << `15`;
5682	break;
5683	}
5684	case ARM::MVE_VMOV_from_lane_s16:
5685	case ARM::MVE_VMOV_from_lane_u16: {
5686	// op: Qd
5687	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
5688	Value \|= (op & UINT64_C(`7`)) << `17`;
5689	Value \|= (op & UINT64_C(`8`)) << `4`;
5690	// op: Rt
5691	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
5692	op &= UINT64_C(`15`);
5693	op <<= `12`;
5694	Value \|= op;
5695	// op: Idx
5696	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
5697	Value \|= (op & UINT64_C(`2`)) << `20`;
5698	Value \|= (op & UINT64_C(`4`)) << `14`;
5699	Value \|= (op & UINT64_C(`1`)) << `6`;
5700	break;
5701	}
5702	case ARM::MVE_VMOV_from_lane_s8:
5703	case ARM::MVE_VMOV_from_lane_u8: {
5704	// op: Qd
5705	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
5706	Value \|= (op & UINT64_C(`7`)) << `17`;
5707	Value \|= (op & UINT64_C(`8`)) << `4`;
5708	// op: Rt
5709	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
5710	op &= UINT64_C(`15`);
5711	op <<= `12`;
5712	Value \|= op;
5713	// op: Idx
5714	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
5715	Value \|= (op & UINT64_C(`4`)) << `19`;
5716	Value \|= (op & UINT64_C(`8`)) << `13`;
5717	Value \|= (op & UINT64_C(`3`)) << `5`;
5718	break;
5719	}
5720	case ARM::MVE_VLDRWU32_qi_pre:
5721	case ARM::MVE_VSTRW32_qi_pre: {
5722	// op: Qd
5723	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
5724	op &= UINT64_C(`7`);
5725	op <<= `13`;
5726	Value \|= op;
5727	// op: addr
5728	op = getMveAddrModeQOpValue<`2`>(MI, `2`, Fixups, STI);
5729	Value \|= (op & UINT64_C(`128`)) << `16`;
5730	Value \|= (op & UINT64_C(`1792`)) << `9`;
5731	Value \|= (op & UINT64_C(`127`));
5732	break;
5733	}
5734	case ARM::MVE_VLDRDU64_qi_pre:
5735	case ARM::MVE_VSTRD64_qi_pre: {
5736	// op: Qd
5737	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
5738	op &= UINT64_C(`7`);
5739	op <<= `13`;
5740	Value \|= op;
5741	// op: addr
5742	op = getMveAddrModeQOpValue<`3`>(MI, `2`, Fixups, STI);
5743	Value \|= (op & UINT64_C(`128`)) << `16`;
5744	Value \|= (op & UINT64_C(`1792`)) << `9`;
5745	Value \|= (op & UINT64_C(`127`));
5746	break;
5747	}
5748	case ARM::MVE_VLDRBS16_pre:
5749	case ARM::MVE_VLDRBS32_pre:
5750	case ARM::MVE_VLDRBU16_pre:
5751	case ARM::MVE_VLDRBU32_pre:
5752	case ARM::MVE_VSTRB16_pre:
5753	case ARM::MVE_VSTRB32_pre: {
5754	// op: Qd
5755	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
5756	op &= UINT64_C(`7`);
5757	op <<= `13`;
5758	Value \|= op;
5759	// op: addr
5760	op = getT2AddrModeImmOpValue<`7`,`0`>(MI, `2`, Fixups, STI);
5761	Value \|= (op & UINT64_C(`128`)) << `16`;
5762	Value \|= (op & UINT64_C(`1792`)) << `8`;
5763	Value \|= (op & UINT64_C(`127`));
5764	break;
5765	}
5766	case ARM::MVE_VLDRBU8_pre:
5767	case ARM::MVE_VSTRBU8_pre: {
5768	// op: Qd
5769	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
5770	op &= UINT64_C(`7`);
5771	op <<= `13`;
5772	Value \|= op;
5773	// op: addr
5774	op = getT2AddrModeImmOpValue<`7`,`0`>(MI, `2`, Fixups, STI);
5775	Value \|= (op & UINT64_C(`128`)) << `16`;
5776	Value \|= (op & UINT64_C(`3840`)) << `8`;
5777	Value \|= (op & UINT64_C(`127`));
5778	break;
5779	}
5780	case ARM::MVE_VLDRHS32_pre:
5781	case ARM::MVE_VLDRHU32_pre:
5782	case ARM::MVE_VSTRH32_pre: {
5783	// op: Qd
5784	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
5785	op &= UINT64_C(`7`);
5786	op <<= `13`;
5787	Value \|= op;
5788	// op: addr
5789	op = getT2AddrModeImmOpValue<`7`,`1`>(MI, `2`, Fixups, STI);
5790	Value \|= (op & UINT64_C(`128`)) << `16`;
5791	Value \|= (op & UINT64_C(`1792`)) << `8`;
5792	Value \|= (op & UINT64_C(`127`));
5793	break;
5794	}
5795	case ARM::MVE_VLDRHU16_pre:
5796	case ARM::MVE_VSTRHU16_pre: {
5797	// op: Qd
5798	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
5799	op &= UINT64_C(`7`);
5800	op <<= `13`;
5801	Value \|= op;
5802	// op: addr
5803	op = getT2AddrModeImmOpValue<`7`,`1`>(MI, `2`, Fixups, STI);
5804	Value \|= (op & UINT64_C(`128`)) << `16`;
5805	Value \|= (op & UINT64_C(`3840`)) << `8`;
5806	Value \|= (op & UINT64_C(`127`));
5807	break;
5808	}
5809	case ARM::MVE_VLDRWU32_pre:
5810	case ARM::MVE_VSTRWU32_pre: {
5811	// op: Qd
5812	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
5813	op &= UINT64_C(`7`);
5814	op <<= `13`;
5815	Value \|= op;
5816	// op: addr
5817	op = getT2AddrModeImmOpValue<`7`,`2`>(MI, `2`, Fixups, STI);
5818	Value \|= (op & UINT64_C(`128`)) << `16`;
5819	Value \|= (op & UINT64_C(`3840`)) << `8`;
5820	Value \|= (op & UINT64_C(`127`));
5821	break;
5822	}
5823	case ARM::MVE_VLDRBU8_post:
5824	case ARM::MVE_VSTRBU8_post: {
5825	// op: Qd
5826	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
5827	op &= UINT64_C(`7`);
5828	op <<= `13`;
5829	Value \|= op;
5830	// op: addr
5831	op = getT2ScaledImmOpValue<`7`,`0`>(MI, `3`, Fixups, STI);
5832	Value \|= (op & UINT64_C(`128`)) << `16`;
5833	Value \|= (op & UINT64_C(`127`));
5834	// op: Rn
5835	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
5836	op &= UINT64_C(`15`);
5837	op <<= `16`;
5838	Value \|= op;
5839	break;
5840	}
5841	case ARM::MVE_VLDRBS16_post:
5842	case ARM::MVE_VLDRBS32_post:
5843	case ARM::MVE_VLDRBU16_post:
5844	case ARM::MVE_VLDRBU32_post:
5845	case ARM::MVE_VSTRB16_post:
5846	case ARM::MVE_VSTRB32_post: {
5847	// op: Qd
5848	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
5849	op &= UINT64_C(`7`);
5850	op <<= `13`;
5851	Value \|= op;
5852	// op: addr
5853	op = getT2ScaledImmOpValue<`7`,`0`>(MI, `3`, Fixups, STI);
5854	Value \|= (op & UINT64_C(`128`)) << `16`;
5855	Value \|= (op & UINT64_C(`127`));
5856	// op: Rn
5857	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
5858	op &= UINT64_C(`7`);
5859	op <<= `16`;
5860	Value \|= op;
5861	break;
5862	}
5863	case ARM::MVE_VLDRHU16_post:
5864	case ARM::MVE_VSTRHU16_post: {
5865	// op: Qd
5866	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
5867	op &= UINT64_C(`7`);
5868	op <<= `13`;
5869	Value \|= op;
5870	// op: addr
5871	op = getT2ScaledImmOpValue<`7`,`1`>(MI, `3`, Fixups, STI);
5872	Value \|= (op & UINT64_C(`128`)) << `16`;
5873	Value \|= (op & UINT64_C(`127`));
5874	// op: Rn
5875	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
5876	op &= UINT64_C(`15`);
5877	op <<= `16`;
5878	Value \|= op;
5879	break;
5880	}
5881	case ARM::MVE_VLDRHS32_post:
5882	case ARM::MVE_VLDRHU32_post:
5883	case ARM::MVE_VSTRH32_post: {
5884	// op: Qd
5885	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
5886	op &= UINT64_C(`7`);
5887	op <<= `13`;
5888	Value \|= op;
5889	// op: addr
5890	op = getT2ScaledImmOpValue<`7`,`1`>(MI, `3`, Fixups, STI);
5891	Value \|= (op & UINT64_C(`128`)) << `16`;
5892	Value \|= (op & UINT64_C(`127`));
5893	// op: Rn
5894	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
5895	op &= UINT64_C(`7`);
5896	op <<= `16`;
5897	Value \|= op;
5898	break;
5899	}
5900	case ARM::MVE_VLDRWU32_post:
5901	case ARM::MVE_VSTRWU32_post: {
5902	// op: Qd
5903	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
5904	op &= UINT64_C(`7`);
5905	op <<= `13`;
5906	Value \|= op;
5907	// op: addr
5908	op = getT2ScaledImmOpValue<`7`,`2`>(MI, `3`, Fixups, STI);
5909	Value \|= (op & UINT64_C(`128`)) << `16`;
5910	Value \|= (op & UINT64_C(`127`));
5911	// op: Rn
5912	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
5913	op &= UINT64_C(`15`);
5914	op <<= `16`;
5915	Value \|= op;
5916	break;
5917	}
5918	case ARM::MVE_VABSf16:
5919	case ARM::MVE_VABSf32:
5920	case ARM::MVE_VCVTf16s16n:
5921	case ARM::MVE_VCVTf16u16n:
5922	case ARM::MVE_VCVTf32s32n:
5923	case ARM::MVE_VCVTf32u32n:
5924	case ARM::MVE_VCVTs16f16a:
5925	case ARM::MVE_VCVTs16f16m:
5926	case ARM::MVE_VCVTs16f16n:
5927	case ARM::MVE_VCVTs16f16p:
5928	case ARM::MVE_VCVTs16f16z:
5929	case ARM::MVE_VCVTs32f32a:
5930	case ARM::MVE_VCVTs32f32m:
5931	case ARM::MVE_VCVTs32f32n:
5932	case ARM::MVE_VCVTs32f32p:
5933	case ARM::MVE_VCVTs32f32z:
5934	case ARM::MVE_VCVTu16f16a:
5935	case ARM::MVE_VCVTu16f16m:
5936	case ARM::MVE_VCVTu16f16n:
5937	case ARM::MVE_VCVTu16f16p:
5938	case ARM::MVE_VCVTu16f16z:
5939	case ARM::MVE_VCVTu32f32a:
5940	case ARM::MVE_VCVTu32f32m:
5941	case ARM::MVE_VCVTu32f32n:
5942	case ARM::MVE_VCVTu32f32p:
5943	case ARM::MVE_VCVTu32f32z:
5944	case ARM::MVE_VNEGf16:
5945	case ARM::MVE_VNEGf32:
5946	case ARM::MVE_VRINTf16A:
5947	case ARM::MVE_VRINTf16M:
5948	case ARM::MVE_VRINTf16N:
5949	case ARM::MVE_VRINTf16P:
5950	case ARM::MVE_VRINTf16X:
5951	case ARM::MVE_VRINTf16Z:
5952	case ARM::MVE_VRINTf32A:
5953	case ARM::MVE_VRINTf32M:
5954	case ARM::MVE_VRINTf32N:
5955	case ARM::MVE_VRINTf32P:
5956	case ARM::MVE_VRINTf32X:
5957	case ARM::MVE_VRINTf32Z: {
5958	// op: Qm
5959	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
5960	Value \|= (op & UINT64_C(`8`)) << `2`;
5961	Value \|= (op & UINT64_C(`7`)) << `1`;
5962	// op: Qd
5963	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
5964	Value \|= (op & UINT64_C(`8`)) << `19`;
5965	Value \|= (op & UINT64_C(`7`)) << `13`;
5966	break;
5967	}
5968	case ARM::MVE_VCVTf16s16_fix:
5969	case ARM::MVE_VCVTf16u16_fix:
5970	case ARM::MVE_VCVTs16f16_fix:
5971	case ARM::MVE_VCVTu16f16_fix: {
5972	// op: Qm
5973	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
5974	Value \|= (op & UINT64_C(`8`)) << `2`;
5975	Value \|= (op & UINT64_C(`7`)) << `1`;
5976	// op: Qd
5977	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
5978	Value \|= (op & UINT64_C(`8`)) << `19`;
5979	Value \|= (op & UINT64_C(`7`)) << `13`;
5980	// op: imm6
5981	op = getNEONVcvtImm32OpValue(MI, `2`, Fixups, STI);
5982	op &= UINT64_C(`15`);
5983	op <<= `16`;
5984	Value \|= op;
5985	break;
5986	}
5987	case ARM::MVE_VCVTf32s32_fix:
5988	case ARM::MVE_VCVTf32u32_fix:
5989	case ARM::MVE_VCVTs32f32_fix:
5990	case ARM::MVE_VCVTu32f32_fix: {
5991	// op: Qm
5992	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
5993	Value \|= (op & UINT64_C(`8`)) << `2`;
5994	Value \|= (op & UINT64_C(`7`)) << `1`;
5995	// op: Qd
5996	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
5997	Value \|= (op & UINT64_C(`8`)) << `19`;
5998	Value \|= (op & UINT64_C(`7`)) << `13`;
5999	// op: imm6
6000	op = getNEONVcvtImm32OpValue(MI, `2`, Fixups, STI);
6001	op &= UINT64_C(`31`);
6002	op <<= `16`;
6003	Value \|= op;
6004	break;
6005	}
6006	case ARM::MVE_VADDVs16no_acc:
6007	case ARM::MVE_VADDVs32no_acc:
6008	case ARM::MVE_VADDVs8no_acc:
6009	case ARM::MVE_VADDVu16no_acc:
6010	case ARM::MVE_VADDVu32no_acc:
6011	case ARM::MVE_VADDVu8no_acc: {
6012	// op: Qm
6013	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
6014	op &= UINT64_C(`7`);
6015	op <<= `1`;
6016	Value \|= op;
6017	// op: Rda
6018	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6019	op &= UINT64_C(`14`);
6020	op <<= `12`;
6021	Value \|= op;
6022	break;
6023	}
6024	case ARM::MVE_VABDf16:
6025	case ARM::MVE_VABDf32:
6026	case ARM::MVE_VADDf16:
6027	case ARM::MVE_VADDf32:
6028	case ARM::MVE_VMULf16:
6029	case ARM::MVE_VMULf32:
6030	case ARM::MVE_VSUBf16:
6031	case ARM::MVE_VSUBf32: {
6032	// op: Qm
6033	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
6034	Value \|= (op & UINT64_C(`8`)) << `2`;
6035	Value \|= (op & UINT64_C(`7`)) << `1`;
6036	// op: Qd
6037	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6038	Value \|= (op & UINT64_C(`8`)) << `19`;
6039	Value \|= (op & UINT64_C(`7`)) << `13`;
6040	// op: Qn
6041	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
6042	Value \|= (op & UINT64_C(`7`)) << `17`;
6043	Value \|= (op & UINT64_C(`8`)) << `4`;
6044	break;
6045	}
6046	case ARM::MVE_VCADDf16:
6047	case ARM::MVE_VCADDf32: {
6048	// op: Qm
6049	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
6050	Value \|= (op & UINT64_C(`8`)) << `2`;
6051	Value \|= (op & UINT64_C(`7`)) << `1`;
6052	// op: Qd
6053	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6054	Value \|= (op & UINT64_C(`8`)) << `19`;
6055	Value \|= (op & UINT64_C(`7`)) << `13`;
6056	// op: Qn
6057	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
6058	Value \|= (op & UINT64_C(`7`)) << `17`;
6059	Value \|= (op & UINT64_C(`8`)) << `4`;
6060	// op: rot
6061	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
6062	op &= UINT64_C(`1`);
6063	op <<= `24`;
6064	Value \|= op;
6065	break;
6066	}
6067	case ARM::MVE_VADDVs16acc:
6068	case ARM::MVE_VADDVs32acc:
6069	case ARM::MVE_VADDVs8acc:
6070	case ARM::MVE_VADDVu16acc:
6071	case ARM::MVE_VADDVu32acc:
6072	case ARM::MVE_VADDVu8acc: {
6073	// op: Qm
6074	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
6075	op &= UINT64_C(`7`);
6076	op <<= `1`;
6077	Value \|= op;
6078	// op: Rda
6079	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6080	op &= UINT64_C(`14`);
6081	op <<= `12`;
6082	Value \|= op;
6083	break;
6084	}
6085	case ARM::MVE_VMAXAVs16:
6086	case ARM::MVE_VMAXAVs32:
6087	case ARM::MVE_VMAXAVs8:
6088	case ARM::MVE_VMAXNMAVf16:
6089	case ARM::MVE_VMAXNMAVf32:
6090	case ARM::MVE_VMAXNMVf16:
6091	case ARM::MVE_VMAXNMVf32:
6092	case ARM::MVE_VMAXVs16:
6093	case ARM::MVE_VMAXVs32:
6094	case ARM::MVE_VMAXVs8:
6095	case ARM::MVE_VMAXVu16:
6096	case ARM::MVE_VMAXVu32:
6097	case ARM::MVE_VMAXVu8:
6098	case ARM::MVE_VMINAVs16:
6099	case ARM::MVE_VMINAVs32:
6100	case ARM::MVE_VMINAVs8:
6101	case ARM::MVE_VMINNMAVf16:
6102	case ARM::MVE_VMINNMAVf32:
6103	case ARM::MVE_VMINNMVf16:
6104	case ARM::MVE_VMINNMVf32:
6105	case ARM::MVE_VMINVs16:
6106	case ARM::MVE_VMINVs32:
6107	case ARM::MVE_VMINVs8:
6108	case ARM::MVE_VMINVu16:
6109	case ARM::MVE_VMINVu32:
6110	case ARM::MVE_VMINVu8: {
6111	// op: Qm
6112	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
6113	op &= UINT64_C(`7`);
6114	op <<= `1`;
6115	Value \|= op;
6116	// op: RdaDest
6117	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6118	op &= UINT64_C(`15`);
6119	op <<= `12`;
6120	Value \|= op;
6121	break;
6122	}
6123	case ARM::MVE_VADDLVs32no_acc:
6124	case ARM::MVE_VADDLVu32no_acc: {
6125	// op: Qm
6126	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
6127	op &= UINT64_C(`7`);
6128	op <<= `1`;
6129	Value \|= op;
6130	// op: RdaLo
6131	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6132	op &= UINT64_C(`14`);
6133	op <<= `12`;
6134	Value \|= op;
6135	// op: RdaHi
6136	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
6137	op &= UINT64_C(`14`);
6138	op <<= `19`;
6139	Value \|= op;
6140	break;
6141	}
6142	case ARM::MVE_VFMAf16:
6143	case ARM::MVE_VFMAf32:
6144	case ARM::MVE_VFMSf16:
6145	case ARM::MVE_VFMSf32: {
6146	// op: Qm
6147	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
6148	Value \|= (op & UINT64_C(`8`)) << `2`;
6149	Value \|= (op & UINT64_C(`7`)) << `1`;
6150	// op: Qd
6151	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6152	Value \|= (op & UINT64_C(`8`)) << `19`;
6153	Value \|= (op & UINT64_C(`7`)) << `13`;
6154	// op: Qn
6155	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
6156	Value \|= (op & UINT64_C(`7`)) << `17`;
6157	Value \|= (op & UINT64_C(`8`)) << `4`;
6158	break;
6159	}
6160	case ARM::MVE_VCMLAf16:
6161	case ARM::MVE_VCMLAf32: {
6162	// op: Qm
6163	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
6164	Value \|= (op & UINT64_C(`8`)) << `2`;
6165	Value \|= (op & UINT64_C(`7`)) << `1`;
6166	// op: Qd
6167	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6168	Value \|= (op & UINT64_C(`8`)) << `19`;
6169	Value \|= (op & UINT64_C(`7`)) << `13`;
6170	// op: Qn
6171	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
6172	Value \|= (op & UINT64_C(`7`)) << `17`;
6173	Value \|= (op & UINT64_C(`8`)) << `4`;
6174	// op: rot
6175	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
6176	op &= UINT64_C(`3`);
6177	op <<= `23`;
6178	Value \|= op;
6179	break;
6180	}
6181	case ARM::MVE_VABAVs16:
6182	case ARM::MVE_VABAVs32:
6183	case ARM::MVE_VABAVs8:
6184	case ARM::MVE_VABAVu16:
6185	case ARM::MVE_VABAVu32:
6186	case ARM::MVE_VABAVu8: {
6187	// op: Qm
6188	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
6189	Value \|= (op & UINT64_C(`8`)) << `2`;
6190	Value \|= (op & UINT64_C(`7`)) << `1`;
6191	// op: Qn
6192	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
6193	Value \|= (op & UINT64_C(`7`)) << `17`;
6194	Value \|= (op & UINT64_C(`8`)) << `4`;
6195	// op: Rda
6196	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6197	op &= UINT64_C(`15`);
6198	op <<= `12`;
6199	Value \|= op;
6200	break;
6201	}
6202	case ARM::MVE_VADDLVs32acc:
6203	case ARM::MVE_VADDLVu32acc: {
6204	// op: Qm
6205	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
6206	op &= UINT64_C(`7`);
6207	op <<= `1`;
6208	Value \|= op;
6209	// op: RdaLo
6210	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6211	op &= UINT64_C(`14`);
6212	op <<= `12`;
6213	Value \|= op;
6214	// op: RdaHi
6215	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
6216	op &= UINT64_C(`14`);
6217	op <<= `19`;
6218	Value \|= op;
6219	break;
6220	}
6221	case ARM::MVE_VPSEL: {
6222	// op: Qn
6223	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
6224	Value \|= (op & UINT64_C(`7`)) << `17`;
6225	Value \|= (op & UINT64_C(`8`)) << `4`;
6226	// op: Qd
6227	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6228	Value \|= (op & UINT64_C(`8`)) << `19`;
6229	Value \|= (op & UINT64_C(`7`)) << `13`;
6230	// op: Qm
6231	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
6232	Value \|= (op & UINT64_C(`8`)) << `2`;
6233	Value \|= (op & UINT64_C(`7`)) << `1`;
6234	break;
6235	}
6236	case ARM::tMOVr: {
6237	// op: Rd
6238	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6239	Value \|= (op & UINT64_C(`8`)) << `4`;
6240	Value \|= (op & UINT64_C(`7`));
6241	// op: Rm
6242	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
6243	op &= UINT64_C(`15`);
6244	op <<= `3`;
6245	Value \|= op;
6246	break;
6247	}
6248	case ARM::t2STLEX: {
6249	// op: Rd
6250	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6251	op &= UINT64_C(`15`);
6252	Value \|= op;
6253	// op: Rt
6254	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
6255	op &= UINT64_C(`15`);
6256	op <<= `12`;
6257	Value \|= op;
6258	// op: addr
6259	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
6260	op &= UINT64_C(`15`);
6261	op <<= `16`;
6262	Value \|= op;
6263	break;
6264	}
6265	case ARM::t2STLEXB:
6266	case ARM::t2STLEXH:
6267	case ARM::t2STREXB:
6268	case ARM::t2STREXH: {
6269	// op: Rd
6270	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6271	op &= UINT64_C(`15`);
6272	Value \|= op;
6273	// op: addr
6274	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
6275	op &= UINT64_C(`15`);
6276	op <<= `16`;
6277	Value \|= op;
6278	// op: Rt
6279	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
6280	op &= UINT64_C(`15`);
6281	op <<= `12`;
6282	Value \|= op;
6283	break;
6284	}
6285	case ARM::t2STLEXD:
6286	case ARM::t2STREXD: {
6287	// op: Rd
6288	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6289	op &= UINT64_C(`15`);
6290	Value \|= op;
6291	// op: addr
6292	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
6293	op &= UINT64_C(`15`);
6294	op <<= `16`;
6295	Value \|= op;
6296	// op: Rt
6297	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
6298	op &= UINT64_C(`15`);
6299	op <<= `12`;
6300	Value \|= op;
6301	// op: Rt2
6302	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
6303	op &= UINT64_C(`15`);
6304	op <<= `8`;
6305	Value \|= op;
6306	break;
6307	}
6308	case ARM::CRC32B:
6309	case ARM::CRC32CB:
6310	case ARM::CRC32CH:
6311	case ARM::CRC32CW:
6312	case ARM::CRC32H:
6313	case ARM::CRC32W: {
6314	// op: Rd
6315	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6316	op &= UINT64_C(`15`);
6317	op <<= `12`;
6318	Value \|= op;
6319	// op: Rn
6320	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
6321	op &= UINT64_C(`15`);
6322	op <<= `16`;
6323	Value \|= op;
6324	// op: Rm
6325	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
6326	op &= UINT64_C(`15`);
6327	Value \|= op;
6328	break;
6329	}
6330	case ARM::t2MRS_AR:
6331	case ARM::t2MRSsys_AR: {
6332	// op: Rd
6333	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6334	op &= UINT64_C(`15`);
6335	op <<= `8`;
6336	Value \|= op;
6337	break;
6338	}
6339	case ARM::t2CLZ:
6340	case ARM::t2RBIT:
6341	case ARM::t2REV:
6342	case ARM::t2REV16:
6343	case ARM::t2REVSH: {
6344	// op: Rd
6345	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6346	op &= UINT64_C(`15`);
6347	op <<= `8`;
6348	Value \|= op;
6349	// op: Rm
6350	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
6351	Value \|= (op & UINT64_C(`15`)) << `16`;
6352	Value \|= (op & UINT64_C(`15`));
6353	break;
6354	}
6355	case ARM::t2MOVsra_flag:
6356	case ARM::t2MOVsrl_flag: {
6357	// op: Rd
6358	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6359	op &= UINT64_C(`15`);
6360	op <<= `8`;
6361	Value \|= op;
6362	// op: Rm
6363	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
6364	op &= UINT64_C(`15`);
6365	Value \|= op;
6366	break;
6367	}
6368	case ARM::t2SXTB:
6369	case ARM::t2SXTB16:
6370	case ARM::t2SXTH:
6371	case ARM::t2UXTB:
6372	case ARM::t2UXTB16:
6373	case ARM::t2UXTH: {
6374	// op: Rd
6375	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6376	op &= UINT64_C(`15`);
6377	op <<= `8`;
6378	Value \|= op;
6379	// op: Rm
6380	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
6381	op &= UINT64_C(`15`);
6382	Value \|= op;
6383	// op: rot
6384	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
6385	op &= UINT64_C(`3`);
6386	op <<= `4`;
6387	Value \|= op;
6388	break;
6389	}
6390	case ARM::t2CSEL:
6391	case ARM::t2CSINC:
6392	case ARM::t2CSINV:
6393	case ARM::t2CSNEG: {
6394	// op: Rd
6395	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6396	op &= UINT64_C(`15`);
6397	op <<= `8`;
6398	Value \|= op;
6399	// op: Rm
6400	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
6401	op &= UINT64_C(`15`);
6402	Value \|= op;
6403	// op: Rn
6404	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
6405	op &= UINT64_C(`15`);
6406	op <<= `16`;
6407	Value \|= op;
6408	// op: fcond
6409	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
6410	op &= UINT64_C(`15`);
6411	op <<= `4`;
6412	Value \|= op;
6413	break;
6414	}
6415	case ARM::t2CRC32B:
6416	case ARM::t2CRC32CB:
6417	case ARM::t2CRC32CH:
6418	case ARM::t2CRC32CW:
6419	case ARM::t2CRC32H:
6420	case ARM::t2CRC32W:
6421	case ARM::t2MUL:
6422	case ARM::t2QADD16:
6423	case ARM::t2QADD8:
6424	case ARM::t2QASX:
6425	case ARM::t2QSAX:
6426	case ARM::t2QSUB16:
6427	case ARM::t2QSUB8:
6428	case ARM::t2SADD16:
6429	case ARM::t2SADD8:
6430	case ARM::t2SASX:
6431	case ARM::t2SDIV:
6432	case ARM::t2SEL:
6433	case ARM::t2SHADD16:
6434	case ARM::t2SHADD8:
6435	case ARM::t2SHASX:
6436	case ARM::t2SHSAX:
6437	case ARM::t2SHSUB16:
6438	case ARM::t2SHSUB8:
6439	case ARM::t2SMMUL:
6440	case ARM::t2SMMULR:
6441	case ARM::t2SMUAD:
6442	case ARM::t2SMUADX:
6443	case ARM::t2SMULBB:
6444	case ARM::t2SMULBT:
6445	case ARM::t2SMULTB:
6446	case ARM::t2SMULTT:
6447	case ARM::t2SMULWB:
6448	case ARM::t2SMULWT:
6449	case ARM::t2SMUSD:
6450	case ARM::t2SMUSDX:
6451	case ARM::t2SSAX:
6452	case ARM::t2SSUB16:
6453	case ARM::t2SSUB8:
6454	case ARM::t2UADD16:
6455	case ARM::t2UADD8:
6456	case ARM::t2UASX:
6457	case ARM::t2UDIV:
6458	case ARM::t2UHADD16:
6459	case ARM::t2UHADD8:
6460	case ARM::t2UHASX:
6461	case ARM::t2UHSAX:
6462	case ARM::t2UHSUB16:
6463	case ARM::t2UHSUB8:
6464	case ARM::t2UQADD16:
6465	case ARM::t2UQADD8:
6466	case ARM::t2UQASX:
6467	case ARM::t2UQSAX:
6468	case ARM::t2UQSUB16:
6469	case ARM::t2UQSUB8:
6470	case ARM::t2USAD8:
6471	case ARM::t2USAX:
6472	case ARM::t2USUB16:
6473	case ARM::t2USUB8: {
6474	// op: Rd
6475	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6476	op &= UINT64_C(`15`);
6477	op <<= `8`;
6478	Value \|= op;
6479	// op: Rn
6480	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
6481	op &= UINT64_C(`15`);
6482	op <<= `16`;
6483	Value \|= op;
6484	// op: Rm
6485	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
6486	op &= UINT64_C(`15`);
6487	Value \|= op;
6488	break;
6489	}
6490	case ARM::t2MLA:
6491	case ARM::t2MLS:
6492	case ARM::t2SMLABB:
6493	case ARM::t2SMLABT:
6494	case ARM::t2SMLAD:
6495	case ARM::t2SMLADX:
6496	case ARM::t2SMLATB:
6497	case ARM::t2SMLATT:
6498	case ARM::t2SMLAWB:
6499	case ARM::t2SMLAWT:
6500	case ARM::t2SMLSD:
6501	case ARM::t2SMLSDX:
6502	case ARM::t2SMMLA:
6503	case ARM::t2SMMLAR:
6504	case ARM::t2SMMLS:
6505	case ARM::t2SMMLSR:
6506	case ARM::t2USADA8: {
6507	// op: Rd
6508	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6509	op &= UINT64_C(`15`);
6510	op <<= `8`;
6511	Value \|= op;
6512	// op: Rn
6513	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
6514	op &= UINT64_C(`15`);
6515	op <<= `16`;
6516	Value \|= op;
6517	// op: Rm
6518	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
6519	op &= UINT64_C(`15`);
6520	Value \|= op;
6521	// op: Ra
6522	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
6523	op &= UINT64_C(`15`);
6524	op <<= `12`;
6525	Value \|= op;
6526	break;
6527	}
6528	case ARM::t2SXTAB:
6529	case ARM::t2SXTAB16:
6530	case ARM::t2SXTAH:
6531	case ARM::t2UXTAB:
6532	case ARM::t2UXTAB16:
6533	case ARM::t2UXTAH: {
6534	// op: Rd
6535	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6536	op &= UINT64_C(`15`);
6537	op <<= `8`;
6538	Value \|= op;
6539	// op: Rn
6540	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
6541	op &= UINT64_C(`15`);
6542	op <<= `16`;
6543	Value \|= op;
6544	// op: Rm
6545	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
6546	op &= UINT64_C(`15`);
6547	Value \|= op;
6548	// op: rot
6549	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
6550	op &= UINT64_C(`3`);
6551	op <<= `4`;
6552	Value \|= op;
6553	break;
6554	}
6555	case ARM::t2PKHBT:
6556	case ARM::t2PKHTB: {
6557	// op: Rd
6558	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6559	op &= UINT64_C(`15`);
6560	op <<= `8`;
6561	Value \|= op;
6562	// op: Rn
6563	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
6564	op &= UINT64_C(`15`);
6565	op <<= `16`;
6566	Value \|= op;
6567	// op: Rm
6568	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
6569	op &= UINT64_C(`15`);
6570	Value \|= op;
6571	// op: sh
6572	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
6573	Value \|= (op & UINT64_C(`28`)) << `10`;
6574	Value \|= (op & UINT64_C(`3`)) << `6`;
6575	break;
6576	}
6577	case ARM::t2ADDri12:
6578	case ARM::t2SUBri12: {
6579	// op: Rd
6580	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6581	op &= UINT64_C(`15`);
6582	op <<= `8`;
6583	Value \|= op;
6584	// op: Rn
6585	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
6586	op &= UINT64_C(`15`);
6587	op <<= `16`;
6588	Value \|= op;
6589	// op: imm
6590	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
6591	Value \|= (op & UINT64_C(`2048`)) << `15`;
6592	Value \|= (op & UINT64_C(`1792`)) << `4`;
6593	Value \|= (op & UINT64_C(`255`));
6594	break;
6595	}
6596	case ARM::t2QADD:
6597	case ARM::t2QDADD:
6598	case ARM::t2QDSUB:
6599	case ARM::t2QSUB: {
6600	// op: Rd
6601	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6602	op &= UINT64_C(`15`);
6603	op <<= `8`;
6604	Value \|= op;
6605	// op: Rn
6606	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
6607	op &= UINT64_C(`15`);
6608	op <<= `16`;
6609	Value \|= op;
6610	// op: Rm
6611	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
6612	op &= UINT64_C(`15`);
6613	Value \|= op;
6614	break;
6615	}
6616	case ARM::t2BFI: {
6617	// op: Rd
6618	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6619	op &= UINT64_C(`15`);
6620	op <<= `8`;
6621	Value \|= op;
6622	// op: Rn
6623	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
6624	op &= UINT64_C(`15`);
6625	op <<= `16`;
6626	Value \|= op;
6627	// op: imm
6628	op = getBitfieldInvertedMaskOpValue(MI, `3`, Fixups, STI);
6629	Value \|= (op & UINT64_C(`28`)) << `10`;
6630	Value \|= (op & UINT64_C(`3`)) << `6`;
6631	Value \|= (op & UINT64_C(`992`)) >> `5`;
6632	break;
6633	}
6634	case ARM::t2SSAT16:
6635	case ARM::t2USAT16: {
6636	// op: Rd
6637	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6638	op &= UINT64_C(`15`);
6639	op <<= `8`;
6640	Value \|= op;
6641	// op: Rn
6642	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
6643	op &= UINT64_C(`15`);
6644	op <<= `16`;
6645	Value \|= op;
6646	// op: sat_imm
6647	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
6648	op &= UINT64_C(`15`);
6649	Value \|= op;
6650	break;
6651	}
6652	case ARM::t2SSAT:
6653	case ARM::t2USAT: {
6654	// op: Rd
6655	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6656	op &= UINT64_C(`15`);
6657	op <<= `8`;
6658	Value \|= op;
6659	// op: Rn
6660	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
6661	op &= UINT64_C(`15`);
6662	op <<= `16`;
6663	Value \|= op;
6664	// op: sat_imm
6665	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
6666	op &= UINT64_C(`31`);
6667	Value \|= op;
6668	// op: sh
6669	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
6670	Value \|= (op & UINT64_C(`32`)) << `16`;
6671	Value \|= (op & UINT64_C(`28`)) << `10`;
6672	Value \|= (op & UINT64_C(`3`)) << `6`;
6673	break;
6674	}
6675	case ARM::t2STREX: {
6676	// op: Rd
6677	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6678	op &= UINT64_C(`15`);
6679	op <<= `8`;
6680	Value \|= op;
6681	// op: Rt
6682	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
6683	op &= UINT64_C(`15`);
6684	op <<= `12`;
6685	Value \|= op;
6686	// op: addr
6687	op = getT2AddrModeImm0_1020s4OpValue(MI, `2`, Fixups, STI);
6688	Value \|= (op & UINT64_C(`3840`)) << `8`;
6689	Value \|= (op & UINT64_C(`255`));
6690	break;
6691	}
6692	case ARM::t2MRS_M: {
6693	// op: Rd
6694	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6695	op &= UINT64_C(`15`);
6696	op <<= `8`;
6697	Value \|= op;
6698	// op: SYSm
6699	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
6700	op &= UINT64_C(`255`);
6701	Value \|= op;
6702	break;
6703	}
6704	case ARM::t2ADR: {
6705	// op: Rd
6706	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6707	op &= UINT64_C(`15`);
6708	op <<= `8`;
6709	Value \|= op;
6710	// op: addr
6711	op = getT2AdrLabelOpValue(MI, `1`, Fixups, STI);
6712	Value \|= (op & UINT64_C(`2048`)) << `15`;
6713	Value \|= (op & UINT64_C(`4096`)) << `11`;
6714	Value \|= (op & UINT64_C(`4096`)) << `9`;
6715	Value \|= (op & UINT64_C(`1792`)) << `4`;
6716	Value \|= (op & UINT64_C(`255`));
6717	break;
6718	}
6719	case ARM::t2BFC: {
6720	// op: Rd
6721	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6722	op &= UINT64_C(`15`);
6723	op <<= `8`;
6724	Value \|= op;
6725	// op: imm
6726	op = getBitfieldInvertedMaskOpValue(MI, `2`, Fixups, STI);
6727	Value \|= (op & UINT64_C(`28`)) << `10`;
6728	Value \|= (op & UINT64_C(`3`)) << `6`;
6729	Value \|= (op & UINT64_C(`992`)) >> `5`;
6730	break;
6731	}
6732	case ARM::t2MOVi16: {
6733	// op: Rd
6734	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6735	op &= UINT64_C(`15`);
6736	op <<= `8`;
6737	Value \|= op;
6738	// op: imm
6739	op = getHiLo16ImmOpValue(MI, `1`, Fixups, STI);
6740	Value \|= (op & UINT64_C(`2048`)) << `15`;
6741	Value \|= (op & UINT64_C(`61440`)) << `4`;
6742	Value \|= (op & UINT64_C(`1792`)) << `4`;
6743	Value \|= (op & UINT64_C(`255`));
6744	break;
6745	}
6746	case ARM::t2MOVTi16: {
6747	// op: Rd
6748	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6749	op &= UINT64_C(`15`);
6750	op <<= `8`;
6751	Value \|= op;
6752	// op: imm
6753	op = getHiLo16ImmOpValue(MI, `2`, Fixups, STI);
6754	Value \|= (op & UINT64_C(`2048`)) << `15`;
6755	Value \|= (op & UINT64_C(`61440`)) << `4`;
6756	Value \|= (op & UINT64_C(`1792`)) << `4`;
6757	Value \|= (op & UINT64_C(`255`));
6758	break;
6759	}
6760	case ARM::t2SBFX:
6761	case ARM::t2UBFX: {
6762	// op: Rd
6763	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6764	op &= UINT64_C(`15`);
6765	op <<= `8`;
6766	Value \|= op;
6767	// op: msb
6768	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
6769	op &= UINT64_C(`31`);
6770	Value \|= op;
6771	// op: lsb
6772	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
6773	Value \|= (op & UINT64_C(`28`)) << `10`;
6774	Value \|= (op & UINT64_C(`3`)) << `6`;
6775	// op: Rn
6776	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
6777	op &= UINT64_C(`15`);
6778	op <<= `16`;
6779	Value \|= op;
6780	break;
6781	}
6782	case ARM::tMOVSr: {
6783	// op: Rd
6784	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6785	op &= UINT64_C(`7`);
6786	Value \|= op;
6787	// op: Rm
6788	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
6789	op &= UINT64_C(`7`);
6790	op <<= `3`;
6791	Value \|= op;
6792	break;
6793	}
6794	case ARM::tADDi3:
6795	case ARM::tSUBi3: {
6796	// op: Rd
6797	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6798	op &= UINT64_C(`7`);
6799	Value \|= op;
6800	// op: Rm
6801	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
6802	op &= UINT64_C(`7`);
6803	op <<= `3`;
6804	Value \|= op;
6805	// op: imm3
6806	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
6807	op &= UINT64_C(`7`);
6808	op <<= `6`;
6809	Value \|= op;
6810	break;
6811	}
6812	case ARM::tASRri:
6813	case ARM::tLSLri:
6814	case ARM::tLSRri: {
6815	// op: Rd
6816	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6817	op &= UINT64_C(`7`);
6818	Value \|= op;
6819	// op: Rm
6820	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
6821	op &= UINT64_C(`7`);
6822	op <<= `3`;
6823	Value \|= op;
6824	// op: imm5
6825	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
6826	op &= UINT64_C(`31`);
6827	op <<= `6`;
6828	Value \|= op;
6829	break;
6830	}
6831	case ARM::tMUL:
6832	case ARM::tMVN:
6833	case ARM::tRSB: {
6834	// op: Rd
6835	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6836	op &= UINT64_C(`7`);
6837	Value \|= op;
6838	// op: Rn
6839	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
6840	op &= UINT64_C(`7`);
6841	op <<= `3`;
6842	Value \|= op;
6843	break;
6844	}
6845	case ARM::tADR: {
6846	// op: Rd
6847	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6848	op &= UINT64_C(`7`);
6849	op <<= `8`;
6850	Value \|= op;
6851	// op: addr
6852	op = getThumbAdrLabelOpValue(MI, `1`, Fixups, STI);
6853	op &= UINT64_C(`255`);
6854	Value \|= op;
6855	break;
6856	}
6857	case ARM::tMOVi8: {
6858	// op: Rd
6859	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6860	op &= UINT64_C(`7`);
6861	op <<= `8`;
6862	Value \|= op;
6863	// op: imm8
6864	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
6865	op &= UINT64_C(`255`);
6866	Value \|= op;
6867	break;
6868	}
6869	case ARM::t2SMLALD:
6870	case ARM::t2SMLALDX:
6871	case ARM::t2SMLSLD:
6872	case ARM::t2SMLSLDX: {
6873	// op: Rd
6874	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
6875	op &= UINT64_C(`15`);
6876	op <<= `8`;
6877	Value \|= op;
6878	// op: Rn
6879	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
6880	op &= UINT64_C(`15`);
6881	op <<= `16`;
6882	Value \|= op;
6883	// op: Rm
6884	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
6885	op &= UINT64_C(`15`);
6886	Value \|= op;
6887	// op: Ra
6888	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6889	op &= UINT64_C(`15`);
6890	op <<= `12`;
6891	Value \|= op;
6892	break;
6893	}
6894	case ARM::t2SMLAL:
6895	case ARM::t2SMLALBB:
6896	case ARM::t2SMLALBT:
6897	case ARM::t2SMLALTB:
6898	case ARM::t2SMLALTT:
6899	case ARM::t2SMULL:
6900	case ARM::t2UMAAL:
6901	case ARM::t2UMLAL:
6902	case ARM::t2UMULL: {
6903	// op: RdLo
6904	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6905	op &= UINT64_C(`15`);
6906	op <<= `12`;
6907	Value \|= op;
6908	// op: RdHi
6909	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
6910	op &= UINT64_C(`15`);
6911	op <<= `8`;
6912	Value \|= op;
6913	// op: Rn
6914	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
6915	op &= UINT64_C(`15`);
6916	op <<= `16`;
6917	Value \|= op;
6918	// op: Rm
6919	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
6920	op &= UINT64_C(`15`);
6921	Value \|= op;
6922	break;
6923	}
6924	case ARM::MVE_VMLADAVs16:
6925	case ARM::MVE_VMLADAVs32:
6926	case ARM::MVE_VMLADAVs8:
6927	case ARM::MVE_VMLADAVu16:
6928	case ARM::MVE_VMLADAVu32:
6929	case ARM::MVE_VMLADAVu8:
6930	case ARM::MVE_VMLADAVxs16:
6931	case ARM::MVE_VMLADAVxs32:
6932	case ARM::MVE_VMLADAVxs8:
6933	case ARM::MVE_VMLSDAVs16:
6934	case ARM::MVE_VMLSDAVs32:
6935	case ARM::MVE_VMLSDAVs8:
6936	case ARM::MVE_VMLSDAVxs16:
6937	case ARM::MVE_VMLSDAVxs32:
6938	case ARM::MVE_VMLSDAVxs8: {
6939	// op: RdaDest
6940	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6941	op &= UINT64_C(`14`);
6942	op <<= `12`;
6943	Value \|= op;
6944	// op: Qm
6945	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
6946	op &= UINT64_C(`7`);
6947	op <<= `1`;
6948	Value \|= op;
6949	// op: Qn
6950	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
6951	op &= UINT64_C(`7`);
6952	op <<= `17`;
6953	Value \|= op;
6954	break;
6955	}
6956	case ARM::MVE_VMLADAVas16:
6957	case ARM::MVE_VMLADAVas32:
6958	case ARM::MVE_VMLADAVas8:
6959	case ARM::MVE_VMLADAVau16:
6960	case ARM::MVE_VMLADAVau32:
6961	case ARM::MVE_VMLADAVau8:
6962	case ARM::MVE_VMLADAVaxs16:
6963	case ARM::MVE_VMLADAVaxs32:
6964	case ARM::MVE_VMLADAVaxs8:
6965	case ARM::MVE_VMLSDAVas16:
6966	case ARM::MVE_VMLSDAVas32:
6967	case ARM::MVE_VMLSDAVas8:
6968	case ARM::MVE_VMLSDAVaxs16:
6969	case ARM::MVE_VMLSDAVaxs32:
6970	case ARM::MVE_VMLSDAVaxs8: {
6971	// op: RdaDest
6972	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6973	op &= UINT64_C(`14`);
6974	op <<= `12`;
6975	Value \|= op;
6976	// op: Qm
6977	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
6978	op &= UINT64_C(`7`);
6979	op <<= `1`;
6980	Value \|= op;
6981	// op: Qn
6982	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
6983	op &= UINT64_C(`7`);
6984	op <<= `17`;
6985	Value \|= op;
6986	break;
6987	}
6988	case ARM::MVE_SQRSHR:
6989	case ARM::MVE_UQRSHL: {
6990	// op: RdaDest
6991	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
6992	op &= UINT64_C(`15`);
6993	op <<= `16`;
6994	Value \|= op;
6995	// op: Rm
6996	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
6997	op &= UINT64_C(`15`);
6998	op <<= `12`;
6999	Value \|= op;
7000	break;
7001	}
7002	case ARM::MVE_SQSHL:
7003	case ARM::MVE_SRSHR:
7004	case ARM::MVE_UQSHL:
7005	case ARM::MVE_URSHR: {
7006	// op: RdaDest
7007	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7008	op &= UINT64_C(`15`);
7009	op <<= `16`;
7010	Value \|= op;
7011	// op: imm
7012	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
7013	Value \|= (op & UINT64_C(`28`)) << `10`;
7014	Value \|= (op & UINT64_C(`3`)) << `6`;
7015	break;
7016	}
7017	case ARM::MVE_ASRLr:
7018	case ARM::MVE_LSLLr: {
7019	// op: RdaLo
7020	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7021	op &= UINT64_C(`14`);
7022	op <<= `16`;
7023	Value \|= op;
7024	// op: RdaHi
7025	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
7026	op &= UINT64_C(`14`);
7027	op <<= `8`;
7028	Value \|= op;
7029	// op: Rm
7030	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
7031	op &= UINT64_C(`15`);
7032	op <<= `12`;
7033	Value \|= op;
7034	break;
7035	}
7036	case ARM::MVE_SQRSHRL:
7037	case ARM::MVE_UQRSHLL: {
7038	// op: RdaLo
7039	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7040	op &= UINT64_C(`14`);
7041	op <<= `16`;
7042	Value \|= op;
7043	// op: RdaHi
7044	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
7045	op &= UINT64_C(`14`);
7046	op <<= `8`;
7047	Value \|= op;
7048	// op: Rm
7049	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
7050	op &= UINT64_C(`15`);
7051	op <<= `12`;
7052	Value \|= op;
7053	// op: sat
7054	op = getMachineOpValue(MI, MI.getOperand(`5`), Fixups, STI);
7055	op &= UINT64_C(`1`);
7056	op <<= `7`;
7057	Value \|= op;
7058	break;
7059	}
7060	case ARM::MVE_ASRLi:
7061	case ARM::MVE_LSLLi:
7062	case ARM::MVE_LSRL:
7063	case ARM::MVE_SQSHLL:
7064	case ARM::MVE_SRSHRL:
7065	case ARM::MVE_UQSHLL:
7066	case ARM::MVE_URSHRL: {
7067	// op: RdaLo
7068	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7069	op &= UINT64_C(`14`);
7070	op <<= `16`;
7071	Value \|= op;
7072	// op: RdaHi
7073	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
7074	op &= UINT64_C(`14`);
7075	op <<= `8`;
7076	Value \|= op;
7077	// op: imm
7078	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
7079	Value \|= (op & UINT64_C(`28`)) << `10`;
7080	Value \|= (op & UINT64_C(`3`)) << `6`;
7081	break;
7082	}
7083	case ARM::MVE_VMLALDAVs16:
7084	case ARM::MVE_VMLALDAVs32:
7085	case ARM::MVE_VMLALDAVu16:
7086	case ARM::MVE_VMLALDAVu32:
7087	case ARM::MVE_VMLALDAVxs16:
7088	case ARM::MVE_VMLALDAVxs32:
7089	case ARM::MVE_VMLSLDAVs16:
7090	case ARM::MVE_VMLSLDAVs32:
7091	case ARM::MVE_VMLSLDAVxs16:
7092	case ARM::MVE_VMLSLDAVxs32:
7093	case ARM::MVE_VRMLALDAVHs32:
7094	case ARM::MVE_VRMLALDAVHu32:
7095	case ARM::MVE_VRMLALDAVHxs32:
7096	case ARM::MVE_VRMLSLDAVHs32:
7097	case ARM::MVE_VRMLSLDAVHxs32: {
7098	// op: RdaLoDest
7099	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7100	op &= UINT64_C(`14`);
7101	op <<= `12`;
7102	Value \|= op;
7103	// op: RdaHiDest
7104	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
7105	op &= UINT64_C(`14`);
7106	op <<= `19`;
7107	Value \|= op;
7108	// op: Qm
7109	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
7110	op &= UINT64_C(`7`);
7111	op <<= `1`;
7112	Value \|= op;
7113	// op: Qn
7114	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
7115	op &= UINT64_C(`7`);
7116	op <<= `17`;
7117	Value \|= op;
7118	break;
7119	}
7120	case ARM::MVE_VMLALDAVas16:
7121	case ARM::MVE_VMLALDAVas32:
7122	case ARM::MVE_VMLALDAVau16:
7123	case ARM::MVE_VMLALDAVau32:
7124	case ARM::MVE_VMLALDAVaxs16:
7125	case ARM::MVE_VMLALDAVaxs32:
7126	case ARM::MVE_VMLSLDAVas16:
7127	case ARM::MVE_VMLSLDAVas32:
7128	case ARM::MVE_VMLSLDAVaxs16:
7129	case ARM::MVE_VMLSLDAVaxs32:
7130	case ARM::MVE_VRMLALDAVHas32:
7131	case ARM::MVE_VRMLALDAVHau32:
7132	case ARM::MVE_VRMLALDAVHaxs32:
7133	case ARM::MVE_VRMLSLDAVHas32:
7134	case ARM::MVE_VRMLSLDAVHaxs32: {
7135	// op: RdaLoDest
7136	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7137	op &= UINT64_C(`14`);
7138	op <<= `12`;
7139	Value \|= op;
7140	// op: RdaHiDest
7141	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
7142	op &= UINT64_C(`14`);
7143	op <<= `19`;
7144	Value \|= op;
7145	// op: Qm
7146	op = getMachineOpValue(MI, MI.getOperand(`5`), Fixups, STI);
7147	op &= UINT64_C(`7`);
7148	op <<= `1`;
7149	Value \|= op;
7150	// op: Qn
7151	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
7152	op &= UINT64_C(`7`);
7153	op <<= `17`;
7154	Value \|= op;
7155	break;
7156	}
7157	case ARM::tADDrSP: {
7158	// op: Rdn
7159	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7160	Value \|= (op & UINT64_C(`8`)) << `4`;
7161	Value \|= (op & UINT64_C(`7`));
7162	break;
7163	}
7164	case ARM::tADDhirr: {
7165	// op: Rdn
7166	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7167	Value \|= (op & UINT64_C(`8`)) << `4`;
7168	Value \|= (op & UINT64_C(`7`));
7169	// op: Rm
7170	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
7171	op &= UINT64_C(`15`);
7172	op <<= `3`;
7173	Value \|= op;
7174	break;
7175	}
7176	case ARM::tADC:
7177	case ARM::tAND:
7178	case ARM::tASRrr:
7179	case ARM::tBIC:
7180	case ARM::tEOR:
7181	case ARM::tLSLrr:
7182	case ARM::tLSRrr:
7183	case ARM::tORR:
7184	case ARM::tROR:
7185	case ARM::tSBC: {
7186	// op: Rdn
7187	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7188	op &= UINT64_C(`7`);
7189	Value \|= op;
7190	// op: Rm
7191	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
7192	op &= UINT64_C(`7`);
7193	op <<= `3`;
7194	Value \|= op;
7195	break;
7196	}
7197	case ARM::tADDi8:
7198	case ARM::tSUBi8: {
7199	// op: Rdn
7200	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7201	op &= UINT64_C(`7`);
7202	op <<= `8`;
7203	Value \|= op;
7204	// op: imm8
7205	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
7206	op &= UINT64_C(`255`);
7207	Value \|= op;
7208	break;
7209	}
7210	case ARM::tBX:
7211	case ARM::tBXNS: {
7212	// op: Rm
7213	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7214	op &= UINT64_C(`15`);
7215	op <<= `3`;
7216	Value \|= op;
7217	break;
7218	}
7219	case ARM::tCMPhir: {
7220	// op: Rm
7221	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
7222	op &= UINT64_C(`15`);
7223	op <<= `3`;
7224	Value \|= op;
7225	// op: Rn
7226	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7227	Value \|= (op & UINT64_C(`8`)) << `4`;
7228	Value \|= (op & UINT64_C(`7`));
7229	break;
7230	}
7231	case ARM::tREV:
7232	case ARM::tREV16:
7233	case ARM::tREVSH:
7234	case ARM::tSXTB:
7235	case ARM::tSXTH:
7236	case ARM::tUXTB:
7237	case ARM::tUXTH: {
7238	// op: Rm
7239	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
7240	op &= UINT64_C(`7`);
7241	op <<= `3`;
7242	Value \|= op;
7243	// op: Rd
7244	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7245	op &= UINT64_C(`7`);
7246	Value \|= op;
7247	break;
7248	}
7249	case ARM::tCMNz:
7250	case ARM::tCMPr:
7251	case ARM::tTST: {
7252	// op: Rm
7253	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
7254	op &= UINT64_C(`7`);
7255	op <<= `3`;
7256	Value \|= op;
7257	// op: Rn
7258	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7259	op &= UINT64_C(`7`);
7260	Value \|= op;
7261	break;
7262	}
7263	case ARM::tADDspr: {
7264	// op: Rm
7265	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
7266	op &= UINT64_C(`15`);
7267	op <<= `3`;
7268	Value \|= op;
7269	break;
7270	}
7271	case ARM::tADDrr:
7272	case ARM::tSUBrr: {
7273	// op: Rm
7274	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
7275	op &= UINT64_C(`7`);
7276	op <<= `6`;
7277	Value \|= op;
7278	// op: Rn
7279	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
7280	op &= UINT64_C(`7`);
7281	op <<= `3`;
7282	Value \|= op;
7283	// op: Rd
7284	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7285	op &= UINT64_C(`7`);
7286	Value \|= op;
7287	break;
7288	}
7289	case ARM::RFEDA:
7290	case ARM::RFEDA_UPD:
7291	case ARM::RFEDB:
7292	case ARM::RFEDB_UPD:
7293	case ARM::RFEIA:
7294	case ARM::RFEIA_UPD:
7295	case ARM::RFEIB:
7296	case ARM::RFEIB_UPD:
7297	case ARM::t2RFEDB:
7298	case ARM::t2RFEDBW:
7299	case ARM::t2RFEIA:
7300	case ARM::t2RFEIAW: {
7301	// op: Rn
7302	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7303	op &= UINT64_C(`15`);
7304	op <<= `16`;
7305	Value \|= op;
7306	break;
7307	}
7308	case ARM::t2CMNzrr:
7309	case ARM::t2CMPrr:
7310	case ARM::t2TBB:
7311	case ARM::t2TBH:
7312	case ARM::t2TEQrr:
7313	case ARM::t2TSTrr: {
7314	// op: Rn
7315	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7316	op &= UINT64_C(`15`);
7317	op <<= `16`;
7318	Value \|= op;
7319	// op: Rm
7320	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
7321	op &= UINT64_C(`15`);
7322	Value \|= op;
7323	break;
7324	}
7325	case ARM::t2CMNzrs:
7326	case ARM::t2CMPrs:
7327	case ARM::t2TEQrs:
7328	case ARM::t2TSTrs: {
7329	// op: Rn
7330	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7331	op &= UINT64_C(`15`);
7332	op <<= `16`;
7333	Value \|= op;
7334	// op: ShiftedRm
7335	op = getT2SORegOpValue(MI, `1`, Fixups, STI);
7336	Value \|= (op & UINT64_C(`3584`)) << `3`;
7337	Value \|= (op & UINT64_C(`480`)) >> `1`;
7338	Value \|= (op & UINT64_C(`15`));
7339	break;
7340	}
7341	case ARM::t2CMNri:
7342	case ARM::t2CMPri:
7343	case ARM::t2TEQri:
7344	case ARM::t2TSTri: {
7345	// op: Rn
7346	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7347	op &= UINT64_C(`15`);
7348	op <<= `16`;
7349	Value \|= op;
7350	// op: imm
7351	op = getT2SOImmOpValue(MI, `1`, Fixups, STI);
7352	Value \|= (op & UINT64_C(`2048`)) << `15`;
7353	Value \|= (op & UINT64_C(`1792`)) << `4`;
7354	Value \|= (op & UINT64_C(`255`));
7355	break;
7356	}
7357	case ARM::t2STMDB:
7358	case ARM::t2STMIA: {
7359	// op: Rn
7360	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7361	op &= UINT64_C(`15`);
7362	op <<= `16`;
7363	Value \|= op;
7364	// op: regs
7365	op = getRegisterListOpValue(MI, `3`, Fixups, STI);
7366	Value \|= (op & UINT64_C(`16384`));
7367	Value \|= (op & UINT64_C(`8191`));
7368	break;
7369	}
7370	case ARM::t2LDMDB:
7371	case ARM::t2LDMIA: {
7372	// op: Rn
7373	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7374	op &= UINT64_C(`15`);
7375	op <<= `16`;
7376	Value \|= op;
7377	// op: regs
7378	op = getRegisterListOpValue(MI, `3`, Fixups, STI);
7379	op &= UINT64_C(`65535`);
7380	Value \|= op;
7381	break;
7382	}
7383	case ARM::tCMPi8: {
7384	// op: Rn
7385	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7386	op &= UINT64_C(`7`);
7387	op <<= `8`;
7388	Value \|= op;
7389	// op: imm8
7390	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
7391	op &= UINT64_C(`255`);
7392	Value \|= op;
7393	break;
7394	}
7395	case ARM::tLDMIA: {
7396	// op: Rn
7397	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7398	op &= UINT64_C(`7`);
7399	op <<= `8`;
7400	Value \|= op;
7401	// op: regs
7402	op = getRegisterListOpValue(MI, `3`, Fixups, STI);
7403	op &= UINT64_C(`255`);
7404	Value \|= op;
7405	break;
7406	}
7407	case ARM::MVE_DLSTP_16:
7408	case ARM::MVE_DLSTP_32:
7409	case ARM::MVE_DLSTP_64:
7410	case ARM::MVE_DLSTP_8:
7411	case ARM::MVE_VCTP16:
7412	case ARM::MVE_VCTP32:
7413	case ARM::MVE_VCTP64:
7414	case ARM::MVE_VCTP8:
7415	case ARM::t2DLS: {
7416	// op: Rn
7417	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
7418	op &= UINT64_C(`15`);
7419	op <<= `16`;
7420	Value \|= op;
7421	break;
7422	}
7423	case ARM::t2TT:
7424	case ARM::t2TTA:
7425	case ARM::t2TTAT:
7426	case ARM::t2TTT: {
7427	// op: Rn
7428	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
7429	op &= UINT64_C(`15`);
7430	op <<= `16`;
7431	Value \|= op;
7432	// op: Rt
7433	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7434	op &= UINT64_C(`15`);
7435	op <<= `8`;
7436	Value \|= op;
7437	break;
7438	}
7439	case ARM::MVE_WLSTP_16:
7440	case ARM::MVE_WLSTP_32:
7441	case ARM::MVE_WLSTP_64:
7442	case ARM::MVE_WLSTP_8:
7443	case ARM::t2WLS: {
7444	// op: Rn
7445	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
7446	op &= UINT64_C(`15`);
7447	op <<= `16`;
7448	Value \|= op;
7449	// op: label
7450	op = getBFTargetOpValue<false, ARM::fixup_wls>(MI, `2`, Fixups, STI);
7451	Value \|= (op & UINT64_C(`1`)) << `11`;
7452	Value \|= (op & UINT64_C(`2046`));
7453	break;
7454	}
7455	case ARM::t2STMDB_UPD:
7456	case ARM::t2STMIA_UPD: {
7457	// op: Rn
7458	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
7459	op &= UINT64_C(`15`);
7460	op <<= `16`;
7461	Value \|= op;
7462	// op: regs
7463	op = getRegisterListOpValue(MI, `4`, Fixups, STI);
7464	Value \|= (op & UINT64_C(`16384`));
7465	Value \|= (op & UINT64_C(`8191`));
7466	break;
7467	}
7468	case ARM::t2LDMDB_UPD:
7469	case ARM::t2LDMIA_UPD: {
7470	// op: Rn
7471	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
7472	op &= UINT64_C(`15`);
7473	op <<= `16`;
7474	Value \|= op;
7475	// op: regs
7476	op = getRegisterListOpValue(MI, `4`, Fixups, STI);
7477	op &= UINT64_C(`65535`);
7478	Value \|= op;
7479	break;
7480	}
7481	case ARM::tSTMIA_UPD: {
7482	// op: Rn
7483	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
7484	op &= UINT64_C(`7`);
7485	op <<= `8`;
7486	Value \|= op;
7487	// op: regs
7488	op = getRegisterListOpValue(MI, `4`, Fixups, STI);
7489	op &= UINT64_C(`255`);
7490	Value \|= op;
7491	break;
7492	}
7493	case ARM::MVE_VMOV_rr_q: {
7494	// op: Rt
7495	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7496	op &= UINT64_C(`15`);
7497	Value \|= op;
7498	// op: Rt2
7499	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
7500	op &= UINT64_C(`15`);
7501	op <<= `16`;
7502	Value \|= op;
7503	// op: Qd
7504	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
7505	Value \|= (op & UINT64_C(`8`)) << `19`;
7506	Value \|= (op & UINT64_C(`7`)) << `13`;
7507	// op: idx2
7508	op = getMVEPairVectorIndexOpValue<`0`>(MI, `4`, Fixups, STI);
7509	op &= UINT64_C(`1`);
7510	op <<= `4`;
7511	Value \|= op;
7512	break;
7513	}
7514	case ARM::t2LDRB_POST:
7515	case ARM::t2LDRH_POST:
7516	case ARM::t2LDRSB_POST:
7517	case ARM::t2LDRSH_POST:
7518	case ARM::t2LDR_POST: {
7519	// op: Rt
7520	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7521	op &= UINT64_C(`15`);
7522	op <<= `12`;
7523	Value \|= op;
7524	// op: Rn
7525	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
7526	op &= UINT64_C(`15`);
7527	op <<= `16`;
7528	Value \|= op;
7529	// op: offset
7530	op = getT2AddrModeImm8OffsetOpValue(MI, `3`, Fixups, STI);
7531	Value \|= (op & UINT64_C(`256`)) << `1`;
7532	Value \|= (op & UINT64_C(`255`));
7533	break;
7534	}
7535	case ARM::MRRC2:
7536	case ARM::t2MRRC:
7537	case ARM::t2MRRC2: {
7538	// op: Rt
7539	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7540	op &= UINT64_C(`15`);
7541	op <<= `12`;
7542	Value \|= op;
7543	// op: Rt2
7544	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
7545	op &= UINT64_C(`15`);
7546	op <<= `16`;
7547	Value \|= op;
7548	// op: cop
7549	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
7550	op &= UINT64_C(`15`);
7551	op <<= `8`;
7552	Value \|= op;
7553	// op: opc1
7554	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
7555	op &= UINT64_C(`15`);
7556	op <<= `4`;
7557	Value \|= op;
7558	// op: CRm
7559	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
7560	op &= UINT64_C(`15`);
7561	Value \|= op;
7562	break;
7563	}
7564	case ARM::t2LDRD_POST: {
7565	// op: Rt
7566	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7567	op &= UINT64_C(`15`);
7568	op <<= `12`;
7569	Value \|= op;
7570	// op: Rt2
7571	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
7572	op &= UINT64_C(`15`);
7573	op <<= `8`;
7574	Value \|= op;
7575	// op: addr
7576	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
7577	op &= UINT64_C(`15`);
7578	op <<= `16`;
7579	Value \|= op;
7580	// op: imm
7581	op = getT2ScaledImmOpValue<`8`,`2`>(MI, `4`, Fixups, STI);
7582	Value \|= (op & UINT64_C(`256`)) << `15`;
7583	Value \|= (op & UINT64_C(`255`));
7584	break;
7585	}
7586	case ARM::t2LDRDi8:
7587	case ARM::t2STRDi8: {
7588	// op: Rt
7589	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7590	op &= UINT64_C(`15`);
7591	op <<= `12`;
7592	Value \|= op;
7593	// op: Rt2
7594	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
7595	op &= UINT64_C(`15`);
7596	op <<= `8`;
7597	Value \|= op;
7598	// op: addr
7599	op = getT2AddrModeImm8s4OpValue(MI, `2`, Fixups, STI);
7600	Value \|= (op & UINT64_C(`256`)) << `15`;
7601	Value \|= (op & UINT64_C(`7680`)) << `7`;
7602	Value \|= (op & UINT64_C(`255`));
7603	break;
7604	}
7605	case ARM::t2LDRD_PRE: {
7606	// op: Rt
7607	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7608	op &= UINT64_C(`15`);
7609	op <<= `12`;
7610	Value \|= op;
7611	// op: Rt2
7612	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
7613	op &= UINT64_C(`15`);
7614	op <<= `8`;
7615	Value \|= op;
7616	// op: addr
7617	op = getT2AddrModeImm8s4OpValue(MI, `3`, Fixups, STI);
7618	Value \|= (op & UINT64_C(`256`)) << `15`;
7619	Value \|= (op & UINT64_C(`7680`)) << `7`;
7620	Value \|= (op & UINT64_C(`255`));
7621	break;
7622	}
7623	case ARM::t2LDRBi12:
7624	case ARM::t2LDRHi12:
7625	case ARM::t2LDRSBi12:
7626	case ARM::t2LDRSHi12:
7627	case ARM::t2LDRi12:
7628	case ARM::t2STRBi12:
7629	case ARM::t2STRHi12:
7630	case ARM::t2STRi12: {
7631	// op: Rt
7632	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7633	op &= UINT64_C(`15`);
7634	op <<= `12`;
7635	Value \|= op;
7636	// op: addr
7637	op = getAddrModeImm12OpValue(MI, `1`, Fixups, STI);
7638	Value \|= (op & UINT64_C(`122880`)) << `3`;
7639	Value \|= (op & UINT64_C(`4095`));
7640	break;
7641	}
7642	case ARM::t2LDRBpci:
7643	case ARM::t2LDRHpci:
7644	case ARM::t2LDRSBpci:
7645	case ARM::t2LDRSHpci:
7646	case ARM::t2LDRpci: {
7647	// op: Rt
7648	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7649	op &= UINT64_C(`15`);
7650	op <<= `12`;
7651	Value \|= op;
7652	// op: addr
7653	op = getAddrModeImm12OpValue(MI, `1`, Fixups, STI);
7654	Value \|= (op & UINT64_C(`4096`)) << `11`;
7655	Value \|= (op & UINT64_C(`4095`));
7656	break;
7657	}
7658	case ARM::t2LDA:
7659	case ARM::t2LDAB:
7660	case ARM::t2LDAEX:
7661	case ARM::t2LDAH:
7662	case ARM::t2STL:
7663	case ARM::t2STLB:
7664	case ARM::t2STLH: {
7665	// op: Rt
7666	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7667	op &= UINT64_C(`15`);
7668	op <<= `12`;
7669	Value \|= op;
7670	// op: addr
7671	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
7672	op &= UINT64_C(`15`);
7673	op <<= `16`;
7674	Value \|= op;
7675	break;
7676	}
7677	case ARM::t2LDREX: {
7678	// op: Rt
7679	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7680	op &= UINT64_C(`15`);
7681	op <<= `12`;
7682	Value \|= op;
7683	// op: addr
7684	op = getT2AddrModeImm0_1020s4OpValue(MI, `1`, Fixups, STI);
7685	Value \|= (op & UINT64_C(`3840`)) << `8`;
7686	Value \|= (op & UINT64_C(`255`));
7687	break;
7688	}
7689	case ARM::t2LDRBT:
7690	case ARM::t2LDRHT:
7691	case ARM::t2LDRSBT:
7692	case ARM::t2LDRSHT:
7693	case ARM::t2LDRT:
7694	case ARM::t2STRBT:
7695	case ARM::t2STRHT:
7696	case ARM::t2STRT: {
7697	// op: Rt
7698	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7699	op &= UINT64_C(`15`);
7700	op <<= `12`;
7701	Value \|= op;
7702	// op: addr
7703	op = getT2AddrModeImmOpValue<`8`,`0`>(MI, `1`, Fixups, STI);
7704	Value \|= (op & UINT64_C(`7680`)) << `7`;
7705	Value \|= (op & UINT64_C(`255`));
7706	break;
7707	}
7708	case ARM::t2LDRBi8:
7709	case ARM::t2LDRHi8:
7710	case ARM::t2LDRSBi8:
7711	case ARM::t2LDRSHi8:
7712	case ARM::t2LDRi8:
7713	case ARM::t2STRBi8:
7714	case ARM::t2STRHi8:
7715	case ARM::t2STRi8: {
7716	// op: Rt
7717	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7718	op &= UINT64_C(`15`);
7719	op <<= `12`;
7720	Value \|= op;
7721	// op: addr
7722	op = getT2AddrModeImmOpValue<`8`,`0`>(MI, `1`, Fixups, STI);
7723	Value \|= (op & UINT64_C(`7680`)) << `7`;
7724	Value \|= (op & UINT64_C(`256`)) << `1`;
7725	Value \|= (op & UINT64_C(`255`));
7726	break;
7727	}
7728	case ARM::t2LDRB_PRE:
7729	case ARM::t2LDRH_PRE:
7730	case ARM::t2LDRSB_PRE:
7731	case ARM::t2LDRSH_PRE:
7732	case ARM::t2LDR_PRE: {
7733	// op: Rt
7734	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7735	op &= UINT64_C(`15`);
7736	op <<= `12`;
7737	Value \|= op;
7738	// op: addr
7739	op = getT2AddrModeImmOpValue<`8`,`0`>(MI, `2`, Fixups, STI);
7740	Value \|= (op & UINT64_C(`7680`)) << `7`;
7741	Value \|= (op & UINT64_C(`256`)) << `1`;
7742	Value \|= (op & UINT64_C(`255`));
7743	break;
7744	}
7745	case ARM::t2LDRBs:
7746	case ARM::t2LDRHs:
7747	case ARM::t2LDRSBs:
7748	case ARM::t2LDRSHs:
7749	case ARM::t2LDRs:
7750	case ARM::t2STRBs:
7751	case ARM::t2STRHs:
7752	case ARM::t2STRs: {
7753	// op: Rt
7754	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7755	op &= UINT64_C(`15`);
7756	op <<= `12`;
7757	Value \|= op;
7758	// op: addr
7759	op = getT2AddrModeSORegOpValue(MI, `1`, Fixups, STI);
7760	Value \|= (op & UINT64_C(`960`)) << `10`;
7761	Value \|= (op & UINT64_C(`3`)) << `4`;
7762	Value \|= (op & UINT64_C(`60`)) >> `2`;
7763	break;
7764	}
7765	case ARM::MRC2:
7766	case ARM::t2MRC:
7767	case ARM::t2MRC2: {
7768	// op: Rt
7769	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7770	op &= UINT64_C(`15`);
7771	op <<= `12`;
7772	Value \|= op;
7773	// op: cop
7774	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
7775	op &= UINT64_C(`15`);
7776	op <<= `8`;
7777	Value \|= op;
7778	// op: opc1
7779	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
7780	op &= UINT64_C(`7`);
7781	op <<= `21`;
7782	Value \|= op;
7783	// op: opc2
7784	op = getMachineOpValue(MI, MI.getOperand(`5`), Fixups, STI);
7785	op &= UINT64_C(`7`);
7786	op <<= `5`;
7787	Value \|= op;
7788	// op: CRm
7789	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
7790	op &= UINT64_C(`15`);
7791	Value \|= op;
7792	// op: CRn
7793	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
7794	op &= UINT64_C(`15`);
7795	op <<= `16`;
7796	Value \|= op;
7797	break;
7798	}
7799	case ARM::tLDRBi:
7800	case ARM::tLDRHi:
7801	case ARM::tLDRi:
7802	case ARM::tSTRBi:
7803	case ARM::tSTRHi:
7804	case ARM::tSTRi: {
7805	// op: Rt
7806	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7807	op &= UINT64_C(`7`);
7808	Value \|= op;
7809	// op: addr
7810	op = getAddrModeISOpValue(MI, `1`, Fixups, STI);
7811	op &= UINT64_C(`255`);
7812	op <<= `3`;
7813	Value \|= op;
7814	break;
7815	}
7816	case ARM::tLDRBr:
7817	case ARM::tLDRHr:
7818	case ARM::tLDRSB:
7819	case ARM::tLDRSH:
7820	case ARM::tLDRr:
7821	case ARM::tSTRBr:
7822	case ARM::tSTRHr:
7823	case ARM::tSTRr: {
7824	// op: Rt
7825	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7826	op &= UINT64_C(`7`);
7827	Value \|= op;
7828	// op: addr
7829	op = getThumbAddrModeRegRegOpValue(MI, `1`, Fixups, STI);
7830	op &= UINT64_C(`63`);
7831	op <<= `3`;
7832	Value \|= op;
7833	break;
7834	}
7835	case ARM::tLDRpci: {
7836	// op: Rt
7837	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7838	op &= UINT64_C(`7`);
7839	op <<= `8`;
7840	Value \|= op;
7841	// op: addr
7842	op = getAddrModePCOpValue(MI, `1`, Fixups, STI);
7843	op &= UINT64_C(`255`);
7844	Value \|= op;
7845	break;
7846	}
7847	case ARM::tLDRspi:
7848	case ARM::tSTRspi: {
7849	// op: Rt
7850	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7851	op &= UINT64_C(`7`);
7852	op <<= `8`;
7853	Value \|= op;
7854	// op: addr
7855	op = getAddrModeThumbSPOpValue(MI, `1`, Fixups, STI);
7856	op &= UINT64_C(`255`);
7857	Value \|= op;
7858	break;
7859	}
7860	case ARM::t2STRB_POST:
7861	case ARM::t2STRH_POST:
7862	case ARM::t2STR_POST: {
7863	// op: Rt
7864	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
7865	op &= UINT64_C(`15`);
7866	op <<= `12`;
7867	Value \|= op;
7868	// op: Rn
7869	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
7870	op &= UINT64_C(`15`);
7871	op <<= `16`;
7872	Value \|= op;
7873	// op: offset
7874	op = getT2AddrModeImm8OffsetOpValue(MI, `3`, Fixups, STI);
7875	Value \|= (op & UINT64_C(`256`)) << `1`;
7876	Value \|= (op & UINT64_C(`255`));
7877	break;
7878	}
7879	case ARM::t2STRD_POST: {
7880	// op: Rt
7881	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
7882	op &= UINT64_C(`15`);
7883	op <<= `12`;
7884	Value \|= op;
7885	// op: Rt2
7886	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
7887	op &= UINT64_C(`15`);
7888	op <<= `8`;
7889	Value \|= op;
7890	// op: addr
7891	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
7892	op &= UINT64_C(`15`);
7893	op <<= `16`;
7894	Value \|= op;
7895	// op: imm
7896	op = getT2ScaledImmOpValue<`8`,`2`>(MI, `4`, Fixups, STI);
7897	Value \|= (op & UINT64_C(`256`)) << `15`;
7898	Value \|= (op & UINT64_C(`255`));
7899	break;
7900	}
7901	case ARM::t2STRD_PRE: {
7902	// op: Rt
7903	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
7904	op &= UINT64_C(`15`);
7905	op <<= `12`;
7906	Value \|= op;
7907	// op: Rt2
7908	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
7909	op &= UINT64_C(`15`);
7910	op <<= `8`;
7911	Value \|= op;
7912	// op: addr
7913	op = getT2AddrModeImm8s4OpValue(MI, `3`, Fixups, STI);
7914	Value \|= (op & UINT64_C(`256`)) << `15`;
7915	Value \|= (op & UINT64_C(`7680`)) << `7`;
7916	Value \|= (op & UINT64_C(`255`));
7917	break;
7918	}
7919	case ARM::t2STRB_PRE:
7920	case ARM::t2STRH_PRE:
7921	case ARM::t2STR_PRE: {
7922	// op: Rt
7923	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
7924	op &= UINT64_C(`15`);
7925	op <<= `12`;
7926	Value \|= op;
7927	// op: addr
7928	op = getT2AddrModeImmOpValue<`8`,`0`>(MI, `2`, Fixups, STI);
7929	Value \|= (op & UINT64_C(`7680`)) << `7`;
7930	Value \|= (op & UINT64_C(`256`)) << `1`;
7931	Value \|= (op & UINT64_C(`255`));
7932	break;
7933	}
7934	case ARM::MVE_VMOV_q_rr: {
7935	// op: Rt
7936	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
7937	op &= UINT64_C(`15`);
7938	Value \|= op;
7939	// op: Rt2
7940	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
7941	op &= UINT64_C(`15`);
7942	op <<= `16`;
7943	Value \|= op;
7944	// op: Qd
7945	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7946	Value \|= (op & UINT64_C(`8`)) << `19`;
7947	Value \|= (op & UINT64_C(`7`)) << `13`;
7948	// op: idx2
7949	op = getMVEPairVectorIndexOpValue<`0`>(MI, `5`, Fixups, STI);
7950	op &= UINT64_C(`1`);
7951	op <<= `4`;
7952	Value \|= op;
7953	break;
7954	}
7955	case ARM::MCRR2:
7956	case ARM::t2MCRR:
7957	case ARM::t2MCRR2: {
7958	// op: Rt
7959	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
7960	op &= UINT64_C(`15`);
7961	op <<= `12`;
7962	Value \|= op;
7963	// op: Rt2
7964	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
7965	op &= UINT64_C(`15`);
7966	op <<= `16`;
7967	Value \|= op;
7968	// op: cop
7969	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7970	op &= UINT64_C(`15`);
7971	op <<= `8`;
7972	Value \|= op;
7973	// op: opc1
7974	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
7975	op &= UINT64_C(`15`);
7976	op <<= `4`;
7977	Value \|= op;
7978	// op: CRm
7979	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
7980	op &= UINT64_C(`15`);
7981	Value \|= op;
7982	break;
7983	}
7984	case ARM::MCR2:
7985	case ARM::t2MCR:
7986	case ARM::t2MCR2: {
7987	// op: Rt
7988	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
7989	op &= UINT64_C(`15`);
7990	op <<= `12`;
7991	Value \|= op;
7992	// op: cop
7993	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
7994	op &= UINT64_C(`15`);
7995	op <<= `8`;
7996	Value \|= op;
7997	// op: opc1
7998	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
7999	op &= UINT64_C(`7`);
8000	op <<= `21`;
8001	Value \|= op;
8002	// op: opc2
8003	op = getMachineOpValue(MI, MI.getOperand(`5`), Fixups, STI);
8004	op &= UINT64_C(`7`);
8005	op <<= `5`;
8006	Value \|= op;
8007	// op: CRm
8008	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
8009	op &= UINT64_C(`15`);
8010	Value \|= op;
8011	// op: CRn
8012	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
8013	op &= UINT64_C(`15`);
8014	op <<= `16`;
8015	Value \|= op;
8016	break;
8017	}
8018	case ARM::t2MSR_M: {
8019	// op: SYSm
8020	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8021	Value \|= (op & UINT64_C(`3072`));
8022	Value \|= (op & UINT64_C(`255`));
8023	// op: Rn
8024	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
8025	op &= UINT64_C(`15`);
8026	op <<= `16`;
8027	Value \|= op;
8028	break;
8029	}
8030	case ARM::VCVTASD:
8031	case ARM::VCVTAUD:
8032	case ARM::VCVTMSD:
8033	case ARM::VCVTMUD:
8034	case ARM::VCVTNSD:
8035	case ARM::VCVTNUD:
8036	case ARM::VCVTPSD:
8037	case ARM::VCVTPUD: {
8038	// op: Sd
8039	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8040	Value \|= (op & UINT64_C(`1`)) << `22`;
8041	Value \|= (op & UINT64_C(`30`)) << `11`;
8042	// op: Dm
8043	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
8044	Value \|= (op & UINT64_C(`16`)) << `1`;
8045	Value \|= (op & UINT64_C(`15`));
8046	break;
8047	}
8048	case ARM::VCVTASH:
8049	case ARM::VCVTASS:
8050	case ARM::VCVTAUH:
8051	case ARM::VCVTAUS:
8052	case ARM::VCVTMSH:
8053	case ARM::VCVTMSS:
8054	case ARM::VCVTMUH:
8055	case ARM::VCVTMUS:
8056	case ARM::VCVTNSH:
8057	case ARM::VCVTNSS:
8058	case ARM::VCVTNUH:
8059	case ARM::VCVTNUS:
8060	case ARM::VCVTPSH:
8061	case ARM::VCVTPSS:
8062	case ARM::VCVTPUH:
8063	case ARM::VCVTPUS:
8064	case ARM::VINSH:
8065	case ARM::VMOVH:
8066	case ARM::VRINTAH:
8067	case ARM::VRINTAS:
8068	case ARM::VRINTMH:
8069	case ARM::VRINTMS:
8070	case ARM::VRINTNH:
8071	case ARM::VRINTNS:
8072	case ARM::VRINTPH:
8073	case ARM::VRINTPS: {
8074	// op: Sd
8075	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8076	Value \|= (op & UINT64_C(`1`)) << `22`;
8077	Value \|= (op & UINT64_C(`30`)) << `11`;
8078	// op: Sm
8079	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
8080	Value \|= (op & UINT64_C(`1`)) << `5`;
8081	Value \|= (op & UINT64_C(`30`)) >> `1`;
8082	break;
8083	}
8084	case ARM::VFP_VMAXNMH:
8085	case ARM::VFP_VMAXNMS:
8086	case ARM::VFP_VMINNMH:
8087	case ARM::VFP_VMINNMS:
8088	case ARM::VSELEQH:
8089	case ARM::VSELEQS:
8090	case ARM::VSELGEH:
8091	case ARM::VSELGES:
8092	case ARM::VSELGTH:
8093	case ARM::VSELGTS:
8094	case ARM::VSELVSH:
8095	case ARM::VSELVSS: {
8096	// op: Sd
8097	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8098	Value \|= (op & UINT64_C(`1`)) << `22`;
8099	Value \|= (op & UINT64_C(`30`)) << `11`;
8100	// op: Sn
8101	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
8102	Value \|= (op & UINT64_C(`30`)) << `15`;
8103	Value \|= (op & UINT64_C(`1`)) << `7`;
8104	// op: Sm
8105	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
8106	Value \|= (op & UINT64_C(`1`)) << `5`;
8107	Value \|= (op & UINT64_C(`30`)) >> `1`;
8108	break;
8109	}
8110	case ARM::VDUP16d:
8111	case ARM::VDUP16q:
8112	case ARM::VDUP32d:
8113	case ARM::VDUP32q:
8114	case ARM::VDUP8d:
8115	case ARM::VDUP8q: {
8116	// op: V
8117	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8118	Value \|= (op & UINT64_C(`15`)) << `16`;
8119	Value \|= (op & UINT64_C(`16`)) << `3`;
8120	// op: R
8121	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
8122	op &= UINT64_C(`15`);
8123	op <<= `12`;
8124	Value \|= op;
8125	// op: p
8126	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
8127	op &= UINT64_C(`15`);
8128	op <<= `28`;
8129	Value \|= op;
8130	Value = NEONThumb2DupPostEncoder(MI, Value, STI);
8131	break;
8132	}
8133	case ARM::VSETLNi16: {
8134	// op: V
8135	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8136	Value \|= (op & UINT64_C(`15`)) << `16`;
8137	Value \|= (op & UINT64_C(`16`)) << `3`;
8138	// op: R
8139	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
8140	op &= UINT64_C(`15`);
8141	op <<= `12`;
8142	Value \|= op;
8143	// op: p
8144	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
8145	op &= UINT64_C(`15`);
8146	op <<= `28`;
8147	Value \|= op;
8148	// op: lane
8149	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
8150	Value \|= (op & UINT64_C(`2`)) << `20`;
8151	Value \|= (op & UINT64_C(`1`)) << `6`;
8152	Value = NEONThumb2DupPostEncoder(MI, Value, STI);
8153	break;
8154	}
8155	case ARM::VSETLNi8: {
8156	// op: V
8157	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8158	Value \|= (op & UINT64_C(`15`)) << `16`;
8159	Value \|= (op & UINT64_C(`16`)) << `3`;
8160	// op: R
8161	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
8162	op &= UINT64_C(`15`);
8163	op <<= `12`;
8164	Value \|= op;
8165	// op: p
8166	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
8167	op &= UINT64_C(`15`);
8168	op <<= `28`;
8169	Value \|= op;
8170	// op: lane
8171	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
8172	Value \|= (op & UINT64_C(`4`)) << `19`;
8173	Value \|= (op & UINT64_C(`3`)) << `5`;
8174	Value = NEONThumb2DupPostEncoder(MI, Value, STI);
8175	break;
8176	}
8177	case ARM::VSETLNi32: {
8178	// op: V
8179	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8180	Value \|= (op & UINT64_C(`15`)) << `16`;
8181	Value \|= (op & UINT64_C(`16`)) << `3`;
8182	// op: R
8183	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
8184	op &= UINT64_C(`15`);
8185	op <<= `12`;
8186	Value \|= op;
8187	// op: p
8188	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
8189	op &= UINT64_C(`15`);
8190	op <<= `28`;
8191	Value \|= op;
8192	// op: lane
8193	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
8194	op &= UINT64_C(`1`);
8195	op <<= `21`;
8196	Value \|= op;
8197	Value = NEONThumb2DupPostEncoder(MI, Value, STI);
8198	break;
8199	}
8200	case ARM::VGETLNs16:
8201	case ARM::VGETLNu16: {
8202	// op: V
8203	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
8204	Value \|= (op & UINT64_C(`15`)) << `16`;
8205	Value \|= (op & UINT64_C(`16`)) << `3`;
8206	// op: R
8207	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8208	op &= UINT64_C(`15`);
8209	op <<= `12`;
8210	Value \|= op;
8211	// op: p
8212	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
8213	op &= UINT64_C(`15`);
8214	op <<= `28`;
8215	Value \|= op;
8216	// op: lane
8217	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
8218	Value \|= (op & UINT64_C(`2`)) << `20`;
8219	Value \|= (op & UINT64_C(`1`)) << `6`;
8220	Value = NEONThumb2DupPostEncoder(MI, Value, STI);
8221	break;
8222	}
8223	case ARM::VGETLNs8:
8224	case ARM::VGETLNu8: {
8225	// op: V
8226	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
8227	Value \|= (op & UINT64_C(`15`)) << `16`;
8228	Value \|= (op & UINT64_C(`16`)) << `3`;
8229	// op: R
8230	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8231	op &= UINT64_C(`15`);
8232	op <<= `12`;
8233	Value \|= op;
8234	// op: p
8235	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
8236	op &= UINT64_C(`15`);
8237	op <<= `28`;
8238	Value \|= op;
8239	// op: lane
8240	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
8241	Value \|= (op & UINT64_C(`4`)) << `19`;
8242	Value \|= (op & UINT64_C(`3`)) << `5`;
8243	Value = NEONThumb2DupPostEncoder(MI, Value, STI);
8244	break;
8245	}
8246	case ARM::VGETLNi32: {
8247	// op: V
8248	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
8249	Value \|= (op & UINT64_C(`15`)) << `16`;
8250	Value \|= (op & UINT64_C(`16`)) << `3`;
8251	// op: R
8252	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8253	op &= UINT64_C(`15`);
8254	op <<= `12`;
8255	Value \|= op;
8256	// op: p
8257	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
8258	op &= UINT64_C(`15`);
8259	op <<= `28`;
8260	Value \|= op;
8261	// op: lane
8262	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
8263	op &= UINT64_C(`1`);
8264	op <<= `21`;
8265	Value \|= op;
8266	Value = NEONThumb2DupPostEncoder(MI, Value, STI);
8267	break;
8268	}
8269	case ARM::MVE_VST20_16:
8270	case ARM::MVE_VST20_32:
8271	case ARM::MVE_VST20_8:
8272	case ARM::MVE_VST21_16:
8273	case ARM::MVE_VST21_32:
8274	case ARM::MVE_VST21_8:
8275	case ARM::MVE_VST40_16:
8276	case ARM::MVE_VST40_32:
8277	case ARM::MVE_VST40_8:
8278	case ARM::MVE_VST41_16:
8279	case ARM::MVE_VST41_32:
8280	case ARM::MVE_VST41_8:
8281	case ARM::MVE_VST42_16:
8282	case ARM::MVE_VST42_32:
8283	case ARM::MVE_VST42_8:
8284	case ARM::MVE_VST43_16:
8285	case ARM::MVE_VST43_32:
8286	case ARM::MVE_VST43_8: {
8287	// op: VQd
8288	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8289	op &= UINT64_C(`7`);
8290	op <<= `13`;
8291	Value \|= op;
8292	// op: Rn
8293	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
8294	op &= UINT64_C(`15`);
8295	op <<= `16`;
8296	Value \|= op;
8297	break;
8298	}
8299	case ARM::MVE_VLD20_16:
8300	case ARM::MVE_VLD20_32:
8301	case ARM::MVE_VLD20_8:
8302	case ARM::MVE_VLD21_16:
8303	case ARM::MVE_VLD21_32:
8304	case ARM::MVE_VLD21_8:
8305	case ARM::MVE_VLD40_16:
8306	case ARM::MVE_VLD40_32:
8307	case ARM::MVE_VLD40_8:
8308	case ARM::MVE_VLD41_16:
8309	case ARM::MVE_VLD41_32:
8310	case ARM::MVE_VLD41_8:
8311	case ARM::MVE_VLD42_16:
8312	case ARM::MVE_VLD42_32:
8313	case ARM::MVE_VLD42_8:
8314	case ARM::MVE_VLD43_16:
8315	case ARM::MVE_VLD43_32:
8316	case ARM::MVE_VLD43_8: {
8317	// op: VQd
8318	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8319	op &= UINT64_C(`7`);
8320	op <<= `13`;
8321	Value \|= op;
8322	// op: Rn
8323	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
8324	op &= UINT64_C(`15`);
8325	op <<= `16`;
8326	Value \|= op;
8327	break;
8328	}
8329	case ARM::MVE_VLD20_16_wb:
8330	case ARM::MVE_VLD20_32_wb:
8331	case ARM::MVE_VLD20_8_wb:
8332	case ARM::MVE_VLD21_16_wb:
8333	case ARM::MVE_VLD21_32_wb:
8334	case ARM::MVE_VLD21_8_wb:
8335	case ARM::MVE_VLD40_16_wb:
8336	case ARM::MVE_VLD40_32_wb:
8337	case ARM::MVE_VLD40_8_wb:
8338	case ARM::MVE_VLD41_16_wb:
8339	case ARM::MVE_VLD41_32_wb:
8340	case ARM::MVE_VLD41_8_wb:
8341	case ARM::MVE_VLD42_16_wb:
8342	case ARM::MVE_VLD42_32_wb:
8343	case ARM::MVE_VLD42_8_wb:
8344	case ARM::MVE_VLD43_16_wb:
8345	case ARM::MVE_VLD43_32_wb:
8346	case ARM::MVE_VLD43_8_wb: {
8347	// op: VQd
8348	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8349	op &= UINT64_C(`7`);
8350	op <<= `13`;
8351	Value \|= op;
8352	// op: Rn
8353	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
8354	op &= UINT64_C(`15`);
8355	op <<= `16`;
8356	Value \|= op;
8357	break;
8358	}
8359	case ARM::MVE_VST20_16_wb:
8360	case ARM::MVE_VST20_32_wb:
8361	case ARM::MVE_VST20_8_wb:
8362	case ARM::MVE_VST21_16_wb:
8363	case ARM::MVE_VST21_32_wb:
8364	case ARM::MVE_VST21_8_wb:
8365	case ARM::MVE_VST40_16_wb:
8366	case ARM::MVE_VST40_32_wb:
8367	case ARM::MVE_VST40_8_wb:
8368	case ARM::MVE_VST41_16_wb:
8369	case ARM::MVE_VST41_32_wb:
8370	case ARM::MVE_VST41_8_wb:
8371	case ARM::MVE_VST42_16_wb:
8372	case ARM::MVE_VST42_32_wb:
8373	case ARM::MVE_VST42_8_wb:
8374	case ARM::MVE_VST43_16_wb:
8375	case ARM::MVE_VST43_32_wb:
8376	case ARM::MVE_VST43_8_wb: {
8377	// op: VQd
8378	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
8379	op &= UINT64_C(`7`);
8380	op <<= `13`;
8381	Value \|= op;
8382	// op: Rn
8383	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
8384	op &= UINT64_C(`15`);
8385	op <<= `16`;
8386	Value \|= op;
8387	break;
8388	}
8389	case ARM::VLD1d16:
8390	case ARM::VLD1d16T:
8391	case ARM::VLD1d32:
8392	case ARM::VLD1d32T:
8393	case ARM::VLD1d64:
8394	case ARM::VLD1d64T:
8395	case ARM::VLD1d8:
8396	case ARM::VLD1d8T: {
8397	// op: Vd
8398	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8399	Value \|= (op & UINT64_C(`16`)) << `18`;
8400	Value \|= (op & UINT64_C(`15`)) << `12`;
8401	// op: Rn
8402	op = getAddrMode6AddressOpValue(MI, `1`, Fixups, STI);
8403	Value \|= (op & UINT64_C(`15`)) << `16`;
8404	Value \|= (op & UINT64_C(`16`));
8405	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8406	break;
8407	}
8408	case ARM::VLD1LNd16: {
8409	// op: Vd
8410	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8411	Value \|= (op & UINT64_C(`16`)) << `18`;
8412	Value \|= (op & UINT64_C(`15`)) << `12`;
8413	// op: Rn
8414	op = getAddrMode6AddressOpValue(MI, `1`, Fixups, STI);
8415	Value \|= (op & UINT64_C(`15`)) << `16`;
8416	Value \|= (op & UINT64_C(`48`));
8417	// op: lane
8418	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
8419	op &= UINT64_C(`3`);
8420	op <<= `6`;
8421	Value \|= op;
8422	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8423	break;
8424	}
8425	case ARM::VLD1d16Q:
8426	case ARM::VLD1d32Q:
8427	case ARM::VLD1d64Q:
8428	case ARM::VLD1d8Q:
8429	case ARM::VLD1q16:
8430	case ARM::VLD1q32:
8431	case ARM::VLD1q64:
8432	case ARM::VLD1q8:
8433	case ARM::VLD2b16:
8434	case ARM::VLD2b32:
8435	case ARM::VLD2b8:
8436	case ARM::VLD2d16:
8437	case ARM::VLD2d32:
8438	case ARM::VLD2d8:
8439	case ARM::VLD2q16:
8440	case ARM::VLD2q32:
8441	case ARM::VLD2q8: {
8442	// op: Vd
8443	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8444	Value \|= (op & UINT64_C(`16`)) << `18`;
8445	Value \|= (op & UINT64_C(`15`)) << `12`;
8446	// op: Rn
8447	op = getAddrMode6AddressOpValue(MI, `1`, Fixups, STI);
8448	Value \|= (op & UINT64_C(`15`)) << `16`;
8449	Value \|= (op & UINT64_C(`48`));
8450	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8451	break;
8452	}
8453	case ARM::VLD1LNd8: {
8454	// op: Vd
8455	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8456	Value \|= (op & UINT64_C(`16`)) << `18`;
8457	Value \|= (op & UINT64_C(`15`)) << `12`;
8458	// op: Rn
8459	op = getAddrMode6AddressOpValue(MI, `1`, Fixups, STI);
8460	op &= UINT64_C(`15`);
8461	op <<= `16`;
8462	Value \|= op;
8463	// op: lane
8464	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
8465	op &= UINT64_C(`7`);
8466	op <<= `5`;
8467	Value \|= op;
8468	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8469	break;
8470	}
8471	case ARM::VLD1LNd32_UPD: {
8472	// op: Vd
8473	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8474	Value \|= (op & UINT64_C(`16`)) << `18`;
8475	Value \|= (op & UINT64_C(`15`)) << `12`;
8476	// op: Rn
8477	op = getAddrMode6AddressOpValue(MI, `2`, Fixups, STI);
8478	Value \|= (op & UINT64_C(`15`)) << `16`;
8479	Value \|= (op & UINT64_C(`16`)) << `1`;
8480	Value \|= (op & UINT64_C(`16`));
8481	// op: Rm
8482	op = getAddrMode6OffsetOpValue(MI, `4`, Fixups, STI);
8483	op &= UINT64_C(`15`);
8484	Value \|= op;
8485	// op: lane
8486	op = getMachineOpValue(MI, MI.getOperand(`6`), Fixups, STI);
8487	op &= UINT64_C(`1`);
8488	op <<= `7`;
8489	Value \|= op;
8490	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8491	break;
8492	}
8493	case ARM::VLD1LNd16_UPD: {
8494	// op: Vd
8495	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8496	Value \|= (op & UINT64_C(`16`)) << `18`;
8497	Value \|= (op & UINT64_C(`15`)) << `12`;
8498	// op: Rn
8499	op = getAddrMode6AddressOpValue(MI, `2`, Fixups, STI);
8500	Value \|= (op & UINT64_C(`15`)) << `16`;
8501	Value \|= (op & UINT64_C(`16`));
8502	// op: Rm
8503	op = getAddrMode6OffsetOpValue(MI, `4`, Fixups, STI);
8504	op &= UINT64_C(`15`);
8505	Value \|= op;
8506	// op: lane
8507	op = getMachineOpValue(MI, MI.getOperand(`6`), Fixups, STI);
8508	op &= UINT64_C(`3`);
8509	op <<= `6`;
8510	Value \|= op;
8511	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8512	break;
8513	}
8514	case ARM::VLD1d16Twb_register:
8515	case ARM::VLD1d16wb_register:
8516	case ARM::VLD1d32Twb_register:
8517	case ARM::VLD1d32wb_register:
8518	case ARM::VLD1d64Twb_register:
8519	case ARM::VLD1d64wb_register:
8520	case ARM::VLD1d8Twb_register:
8521	case ARM::VLD1d8wb_register: {
8522	// op: Vd
8523	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8524	Value \|= (op & UINT64_C(`16`)) << `18`;
8525	Value \|= (op & UINT64_C(`15`)) << `12`;
8526	// op: Rn
8527	op = getAddrMode6AddressOpValue(MI, `2`, Fixups, STI);
8528	Value \|= (op & UINT64_C(`15`)) << `16`;
8529	Value \|= (op & UINT64_C(`16`));
8530	// op: Rm
8531	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
8532	op &= UINT64_C(`15`);
8533	Value \|= op;
8534	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8535	break;
8536	}
8537	case ARM::VLD2LNd32:
8538	case ARM::VLD2LNq32: {
8539	// op: Vd
8540	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8541	Value \|= (op & UINT64_C(`16`)) << `18`;
8542	Value \|= (op & UINT64_C(`15`)) << `12`;
8543	// op: Rn
8544	op = getAddrMode6AddressOpValue(MI, `2`, Fixups, STI);
8545	Value \|= (op & UINT64_C(`15`)) << `16`;
8546	Value \|= (op & UINT64_C(`16`));
8547	// op: lane
8548	op = getMachineOpValue(MI, MI.getOperand(`6`), Fixups, STI);
8549	op &= UINT64_C(`1`);
8550	op <<= `7`;
8551	Value \|= op;
8552	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8553	break;
8554	}
8555	case ARM::VLD2LNd16:
8556	case ARM::VLD2LNq16: {
8557	// op: Vd
8558	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8559	Value \|= (op & UINT64_C(`16`)) << `18`;
8560	Value \|= (op & UINT64_C(`15`)) << `12`;
8561	// op: Rn
8562	op = getAddrMode6AddressOpValue(MI, `2`, Fixups, STI);
8563	Value \|= (op & UINT64_C(`15`)) << `16`;
8564	Value \|= (op & UINT64_C(`16`));
8565	// op: lane
8566	op = getMachineOpValue(MI, MI.getOperand(`6`), Fixups, STI);
8567	op &= UINT64_C(`3`);
8568	op <<= `6`;
8569	Value \|= op;
8570	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8571	break;
8572	}
8573	case ARM::VLD2LNd8: {
8574	// op: Vd
8575	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8576	Value \|= (op & UINT64_C(`16`)) << `18`;
8577	Value \|= (op & UINT64_C(`15`)) << `12`;
8578	// op: Rn
8579	op = getAddrMode6AddressOpValue(MI, `2`, Fixups, STI);
8580	Value \|= (op & UINT64_C(`15`)) << `16`;
8581	Value \|= (op & UINT64_C(`16`));
8582	// op: lane
8583	op = getMachineOpValue(MI, MI.getOperand(`6`), Fixups, STI);
8584	op &= UINT64_C(`7`);
8585	op <<= `5`;
8586	Value \|= op;
8587	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8588	break;
8589	}
8590	case ARM::VLD1d16Twb_fixed:
8591	case ARM::VLD1d16wb_fixed:
8592	case ARM::VLD1d32Twb_fixed:
8593	case ARM::VLD1d32wb_fixed:
8594	case ARM::VLD1d64Twb_fixed:
8595	case ARM::VLD1d64wb_fixed:
8596	case ARM::VLD1d8Twb_fixed:
8597	case ARM::VLD1d8wb_fixed: {
8598	// op: Vd
8599	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8600	Value \|= (op & UINT64_C(`16`)) << `18`;
8601	Value \|= (op & UINT64_C(`15`)) << `12`;
8602	// op: Rn
8603	op = getAddrMode6AddressOpValue(MI, `2`, Fixups, STI);
8604	Value \|= (op & UINT64_C(`15`)) << `16`;
8605	Value \|= (op & UINT64_C(`16`));
8606	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8607	break;
8608	}
8609	case ARM::VLD1d16Qwb_register:
8610	case ARM::VLD1d32Qwb_register:
8611	case ARM::VLD1d64Qwb_register:
8612	case ARM::VLD1d8Qwb_register:
8613	case ARM::VLD1q16wb_register:
8614	case ARM::VLD1q32wb_register:
8615	case ARM::VLD1q64wb_register:
8616	case ARM::VLD1q8wb_register:
8617	case ARM::VLD2b16wb_register:
8618	case ARM::VLD2b32wb_register:
8619	case ARM::VLD2b8wb_register:
8620	case ARM::VLD2d16wb_register:
8621	case ARM::VLD2d32wb_register:
8622	case ARM::VLD2d8wb_register:
8623	case ARM::VLD2q16wb_register:
8624	case ARM::VLD2q32wb_register:
8625	case ARM::VLD2q8wb_register: {
8626	// op: Vd
8627	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8628	Value \|= (op & UINT64_C(`16`)) << `18`;
8629	Value \|= (op & UINT64_C(`15`)) << `12`;
8630	// op: Rn
8631	op = getAddrMode6AddressOpValue(MI, `2`, Fixups, STI);
8632	Value \|= (op & UINT64_C(`15`)) << `16`;
8633	Value \|= (op & UINT64_C(`48`));
8634	// op: Rm
8635	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
8636	op &= UINT64_C(`15`);
8637	Value \|= op;
8638	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8639	break;
8640	}
8641	case ARM::VLD1d16Qwb_fixed:
8642	case ARM::VLD1d32Qwb_fixed:
8643	case ARM::VLD1d64Qwb_fixed:
8644	case ARM::VLD1d8Qwb_fixed:
8645	case ARM::VLD1q16wb_fixed:
8646	case ARM::VLD1q32wb_fixed:
8647	case ARM::VLD1q64wb_fixed:
8648	case ARM::VLD1q8wb_fixed:
8649	case ARM::VLD2b16wb_fixed:
8650	case ARM::VLD2b32wb_fixed:
8651	case ARM::VLD2b8wb_fixed:
8652	case ARM::VLD2d16wb_fixed:
8653	case ARM::VLD2d32wb_fixed:
8654	case ARM::VLD2d8wb_fixed:
8655	case ARM::VLD2q16wb_fixed:
8656	case ARM::VLD2q32wb_fixed:
8657	case ARM::VLD2q8wb_fixed: {
8658	// op: Vd
8659	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8660	Value \|= (op & UINT64_C(`16`)) << `18`;
8661	Value \|= (op & UINT64_C(`15`)) << `12`;
8662	// op: Rn
8663	op = getAddrMode6AddressOpValue(MI, `2`, Fixups, STI);
8664	Value \|= (op & UINT64_C(`15`)) << `16`;
8665	Value \|= (op & UINT64_C(`48`));
8666	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8667	break;
8668	}
8669	case ARM::VLD1LNd8_UPD: {
8670	// op: Vd
8671	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8672	Value \|= (op & UINT64_C(`16`)) << `18`;
8673	Value \|= (op & UINT64_C(`15`)) << `12`;
8674	// op: Rn
8675	op = getAddrMode6AddressOpValue(MI, `2`, Fixups, STI);
8676	op &= UINT64_C(`15`);
8677	op <<= `16`;
8678	Value \|= op;
8679	// op: Rm
8680	op = getAddrMode6OffsetOpValue(MI, `4`, Fixups, STI);
8681	op &= UINT64_C(`15`);
8682	Value \|= op;
8683	// op: lane
8684	op = getMachineOpValue(MI, MI.getOperand(`6`), Fixups, STI);
8685	op &= UINT64_C(`7`);
8686	op <<= `5`;
8687	Value \|= op;
8688	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8689	break;
8690	}
8691	case ARM::VLD2LNd32_UPD:
8692	case ARM::VLD2LNq32_UPD: {
8693	// op: Vd
8694	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8695	Value \|= (op & UINT64_C(`16`)) << `18`;
8696	Value \|= (op & UINT64_C(`15`)) << `12`;
8697	// op: Rn
8698	op = getAddrMode6AddressOpValue(MI, `3`, Fixups, STI);
8699	Value \|= (op & UINT64_C(`15`)) << `16`;
8700	Value \|= (op & UINT64_C(`16`));
8701	// op: Rm
8702	op = getAddrMode6OffsetOpValue(MI, `5`, Fixups, STI);
8703	op &= UINT64_C(`15`);
8704	Value \|= op;
8705	// op: lane
8706	op = getMachineOpValue(MI, MI.getOperand(`8`), Fixups, STI);
8707	op &= UINT64_C(`1`);
8708	op <<= `7`;
8709	Value \|= op;
8710	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8711	break;
8712	}
8713	case ARM::VLD2LNd16_UPD:
8714	case ARM::VLD2LNq16_UPD: {
8715	// op: Vd
8716	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8717	Value \|= (op & UINT64_C(`16`)) << `18`;
8718	Value \|= (op & UINT64_C(`15`)) << `12`;
8719	// op: Rn
8720	op = getAddrMode6AddressOpValue(MI, `3`, Fixups, STI);
8721	Value \|= (op & UINT64_C(`15`)) << `16`;
8722	Value \|= (op & UINT64_C(`16`));
8723	// op: Rm
8724	op = getAddrMode6OffsetOpValue(MI, `5`, Fixups, STI);
8725	op &= UINT64_C(`15`);
8726	Value \|= op;
8727	// op: lane
8728	op = getMachineOpValue(MI, MI.getOperand(`8`), Fixups, STI);
8729	op &= UINT64_C(`3`);
8730	op <<= `6`;
8731	Value \|= op;
8732	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8733	break;
8734	}
8735	case ARM::VLD2LNd8_UPD: {
8736	// op: Vd
8737	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8738	Value \|= (op & UINT64_C(`16`)) << `18`;
8739	Value \|= (op & UINT64_C(`15`)) << `12`;
8740	// op: Rn
8741	op = getAddrMode6AddressOpValue(MI, `3`, Fixups, STI);
8742	Value \|= (op & UINT64_C(`15`)) << `16`;
8743	Value \|= (op & UINT64_C(`16`));
8744	// op: Rm
8745	op = getAddrMode6OffsetOpValue(MI, `5`, Fixups, STI);
8746	op &= UINT64_C(`15`);
8747	Value \|= op;
8748	// op: lane
8749	op = getMachineOpValue(MI, MI.getOperand(`8`), Fixups, STI);
8750	op &= UINT64_C(`7`);
8751	op <<= `5`;
8752	Value \|= op;
8753	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8754	break;
8755	}
8756	case ARM::VLD3d16:
8757	case ARM::VLD3d32:
8758	case ARM::VLD3d8:
8759	case ARM::VLD3q16:
8760	case ARM::VLD3q32:
8761	case ARM::VLD3q8: {
8762	// op: Vd
8763	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8764	Value \|= (op & UINT64_C(`16`)) << `18`;
8765	Value \|= (op & UINT64_C(`15`)) << `12`;
8766	// op: Rn
8767	op = getAddrMode6AddressOpValue(MI, `3`, Fixups, STI);
8768	Value \|= (op & UINT64_C(`15`)) << `16`;
8769	Value \|= (op & UINT64_C(`16`));
8770	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8771	break;
8772	}
8773	case ARM::VLD3LNd32:
8774	case ARM::VLD3LNq32: {
8775	// op: Vd
8776	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8777	Value \|= (op & UINT64_C(`16`)) << `18`;
8778	Value \|= (op & UINT64_C(`15`)) << `12`;
8779	// op: Rn
8780	op = getAddrMode6AddressOpValue(MI, `3`, Fixups, STI);
8781	op &= UINT64_C(`15`);
8782	op <<= `16`;
8783	Value \|= op;
8784	// op: lane
8785	op = getMachineOpValue(MI, MI.getOperand(`8`), Fixups, STI);
8786	op &= UINT64_C(`1`);
8787	op <<= `7`;
8788	Value \|= op;
8789	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8790	break;
8791	}
8792	case ARM::VLD3LNd16:
8793	case ARM::VLD3LNq16: {
8794	// op: Vd
8795	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8796	Value \|= (op & UINT64_C(`16`)) << `18`;
8797	Value \|= (op & UINT64_C(`15`)) << `12`;
8798	// op: Rn
8799	op = getAddrMode6AddressOpValue(MI, `3`, Fixups, STI);
8800	op &= UINT64_C(`15`);
8801	op <<= `16`;
8802	Value \|= op;
8803	// op: lane
8804	op = getMachineOpValue(MI, MI.getOperand(`8`), Fixups, STI);
8805	op &= UINT64_C(`3`);
8806	op <<= `6`;
8807	Value \|= op;
8808	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8809	break;
8810	}
8811	case ARM::VLD3LNd8: {
8812	// op: Vd
8813	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8814	Value \|= (op & UINT64_C(`16`)) << `18`;
8815	Value \|= (op & UINT64_C(`15`)) << `12`;
8816	// op: Rn
8817	op = getAddrMode6AddressOpValue(MI, `3`, Fixups, STI);
8818	op &= UINT64_C(`15`);
8819	op <<= `16`;
8820	Value \|= op;
8821	// op: lane
8822	op = getMachineOpValue(MI, MI.getOperand(`8`), Fixups, STI);
8823	op &= UINT64_C(`7`);
8824	op <<= `5`;
8825	Value \|= op;
8826	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8827	break;
8828	}
8829	case ARM::VLD3d16_UPD:
8830	case ARM::VLD3d32_UPD:
8831	case ARM::VLD3d8_UPD:
8832	case ARM::VLD3q16_UPD:
8833	case ARM::VLD3q32_UPD:
8834	case ARM::VLD3q8_UPD: {
8835	// op: Vd
8836	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8837	Value \|= (op & UINT64_C(`16`)) << `18`;
8838	Value \|= (op & UINT64_C(`15`)) << `12`;
8839	// op: Rn
8840	op = getAddrMode6AddressOpValue(MI, `4`, Fixups, STI);
8841	Value \|= (op & UINT64_C(`15`)) << `16`;
8842	Value \|= (op & UINT64_C(`16`));
8843	// op: Rm
8844	op = getAddrMode6OffsetOpValue(MI, `6`, Fixups, STI);
8845	op &= UINT64_C(`15`);
8846	Value \|= op;
8847	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8848	break;
8849	}
8850	case ARM::VLD4LNd16:
8851	case ARM::VLD4LNq16: {
8852	// op: Vd
8853	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8854	Value \|= (op & UINT64_C(`16`)) << `18`;
8855	Value \|= (op & UINT64_C(`15`)) << `12`;
8856	// op: Rn
8857	op = getAddrMode6AddressOpValue(MI, `4`, Fixups, STI);
8858	Value \|= (op & UINT64_C(`15`)) << `16`;
8859	Value \|= (op & UINT64_C(`16`));
8860	// op: lane
8861	op = getMachineOpValue(MI, MI.getOperand(`10`), Fixups, STI);
8862	op &= UINT64_C(`3`);
8863	op <<= `6`;
8864	Value \|= op;
8865	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8866	break;
8867	}
8868	case ARM::VLD4LNd8: {
8869	// op: Vd
8870	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8871	Value \|= (op & UINT64_C(`16`)) << `18`;
8872	Value \|= (op & UINT64_C(`15`)) << `12`;
8873	// op: Rn
8874	op = getAddrMode6AddressOpValue(MI, `4`, Fixups, STI);
8875	Value \|= (op & UINT64_C(`15`)) << `16`;
8876	Value \|= (op & UINT64_C(`16`));
8877	// op: lane
8878	op = getMachineOpValue(MI, MI.getOperand(`10`), Fixups, STI);
8879	op &= UINT64_C(`7`);
8880	op <<= `5`;
8881	Value \|= op;
8882	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8883	break;
8884	}
8885	case ARM::VLD4LNd32:
8886	case ARM::VLD4LNq32: {
8887	// op: Vd
8888	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8889	Value \|= (op & UINT64_C(`16`)) << `18`;
8890	Value \|= (op & UINT64_C(`15`)) << `12`;
8891	// op: Rn
8892	op = getAddrMode6AddressOpValue(MI, `4`, Fixups, STI);
8893	Value \|= (op & UINT64_C(`15`)) << `16`;
8894	Value \|= (op & UINT64_C(`48`));
8895	// op: lane
8896	op = getMachineOpValue(MI, MI.getOperand(`10`), Fixups, STI);
8897	op &= UINT64_C(`1`);
8898	op <<= `7`;
8899	Value \|= op;
8900	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8901	break;
8902	}
8903	case ARM::VLD4d16:
8904	case ARM::VLD4d32:
8905	case ARM::VLD4d8:
8906	case ARM::VLD4q16:
8907	case ARM::VLD4q32:
8908	case ARM::VLD4q8: {
8909	// op: Vd
8910	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8911	Value \|= (op & UINT64_C(`16`)) << `18`;
8912	Value \|= (op & UINT64_C(`15`)) << `12`;
8913	// op: Rn
8914	op = getAddrMode6AddressOpValue(MI, `4`, Fixups, STI);
8915	Value \|= (op & UINT64_C(`15`)) << `16`;
8916	Value \|= (op & UINT64_C(`48`));
8917	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8918	break;
8919	}
8920	case ARM::VLD3LNd32_UPD:
8921	case ARM::VLD3LNq32_UPD: {
8922	// op: Vd
8923	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8924	Value \|= (op & UINT64_C(`16`)) << `18`;
8925	Value \|= (op & UINT64_C(`15`)) << `12`;
8926	// op: Rn
8927	op = getAddrMode6AddressOpValue(MI, `4`, Fixups, STI);
8928	op &= UINT64_C(`15`);
8929	op <<= `16`;
8930	Value \|= op;
8931	// op: Rm
8932	op = getAddrMode6OffsetOpValue(MI, `6`, Fixups, STI);
8933	op &= UINT64_C(`15`);
8934	Value \|= op;
8935	// op: lane
8936	op = getMachineOpValue(MI, MI.getOperand(`10`), Fixups, STI);
8937	op &= UINT64_C(`1`);
8938	op <<= `7`;
8939	Value \|= op;
8940	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8941	break;
8942	}
8943	case ARM::VLD3LNd16_UPD:
8944	case ARM::VLD3LNq16_UPD: {
8945	// op: Vd
8946	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8947	Value \|= (op & UINT64_C(`16`)) << `18`;
8948	Value \|= (op & UINT64_C(`15`)) << `12`;
8949	// op: Rn
8950	op = getAddrMode6AddressOpValue(MI, `4`, Fixups, STI);
8951	op &= UINT64_C(`15`);
8952	op <<= `16`;
8953	Value \|= op;
8954	// op: Rm
8955	op = getAddrMode6OffsetOpValue(MI, `6`, Fixups, STI);
8956	op &= UINT64_C(`15`);
8957	Value \|= op;
8958	// op: lane
8959	op = getMachineOpValue(MI, MI.getOperand(`10`), Fixups, STI);
8960	op &= UINT64_C(`3`);
8961	op <<= `6`;
8962	Value \|= op;
8963	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8964	break;
8965	}
8966	case ARM::VLD3LNd8_UPD: {
8967	// op: Vd
8968	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8969	Value \|= (op & UINT64_C(`16`)) << `18`;
8970	Value \|= (op & UINT64_C(`15`)) << `12`;
8971	// op: Rn
8972	op = getAddrMode6AddressOpValue(MI, `4`, Fixups, STI);
8973	op &= UINT64_C(`15`);
8974	op <<= `16`;
8975	Value \|= op;
8976	// op: Rm
8977	op = getAddrMode6OffsetOpValue(MI, `6`, Fixups, STI);
8978	op &= UINT64_C(`15`);
8979	Value \|= op;
8980	// op: lane
8981	op = getMachineOpValue(MI, MI.getOperand(`10`), Fixups, STI);
8982	op &= UINT64_C(`7`);
8983	op <<= `5`;
8984	Value \|= op;
8985	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
8986	break;
8987	}
8988	case ARM::VLD4LNd16_UPD:
8989	case ARM::VLD4LNq16_UPD: {
8990	// op: Vd
8991	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
8992	Value \|= (op & UINT64_C(`16`)) << `18`;
8993	Value \|= (op & UINT64_C(`15`)) << `12`;
8994	// op: Rn
8995	op = getAddrMode6AddressOpValue(MI, `5`, Fixups, STI);
8996	Value \|= (op & UINT64_C(`15`)) << `16`;
8997	Value \|= (op & UINT64_C(`16`));
8998	// op: Rm
8999	op = getAddrMode6OffsetOpValue(MI, `7`, Fixups, STI);
9000	op &= UINT64_C(`15`);
9001	Value \|= op;
9002	// op: lane
9003	op = getMachineOpValue(MI, MI.getOperand(`12`), Fixups, STI);
9004	op &= UINT64_C(`3`);
9005	op <<= `6`;
9006	Value \|= op;
9007	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9008	break;
9009	}
9010	case ARM::VLD4LNd8_UPD: {
9011	// op: Vd
9012	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
9013	Value \|= (op & UINT64_C(`16`)) << `18`;
9014	Value \|= (op & UINT64_C(`15`)) << `12`;
9015	// op: Rn
9016	op = getAddrMode6AddressOpValue(MI, `5`, Fixups, STI);
9017	Value \|= (op & UINT64_C(`15`)) << `16`;
9018	Value \|= (op & UINT64_C(`16`));
9019	// op: Rm
9020	op = getAddrMode6OffsetOpValue(MI, `7`, Fixups, STI);
9021	op &= UINT64_C(`15`);
9022	Value \|= op;
9023	// op: lane
9024	op = getMachineOpValue(MI, MI.getOperand(`12`), Fixups, STI);
9025	op &= UINT64_C(`7`);
9026	op <<= `5`;
9027	Value \|= op;
9028	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9029	break;
9030	}
9031	case ARM::VLD4LNd32_UPD:
9032	case ARM::VLD4LNq32_UPD: {
9033	// op: Vd
9034	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
9035	Value \|= (op & UINT64_C(`16`)) << `18`;
9036	Value \|= (op & UINT64_C(`15`)) << `12`;
9037	// op: Rn
9038	op = getAddrMode6AddressOpValue(MI, `5`, Fixups, STI);
9039	Value \|= (op & UINT64_C(`15`)) << `16`;
9040	Value \|= (op & UINT64_C(`48`));
9041	// op: Rm
9042	op = getAddrMode6OffsetOpValue(MI, `7`, Fixups, STI);
9043	op &= UINT64_C(`15`);
9044	Value \|= op;
9045	// op: lane
9046	op = getMachineOpValue(MI, MI.getOperand(`12`), Fixups, STI);
9047	op &= UINT64_C(`1`);
9048	op <<= `7`;
9049	Value \|= op;
9050	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9051	break;
9052	}
9053	case ARM::VLD4d16_UPD:
9054	case ARM::VLD4d32_UPD:
9055	case ARM::VLD4d8_UPD:
9056	case ARM::VLD4q16_UPD:
9057	case ARM::VLD4q32_UPD:
9058	case ARM::VLD4q8_UPD: {
9059	// op: Vd
9060	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
9061	Value \|= (op & UINT64_C(`16`)) << `18`;
9062	Value \|= (op & UINT64_C(`15`)) << `12`;
9063	// op: Rn
9064	op = getAddrMode6AddressOpValue(MI, `5`, Fixups, STI);
9065	Value \|= (op & UINT64_C(`15`)) << `16`;
9066	Value \|= (op & UINT64_C(`48`));
9067	// op: Rm
9068	op = getAddrMode6OffsetOpValue(MI, `7`, Fixups, STI);
9069	op &= UINT64_C(`15`);
9070	Value \|= op;
9071	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9072	break;
9073	}
9074	case ARM::VLD1DUPd16:
9075	case ARM::VLD1DUPd32:
9076	case ARM::VLD1DUPd8:
9077	case ARM::VLD1DUPq16:
9078	case ARM::VLD1DUPq32:
9079	case ARM::VLD1DUPq8:
9080	case ARM::VLD2DUPd16:
9081	case ARM::VLD2DUPd16x2:
9082	case ARM::VLD2DUPd32:
9083	case ARM::VLD2DUPd32x2:
9084	case ARM::VLD2DUPd8:
9085	case ARM::VLD2DUPd8x2: {
9086	// op: Vd
9087	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
9088	Value \|= (op & UINT64_C(`16`)) << `18`;
9089	Value \|= (op & UINT64_C(`15`)) << `12`;
9090	// op: Rn
9091	op = getAddrMode6DupAddressOpValue(MI, `1`, Fixups, STI);
9092	Value \|= (op & UINT64_C(`15`)) << `16`;
9093	Value \|= (op & UINT64_C(`16`));
9094	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9095	break;
9096	}
9097	case ARM::VLD1DUPd16wb_register:
9098	case ARM::VLD1DUPd32wb_register:
9099	case ARM::VLD1DUPd8wb_register:
9100	case ARM::VLD1DUPq16wb_register:
9101	case ARM::VLD1DUPq32wb_register:
9102	case ARM::VLD1DUPq8wb_register:
9103	case ARM::VLD2DUPd16wb_register:
9104	case ARM::VLD2DUPd16x2wb_register:
9105	case ARM::VLD2DUPd32wb_register:
9106	case ARM::VLD2DUPd32x2wb_register:
9107	case ARM::VLD2DUPd8wb_register:
9108	case ARM::VLD2DUPd8x2wb_register: {
9109	// op: Vd
9110	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
9111	Value \|= (op & UINT64_C(`16`)) << `18`;
9112	Value \|= (op & UINT64_C(`15`)) << `12`;
9113	// op: Rn
9114	op = getAddrMode6DupAddressOpValue(MI, `2`, Fixups, STI);
9115	Value \|= (op & UINT64_C(`15`)) << `16`;
9116	Value \|= (op & UINT64_C(`16`));
9117	// op: Rm
9118	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
9119	op &= UINT64_C(`15`);
9120	Value \|= op;
9121	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9122	break;
9123	}
9124	case ARM::VLD1DUPd16wb_fixed:
9125	case ARM::VLD1DUPd32wb_fixed:
9126	case ARM::VLD1DUPd8wb_fixed:
9127	case ARM::VLD1DUPq16wb_fixed:
9128	case ARM::VLD1DUPq32wb_fixed:
9129	case ARM::VLD1DUPq8wb_fixed:
9130	case ARM::VLD2DUPd16wb_fixed:
9131	case ARM::VLD2DUPd16x2wb_fixed:
9132	case ARM::VLD2DUPd32wb_fixed:
9133	case ARM::VLD2DUPd32x2wb_fixed:
9134	case ARM::VLD2DUPd8wb_fixed:
9135	case ARM::VLD2DUPd8x2wb_fixed: {
9136	// op: Vd
9137	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
9138	Value \|= (op & UINT64_C(`16`)) << `18`;
9139	Value \|= (op & UINT64_C(`15`)) << `12`;
9140	// op: Rn
9141	op = getAddrMode6DupAddressOpValue(MI, `2`, Fixups, STI);
9142	Value \|= (op & UINT64_C(`15`)) << `16`;
9143	Value \|= (op & UINT64_C(`16`));
9144	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9145	break;
9146	}
9147	case ARM::VLD3DUPd16:
9148	case ARM::VLD3DUPd32:
9149	case ARM::VLD3DUPd8:
9150	case ARM::VLD3DUPq16:
9151	case ARM::VLD3DUPq32:
9152	case ARM::VLD3DUPq8: {
9153	// op: Vd
9154	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
9155	Value \|= (op & UINT64_C(`16`)) << `18`;
9156	Value \|= (op & UINT64_C(`15`)) << `12`;
9157	// op: Rn
9158	op = getAddrMode6DupAddressOpValue(MI, `3`, Fixups, STI);
9159	op &= UINT64_C(`15`);
9160	op <<= `16`;
9161	Value \|= op;
9162	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9163	break;
9164	}
9165	case ARM::VLD4DUPd16:
9166	case ARM::VLD4DUPd8:
9167	case ARM::VLD4DUPq16:
9168	case ARM::VLD4DUPq8: {
9169	// op: Vd
9170	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
9171	Value \|= (op & UINT64_C(`16`)) << `18`;
9172	Value \|= (op & UINT64_C(`15`)) << `12`;
9173	// op: Rn
9174	op = getAddrMode6DupAddressOpValue(MI, `4`, Fixups, STI);
9175	Value \|= (op & UINT64_C(`15`)) << `16`;
9176	Value \|= (op & UINT64_C(`16`));
9177	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9178	break;
9179	}
9180	case ARM::VLD4DUPd32:
9181	case ARM::VLD4DUPq32: {
9182	// op: Vd
9183	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
9184	Value \|= (op & UINT64_C(`16`)) << `18`;
9185	Value \|= (op & UINT64_C(`15`)) << `12`;
9186	// op: Rn
9187	op = getAddrMode6DupAddressOpValue(MI, `4`, Fixups, STI);
9188	Value \|= (op & UINT64_C(`15`)) << `16`;
9189	Value \|= (op & UINT64_C(`32`)) << `1`;
9190	Value \|= (op & UINT64_C(`16`));
9191	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9192	break;
9193	}
9194	case ARM::VLD3DUPd16_UPD:
9195	case ARM::VLD3DUPd32_UPD:
9196	case ARM::VLD3DUPd8_UPD:
9197	case ARM::VLD3DUPq16_UPD:
9198	case ARM::VLD3DUPq32_UPD:
9199	case ARM::VLD3DUPq8_UPD: {
9200	// op: Vd
9201	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
9202	Value \|= (op & UINT64_C(`16`)) << `18`;
9203	Value \|= (op & UINT64_C(`15`)) << `12`;
9204	// op: Rn
9205	op = getAddrMode6DupAddressOpValue(MI, `4`, Fixups, STI);
9206	op &= UINT64_C(`15`);
9207	op <<= `16`;
9208	Value \|= op;
9209	// op: Rm
9210	op = getAddrMode6OffsetOpValue(MI, `6`, Fixups, STI);
9211	op &= UINT64_C(`15`);
9212	Value \|= op;
9213	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9214	break;
9215	}
9216	case ARM::VLD4DUPd16_UPD:
9217	case ARM::VLD4DUPd8_UPD:
9218	case ARM::VLD4DUPq16_UPD:
9219	case ARM::VLD4DUPq8_UPD: {
9220	// op: Vd
9221	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
9222	Value \|= (op & UINT64_C(`16`)) << `18`;
9223	Value \|= (op & UINT64_C(`15`)) << `12`;
9224	// op: Rn
9225	op = getAddrMode6DupAddressOpValue(MI, `5`, Fixups, STI);
9226	Value \|= (op & UINT64_C(`15`)) << `16`;
9227	Value \|= (op & UINT64_C(`16`));
9228	// op: Rm
9229	op = getAddrMode6OffsetOpValue(MI, `7`, Fixups, STI);
9230	op &= UINT64_C(`15`);
9231	Value \|= op;
9232	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9233	break;
9234	}
9235	case ARM::VLD4DUPd32_UPD:
9236	case ARM::VLD4DUPq32_UPD: {
9237	// op: Vd
9238	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
9239	Value \|= (op & UINT64_C(`16`)) << `18`;
9240	Value \|= (op & UINT64_C(`15`)) << `12`;
9241	// op: Rn
9242	op = getAddrMode6DupAddressOpValue(MI, `5`, Fixups, STI);
9243	Value \|= (op & UINT64_C(`15`)) << `16`;
9244	Value \|= (op & UINT64_C(`32`)) << `1`;
9245	Value \|= (op & UINT64_C(`16`));
9246	// op: Rm
9247	op = getAddrMode6OffsetOpValue(MI, `7`, Fixups, STI);
9248	op &= UINT64_C(`15`);
9249	Value \|= op;
9250	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9251	break;
9252	}
9253	case ARM::VLD1LNd32: {
9254	// op: Vd
9255	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
9256	Value \|= (op & UINT64_C(`16`)) << `18`;
9257	Value \|= (op & UINT64_C(`15`)) << `12`;
9258	// op: Rn
9259	op = getAddrMode6OneLane32AddressOpValue(MI, `1`, Fixups, STI);
9260	Value \|= (op & UINT64_C(`15`)) << `16`;
9261	Value \|= (op & UINT64_C(`48`));
9262	// op: lane
9263	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
9264	op &= UINT64_C(`1`);
9265	op <<= `7`;
9266	Value \|= op;
9267	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
9268	break;
9269	}
9270	case ARM::VMOVv16i8:
9271	case ARM::VMOVv1i64:
9272	case ARM::VMOVv2f32:
9273	case ARM::VMOVv2i64:
9274	case ARM::VMOVv4f32:
9275	case ARM::VMOVv8i8: {
9276	// op: Vd
9277	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
9278	Value \|= (op & UINT64_C(`16`)) << `18`;
9279	Value \|= (op & UINT64_C(`15`)) << `12`;
9280	// op: SIMM
9281	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
9282	Value \|= (op & UINT64_C(`128`)) << `17`;
9283	Value \|= (op & UINT64_C(`112`)) << `12`;
9284	Value \|= (op & UINT64_C(`15`));
9285	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9286	break;
9287	}
9288	case ARM::VBICiv2i32:
9289	case ARM::VBICiv4i32:
9290	case ARM::VORRiv2i32:
9291	case ARM::VORRiv4i32: {
9292	// op: Vd
9293	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
9294	Value \|= (op & UINT64_C(`16`)) << `18`;
9295	Value \|= (op & UINT64_C(`15`)) << `12`;
9296	// op: SIMM
9297	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
9298	Value \|= (op & UINT64_C(`128`)) << `17`;
9299	Value \|= (op & UINT64_C(`112`)) << `12`;
9300	Value \|= (op & UINT64_C(`1536`));
9301	Value \|= (op & UINT64_C(`15`));
9302	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9303	break;
9304	}
9305	case ARM::VMOVv2i32:
9306	case ARM::VMOVv4i32:
9307	case ARM::VMVNv2i32:
9308	case ARM::VMVNv4i32: {
9309	// op: Vd
9310	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
9311	Value \|= (op & UINT64_C(`16`)) << `18`;
9312	Value \|= (op & UINT64_C(`15`)) << `12`;
9313	// op: SIMM
9314	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
9315	Value \|= (op & UINT64_C(`128`)) << `17`;
9316	Value \|= (op & UINT64_C(`112`)) << `12`;
9317	Value \|= (op & UINT64_C(`3840`));
9318	Value \|= (op & UINT64_C(`15`));
9319	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9320	break;
9321	}
9322	case ARM::VBICiv4i16:
9323	case ARM::VBICiv8i16:
9324	case ARM::VMOVv4i16:
9325	case ARM::VMOVv8i16:
9326	case ARM::VMVNv4i16:
9327	case ARM::VMVNv8i16:
9328	case ARM::VORRiv4i16:
9329	case ARM::VORRiv8i16: {
9330	// op: Vd
9331	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
9332	Value \|= (op & UINT64_C(`16`)) << `18`;
9333	Value \|= (op & UINT64_C(`15`)) << `12`;
9334	// op: SIMM
9335	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
9336	Value \|= (op & UINT64_C(`128`)) << `17`;
9337	Value \|= (op & UINT64_C(`112`)) << `12`;
9338	Value \|= (op & UINT64_C(`512`));
9339	Value \|= (op & UINT64_C(`15`));
9340	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9341	break;
9342	}
9343	case ARM::VQSHLsiv4i16:
9344	case ARM::VQSHLsiv8i16:
9345	case ARM::VQSHLsuv4i16:
9346	case ARM::VQSHLsuv8i16:
9347	case ARM::VQSHLuiv4i16:
9348	case ARM::VQSHLuiv8i16:
9349	case ARM::VSHLLsv4i32:
9350	case ARM::VSHLLuv4i32:
9351	case ARM::VSHLiv4i16:
9352	case ARM::VSHLiv8i16: {
9353	// op: Vd
9354	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
9355	Value \|= (op & UINT64_C(`16`)) << `18`;
9356	Value \|= (op & UINT64_C(`15`)) << `12`;
9357	// op: Vm
9358	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
9359	Value \|= (op & UINT64_C(`16`)) << `1`;
9360	Value \|= (op & UINT64_C(`15`));
9361	// op: SIMM
9362	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
9363	op &= UINT64_C(`15`);
9364	op <<= `16`;
9365	Value \|= op;
9366	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9367	break;
9368	}
9369	case ARM::VQSHLsiv2i32:
9370	case ARM::VQSHLsiv4i32:
9371	case ARM::VQSHLsuv2i32:
9372	case ARM::VQSHLsuv4i32:
9373	case ARM::VQSHLuiv2i32:
9374	case ARM::VQSHLuiv4i32:
9375	case ARM::VSHLLsv2i64:
9376	case ARM::VSHLLuv2i64:
9377	case ARM::VSHLiv2i32:
9378	case ARM::VSHLiv4i32: {
9379	// op: Vd
9380	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
9381	Value \|= (op & UINT64_C(`16`)) << `18`;
9382	Value \|= (op & UINT64_C(`15`)) << `12`;
9383	// op: Vm
9384	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
9385	Value \|= (op & UINT64_C(`16`)) << `1`;
9386	Value \|= (op & UINT64_C(`15`));
9387	// op: SIMM
9388	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
9389	op &= UINT64_C(`31`);
9390	op <<= `16`;
9391	Value \|= op;
9392	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9393	break;
9394	}
9395	case ARM::VQSHLsiv1i64:
9396	case ARM::VQSHLsiv2i64:
9397	case ARM::VQSHLsuv1i64:
9398	case ARM::VQSHLsuv2i64:
9399	case ARM::VQSHLuiv1i64:
9400	case ARM::VQSHLuiv2i64:
9401	case ARM::VSHLiv1i64:
9402	case ARM::VSHLiv2i64: {
9403	// op: Vd
9404	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
9405	Value \|= (op & UINT64_C(`16`)) << `18`;
9406	Value \|= (op & UINT64_C(`15`)) << `12`;
9407	// op: Vm
9408	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
9409	Value \|= (op & UINT64_C(`16`)) << `1`;
9410	Value \|= (op & UINT64_C(`15`));
9411	// op: SIMM
9412	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
9413	op &= UINT64_C(`63`);
9414	op <<= `16`;
9415	Value \|= op;
9416	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9417	break;
9418	}
9419	case ARM::VQSHLsiv16i8:
9420	case ARM::VQSHLsiv8i8:
9421	case ARM::VQSHLsuv16i8:
9422	case ARM::VQSHLsuv8i8:
9423	case ARM::VQSHLuiv16i8:
9424	case ARM::VQSHLuiv8i8:
9425	case ARM::VSHLLsv8i16:
9426	case ARM::VSHLLuv8i16:
9427	case ARM::VSHLiv16i8:
9428	case ARM::VSHLiv8i8: {
9429	// op: Vd
9430	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
9431	Value \|= (op & UINT64_C(`16`)) << `18`;
9432	Value \|= (op & UINT64_C(`15`)) << `12`;
9433	// op: Vm
9434	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
9435	Value \|= (op & UINT64_C(`16`)) << `1`;
9436	Value \|= (op & UINT64_C(`15`));
9437	// op: SIMM
9438	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
9439	op &= UINT64_C(`7`);
9440	op <<= `16`;
9441	Value \|= op;
9442	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9443	break;
9444	}
9445	case ARM::VCVTf2xsd:
9446	case ARM::VCVTf2xsq:
9447	case ARM::VCVTf2xud:
9448	case ARM::VCVTf2xuq:
9449	case ARM::VCVTh2xsd:
9450	case ARM::VCVTh2xsq:
9451	case ARM::VCVTh2xud:
9452	case ARM::VCVTh2xuq:
9453	case ARM::VCVTxs2fd:
9454	case ARM::VCVTxs2fq:
9455	case ARM::VCVTxs2hd:
9456	case ARM::VCVTxs2hq:
9457	case ARM::VCVTxu2fd:
9458	case ARM::VCVTxu2fq:
9459	case ARM::VCVTxu2hd:
9460	case ARM::VCVTxu2hq: {
9461	// op: Vd
9462	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
9463	Value \|= (op & UINT64_C(`16`)) << `18`;
9464	Value \|= (op & UINT64_C(`15`)) << `12`;
9465	// op: Vm
9466	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
9467	Value \|= (op & UINT64_C(`16`)) << `1`;
9468	Value \|= (op & UINT64_C(`15`));
9469	// op: SIMM
9470	op = getNEONVcvtImm32OpValue(MI, `2`, Fixups, STI);
9471	op &= UINT64_C(`63`);
9472	op <<= `16`;
9473	Value \|= op;
9474	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9475	break;
9476	}
9477	case ARM::VQRSHRNsv4i16:
9478	case ARM::VQRSHRNuv4i16:
9479	case ARM::VQRSHRUNv4i16:
9480	case ARM::VQSHRNsv4i16:
9481	case ARM::VQSHRNuv4i16:
9482	case ARM::VQSHRUNv4i16:
9483	case ARM::VRSHRNv4i16:
9484	case ARM::VRSHRsv4i16:
9485	case ARM::VRSHRsv8i16:
9486	case ARM::VRSHRuv4i16:
9487	case ARM::VRSHRuv8i16:
9488	case ARM::VSHRNv4i16:
9489	case ARM::VSHRsv4i16:
9490	case ARM::VSHRsv8i16:
9491	case ARM::VSHRuv4i16:
9492	case ARM::VSHRuv8i16: {
9493	// op: Vd
9494	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
9495	Value \|= (op & UINT64_C(`16`)) << `18`;
9496	Value \|= (op & UINT64_C(`15`)) << `12`;
9497	// op: Vm
9498	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
9499	Value \|= (op & UINT64_C(`16`)) << `1`;
9500	Value \|= (op & UINT64_C(`15`));
9501	// op: SIMM
9502	op = getShiftRight16Imm(MI, `2`, Fixups, STI);
9503	op &= UINT64_C(`15`);
9504	op <<= `16`;
9505	Value \|= op;
9506	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9507	break;
9508	}
9509	case ARM::VQRSHRNsv2i32:
9510	case ARM::VQRSHRNuv2i32:
9511	case ARM::VQRSHRUNv2i32:
9512	case ARM::VQSHRNsv2i32:
9513	case ARM::VQSHRNuv2i32:
9514	case ARM::VQSHRUNv2i32:
9515	case ARM::VRSHRNv2i32:
9516	case ARM::VRSHRsv2i32:
9517	case ARM::VRSHRsv4i32:
9518	case ARM::VRSHRuv2i32:
9519	case ARM::VRSHRuv4i32:
9520	case ARM::VSHRNv2i32:
9521	case ARM::VSHRsv2i32:
9522	case ARM::VSHRsv4i32:
9523	case ARM::VSHRuv2i32:
9524	case ARM::VSHRuv4i32: {
9525	// op: Vd
9526	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
9527	Value \|= (op & UINT64_C(`16`)) << `18`;
9528	Value \|= (op & UINT64_C(`15`)) << `12`;
9529	// op: Vm
9530	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
9531	Value \|= (op & UINT64_C(`16`)) << `1`;
9532	Value \|= (op & UINT64_C(`15`));
9533	// op: SIMM
9534	op = getShiftRight32Imm(MI, `2`, Fixups, STI);
9535	op &= UINT64_C(`31`);
9536	op <<= `16`;
9537	Value \|= op;
9538	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9539	break;
9540	}
9541	case ARM::VRSHRsv1i64:
9542	case ARM::VRSHRsv2i64:
9543	case ARM::VRSHRuv1i64:
9544	case ARM::VRSHRuv2i64:
9545	case ARM::VSHRsv1i64:
9546	case ARM::VSHRsv2i64:
9547	case ARM::VSHRuv1i64:
9548	case ARM::VSHRuv2i64: {
9549	// op: Vd
9550	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
9551	Value \|= (op & UINT64_C(`16`)) << `18`;
9552	Value \|= (op & UINT64_C(`15`)) << `12`;
9553	// op: Vm
9554	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
9555	Value \|= (op & UINT64_C(`16`)) << `1`;
9556	Value \|= (op & UINT64_C(`15`));
9557	// op: SIMM
9558	op = getShiftRight64Imm(MI, `2`, Fixups, STI);
9559	op &= UINT64_C(`63`);
9560	op <<= `16`;
9561	Value \|= op;
9562	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9563	break;
9564	}
9565	case ARM::VQRSHRNsv8i8:
9566	case ARM::VQRSHRNuv8i8:
9567	case ARM::VQRSHRUNv8i8:
9568	case ARM::VQSHRNsv8i8:
9569	case ARM::VQSHRNuv8i8:
9570	case ARM::VQSHRUNv8i8:
9571	case ARM::VRSHRNv8i8:
9572	case ARM::VRSHRsv16i8:
9573	case ARM::VRSHRsv8i8:
9574	case ARM::VRSHRuv16i8:
9575	case ARM::VRSHRuv8i8:
9576	case ARM::VSHRNv8i8:
9577	case ARM::VSHRsv16i8:
9578	case ARM::VSHRsv8i8:
9579	case ARM::VSHRuv16i8:
9580	case ARM::VSHRuv8i8: {
9581	// op: Vd
9582	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
9583	Value \|= (op & UINT64_C(`16`)) << `18`;
9584	Value \|= (op & UINT64_C(`15`)) << `12`;
9585	// op: Vm
9586	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
9587	Value \|= (op & UINT64_C(`16`)) << `1`;
9588	Value \|= (op & UINT64_C(`15`));
9589	// op: SIMM
9590	op = getShiftRight8Imm(MI, `2`, Fixups, STI);
9591	op &= UINT64_C(`7`);
9592	op <<= `16`;
9593	Value \|= op;
9594	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9595	break;
9596	}
9597	case ARM::VDUPLN32d:
9598	case ARM::VDUPLN32q: {
9599	// op: Vd
9600	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
9601	Value \|= (op & UINT64_C(`16`)) << `18`;
9602	Value \|= (op & UINT64_C(`15`)) << `12`;
9603	// op: Vm
9604	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
9605	Value \|= (op & UINT64_C(`16`)) << `1`;
9606	Value \|= (op & UINT64_C(`15`));
9607	// op: lane
9608	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
9609	op &= UINT64_C(`1`);
9610	op <<= `19`;
9611	Value \|= op;
9612	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9613	break;
9614	}
9615	case ARM::VDUPLN16d:
9616	case ARM::VDUPLN16q: {
9617	// op: Vd
9618	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
9619	Value \|= (op & UINT64_C(`16`)) << `18`;
9620	Value \|= (op & UINT64_C(`15`)) << `12`;
9621	// op: Vm
9622	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
9623	Value \|= (op & UINT64_C(`16`)) << `1`;
9624	Value \|= (op & UINT64_C(`15`));
9625	// op: lane
9626	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
9627	op &= UINT64_C(`3`);
9628	op <<= `18`;
9629	Value \|= op;
9630	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9631	break;
9632	}
9633	case ARM::VDUPLN8d:
9634	case ARM::VDUPLN8q: {
9635	// op: Vd
9636	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
9637	Value \|= (op & UINT64_C(`16`)) << `18`;
9638	Value \|= (op & UINT64_C(`15`)) << `12`;
9639	// op: Vm
9640	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
9641	Value \|= (op & UINT64_C(`16`)) << `1`;
9642	Value \|= (op & UINT64_C(`15`));
9643	// op: lane
9644	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
9645	op &= UINT64_C(`7`);
9646	op <<= `17`;
9647	Value \|= op;
9648	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9649	break;
9650	}
9651	case ARM::AESIMC:
9652	case ARM::AESMC:
9653	case ARM::BF16_VCVT:
9654	case ARM::SHA1H:
9655	case ARM::VABSfd:
9656	case ARM::VABSfq:
9657	case ARM::VABShd:
9658	case ARM::VABShq:
9659	case ARM::VABSv16i8:
9660	case ARM::VABSv2i32:
9661	case ARM::VABSv4i16:
9662	case ARM::VABSv4i32:
9663	case ARM::VABSv8i16:
9664	case ARM::VABSv8i8:
9665	case ARM::VCEQzv16i8:
9666	case ARM::VCEQzv2f32:
9667	case ARM::VCEQzv2i32:
9668	case ARM::VCEQzv4f16:
9669	case ARM::VCEQzv4f32:
9670	case ARM::VCEQzv4i16:
9671	case ARM::VCEQzv4i32:
9672	case ARM::VCEQzv8f16:
9673	case ARM::VCEQzv8i16:
9674	case ARM::VCEQzv8i8:
9675	case ARM::VCGEzv16i8:
9676	case ARM::VCGEzv2f32:
9677	case ARM::VCGEzv2i32:
9678	case ARM::VCGEzv4f16:
9679	case ARM::VCGEzv4f32:
9680	case ARM::VCGEzv4i16:
9681	case ARM::VCGEzv4i32:
9682	case ARM::VCGEzv8f16:
9683	case ARM::VCGEzv8i16:
9684	case ARM::VCGEzv8i8:
9685	case ARM::VCGTzv16i8:
9686	case ARM::VCGTzv2f32:
9687	case ARM::VCGTzv2i32:
9688	case ARM::VCGTzv4f16:
9689	case ARM::VCGTzv4f32:
9690	case ARM::VCGTzv4i16:
9691	case ARM::VCGTzv4i32:
9692	case ARM::VCGTzv8f16:
9693	case ARM::VCGTzv8i16:
9694	case ARM::VCGTzv8i8:
9695	case ARM::VCLEzv16i8:
9696	case ARM::VCLEzv2f32:
9697	case ARM::VCLEzv2i32:
9698	case ARM::VCLEzv4f16:
9699	case ARM::VCLEzv4f32:
9700	case ARM::VCLEzv4i16:
9701	case ARM::VCLEzv4i32:
9702	case ARM::VCLEzv8f16:
9703	case ARM::VCLEzv8i16:
9704	case ARM::VCLEzv8i8:
9705	case ARM::VCLSv16i8:
9706	case ARM::VCLSv2i32:
9707	case ARM::VCLSv4i16:
9708	case ARM::VCLSv4i32:
9709	case ARM::VCLSv8i16:
9710	case ARM::VCLSv8i8:
9711	case ARM::VCLTzv16i8:
9712	case ARM::VCLTzv2f32:
9713	case ARM::VCLTzv2i32:
9714	case ARM::VCLTzv4f16:
9715	case ARM::VCLTzv4f32:
9716	case ARM::VCLTzv4i16:
9717	case ARM::VCLTzv4i32:
9718	case ARM::VCLTzv8f16:
9719	case ARM::VCLTzv8i16:
9720	case ARM::VCLTzv8i8:
9721	case ARM::VCLZv16i8:
9722	case ARM::VCLZv2i32:
9723	case ARM::VCLZv4i16:
9724	case ARM::VCLZv4i32:
9725	case ARM::VCLZv8i16:
9726	case ARM::VCLZv8i8:
9727	case ARM::VCNTd:
9728	case ARM::VCNTq:
9729	case ARM::VCVTf2h:
9730	case ARM::VCVTf2sd:
9731	case ARM::VCVTf2sq:
9732	case ARM::VCVTf2ud:
9733	case ARM::VCVTf2uq:
9734	case ARM::VCVTh2f:
9735	case ARM::VCVTh2sd:
9736	case ARM::VCVTh2sq:
9737	case ARM::VCVTh2ud:
9738	case ARM::VCVTh2uq:
9739	case ARM::VCVTs2fd:
9740	case ARM::VCVTs2fq:
9741	case ARM::VCVTs2hd:
9742	case ARM::VCVTs2hq:
9743	case ARM::VCVTu2fd:
9744	case ARM::VCVTu2fq:
9745	case ARM::VCVTu2hd:
9746	case ARM::VCVTu2hq:
9747	case ARM::VMOVLsv2i64:
9748	case ARM::VMOVLsv4i32:
9749	case ARM::VMOVLsv8i16:
9750	case ARM::VMOVLuv2i64:
9751	case ARM::VMOVLuv4i32:
9752	case ARM::VMOVLuv8i16:
9753	case ARM::VMOVNv2i32:
9754	case ARM::VMOVNv4i16:
9755	case ARM::VMOVNv8i8:
9756	case ARM::VMVNd:
9757	case ARM::VMVNq:
9758	case ARM::VNEGf32q:
9759	case ARM::VNEGfd:
9760	case ARM::VNEGhd:
9761	case ARM::VNEGhq:
9762	case ARM::VNEGs16d:
9763	case ARM::VNEGs16q:
9764	case ARM::VNEGs32d:
9765	case ARM::VNEGs32q:
9766	case ARM::VNEGs8d:
9767	case ARM::VNEGs8q:
9768	case ARM::VPADDLsv16i8:
9769	case ARM::VPADDLsv2i32:
9770	case ARM::VPADDLsv4i16:
9771	case ARM::VPADDLsv4i32:
9772	case ARM::VPADDLsv8i16:
9773	case ARM::VPADDLsv8i8:
9774	case ARM::VPADDLuv16i8:
9775	case ARM::VPADDLuv2i32:
9776	case ARM::VPADDLuv4i16:
9777	case ARM::VPADDLuv4i32:
9778	case ARM::VPADDLuv8i16:
9779	case ARM::VPADDLuv8i8:
9780	case ARM::VQABSv16i8:
9781	case ARM::VQABSv2i32:
9782	case ARM::VQABSv4i16:
9783	case ARM::VQABSv4i32:
9784	case ARM::VQABSv8i16:
9785	case ARM::VQABSv8i8:
9786	case ARM::VQMOVNsuv2i32:
9787	case ARM::VQMOVNsuv4i16:
9788	case ARM::VQMOVNsuv8i8:
9789	case ARM::VQMOVNsv2i32:
9790	case ARM::VQMOVNsv4i16:
9791	case ARM::VQMOVNsv8i8:
9792	case ARM::VQMOVNuv2i32:
9793	case ARM::VQMOVNuv4i16:
9794	case ARM::VQMOVNuv8i8:
9795	case ARM::VQNEGv16i8:
9796	case ARM::VQNEGv2i32:
9797	case ARM::VQNEGv4i16:
9798	case ARM::VQNEGv4i32:
9799	case ARM::VQNEGv8i16:
9800	case ARM::VQNEGv8i8:
9801	case ARM::VRECPEd:
9802	case ARM::VRECPEfd:
9803	case ARM::VRECPEfq:
9804	case ARM::VRECPEhd:
9805	case ARM::VRECPEhq:
9806	case ARM::VRECPEq:
9807	case ARM::VREV16d8:
9808	case ARM::VREV16q8:
9809	case ARM::VREV32d16:
9810	case ARM::VREV32d8:
9811	case ARM::VREV32q16:
9812	case ARM::VREV32q8:
9813	case ARM::VREV64d16:
9814	case ARM::VREV64d32:
9815	case ARM::VREV64d8:
9816	case ARM::VREV64q16:
9817	case ARM::VREV64q32:
9818	case ARM::VREV64q8:
9819	case ARM::VRSQRTEd:
9820	case ARM::VRSQRTEfd:
9821	case ARM::VRSQRTEfq:
9822	case ARM::VRSQRTEhd:
9823	case ARM::VRSQRTEhq:
9824	case ARM::VRSQRTEq:
9825	case ARM::VSHLLi16:
9826	case ARM::VSHLLi32:
9827	case ARM::VSHLLi8:
9828	case ARM::VSWPd:
9829	case ARM::VSWPq:
9830	case ARM::VTRNd16:
9831	case ARM::VTRNd32:
9832	case ARM::VTRNd8:
9833	case ARM::VTRNq16:
9834	case ARM::VTRNq32:
9835	case ARM::VTRNq8:
9836	case ARM::VUZPd16:
9837	case ARM::VUZPd8:
9838	case ARM::VUZPq16:
9839	case ARM::VUZPq32:
9840	case ARM::VUZPq8:
9841	case ARM::VZIPd16:
9842	case ARM::VZIPd8:
9843	case ARM::VZIPq16:
9844	case ARM::VZIPq32:
9845	case ARM::VZIPq8: {
9846	// op: Vd
9847	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
9848	Value \|= (op & UINT64_C(`16`)) << `18`;
9849	Value \|= (op & UINT64_C(`15`)) << `12`;
9850	// op: Vm
9851	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
9852	Value \|= (op & UINT64_C(`16`)) << `1`;
9853	Value \|= (op & UINT64_C(`15`));
9854	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9855	break;
9856	}
9857	case ARM::VCVTANSDf:
9858	case ARM::VCVTANSDh:
9859	case ARM::VCVTANSQf:
9860	case ARM::VCVTANSQh:
9861	case ARM::VCVTANUDf:
9862	case ARM::VCVTANUDh:
9863	case ARM::VCVTANUQf:
9864	case ARM::VCVTANUQh:
9865	case ARM::VCVTMNSDf:
9866	case ARM::VCVTMNSDh:
9867	case ARM::VCVTMNSQf:
9868	case ARM::VCVTMNSQh:
9869	case ARM::VCVTMNUDf:
9870	case ARM::VCVTMNUDh:
9871	case ARM::VCVTMNUQf:
9872	case ARM::VCVTMNUQh:
9873	case ARM::VCVTNNSDf:
9874	case ARM::VCVTNNSDh:
9875	case ARM::VCVTNNSQf:
9876	case ARM::VCVTNNSQh:
9877	case ARM::VCVTNNUDf:
9878	case ARM::VCVTNNUDh:
9879	case ARM::VCVTNNUQf:
9880	case ARM::VCVTNNUQh:
9881	case ARM::VCVTPNSDf:
9882	case ARM::VCVTPNSDh:
9883	case ARM::VCVTPNSQf:
9884	case ARM::VCVTPNSQh:
9885	case ARM::VCVTPNUDf:
9886	case ARM::VCVTPNUDh:
9887	case ARM::VCVTPNUQf:
9888	case ARM::VCVTPNUQh:
9889	case ARM::VRINTANDf:
9890	case ARM::VRINTANDh:
9891	case ARM::VRINTANQf:
9892	case ARM::VRINTANQh:
9893	case ARM::VRINTMNDf:
9894	case ARM::VRINTMNDh:
9895	case ARM::VRINTMNQf:
9896	case ARM::VRINTMNQh:
9897	case ARM::VRINTNNDf:
9898	case ARM::VRINTNNDh:
9899	case ARM::VRINTNNQf:
9900	case ARM::VRINTNNQh:
9901	case ARM::VRINTPNDf:
9902	case ARM::VRINTPNDh:
9903	case ARM::VRINTPNQf:
9904	case ARM::VRINTPNQh:
9905	case ARM::VRINTXNDf:
9906	case ARM::VRINTXNDh:
9907	case ARM::VRINTXNQf:
9908	case ARM::VRINTXNQh:
9909	case ARM::VRINTZNDf:
9910	case ARM::VRINTZNDh:
9911	case ARM::VRINTZNQf:
9912	case ARM::VRINTZNQh: {
9913	// op: Vd
9914	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
9915	Value \|= (op & UINT64_C(`16`)) << `18`;
9916	Value \|= (op & UINT64_C(`15`)) << `12`;
9917	// op: Vm
9918	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
9919	Value \|= (op & UINT64_C(`16`)) << `1`;
9920	Value \|= (op & UINT64_C(`15`));
9921	Value = NEONThumb2V8PostEncoder(MI, Value, STI);
9922	break;
9923	}
9924	case ARM::VSLIv4i16:
9925	case ARM::VSLIv8i16: {
9926	// op: Vd
9927	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
9928	Value \|= (op & UINT64_C(`16`)) << `18`;
9929	Value \|= (op & UINT64_C(`15`)) << `12`;
9930	// op: Vm
9931	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
9932	Value \|= (op & UINT64_C(`16`)) << `1`;
9933	Value \|= (op & UINT64_C(`15`));
9934	// op: SIMM
9935	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
9936	op &= UINT64_C(`15`);
9937	op <<= `16`;
9938	Value \|= op;
9939	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9940	break;
9941	}
9942	case ARM::VSLIv2i32:
9943	case ARM::VSLIv4i32: {
9944	// op: Vd
9945	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
9946	Value \|= (op & UINT64_C(`16`)) << `18`;
9947	Value \|= (op & UINT64_C(`15`)) << `12`;
9948	// op: Vm
9949	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
9950	Value \|= (op & UINT64_C(`16`)) << `1`;
9951	Value \|= (op & UINT64_C(`15`));
9952	// op: SIMM
9953	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
9954	op &= UINT64_C(`31`);
9955	op <<= `16`;
9956	Value \|= op;
9957	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9958	break;
9959	}
9960	case ARM::VSLIv1i64:
9961	case ARM::VSLIv2i64: {
9962	// op: Vd
9963	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
9964	Value \|= (op & UINT64_C(`16`)) << `18`;
9965	Value \|= (op & UINT64_C(`15`)) << `12`;
9966	// op: Vm
9967	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
9968	Value \|= (op & UINT64_C(`16`)) << `1`;
9969	Value \|= (op & UINT64_C(`15`));
9970	// op: SIMM
9971	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
9972	op &= UINT64_C(`63`);
9973	op <<= `16`;
9974	Value \|= op;
9975	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9976	break;
9977	}
9978	case ARM::VSLIv16i8:
9979	case ARM::VSLIv8i8: {
9980	// op: Vd
9981	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
9982	Value \|= (op & UINT64_C(`16`)) << `18`;
9983	Value \|= (op & UINT64_C(`15`)) << `12`;
9984	// op: Vm
9985	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
9986	Value \|= (op & UINT64_C(`16`)) << `1`;
9987	Value \|= (op & UINT64_C(`15`));
9988	// op: SIMM
9989	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
9990	op &= UINT64_C(`7`);
9991	op <<= `16`;
9992	Value \|= op;
9993	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
9994	break;
9995	}
9996	case ARM::VRSRAsv4i16:
9997	case ARM::VRSRAsv8i16:
9998	case ARM::VRSRAuv4i16:
9999	case ARM::VRSRAuv8i16:
10000	case ARM::VSRAsv4i16:
10001	case ARM::VSRAsv8i16:
10002	case ARM::VSRAuv4i16:
10003	case ARM::VSRAuv8i16:
10004	case ARM::VSRIv4i16:
10005	case ARM::VSRIv8i16: {
10006	// op: Vd
10007	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
10008	Value \|= (op & UINT64_C(`16`)) << `18`;
10009	Value \|= (op & UINT64_C(`15`)) << `12`;
10010	// op: Vm
10011	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
10012	Value \|= (op & UINT64_C(`16`)) << `1`;
10013	Value \|= (op & UINT64_C(`15`));
10014	// op: SIMM
10015	op = getShiftRight16Imm(MI, `3`, Fixups, STI);
10016	op &= UINT64_C(`15`);
10017	op <<= `16`;
10018	Value \|= op;
10019	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
10020	break;
10021	}
10022	case ARM::VRSRAsv2i32:
10023	case ARM::VRSRAsv4i32:
10024	case ARM::VRSRAuv2i32:
10025	case ARM::VRSRAuv4i32:
10026	case ARM::VSRAsv2i32:
10027	case ARM::VSRAsv4i32:
10028	case ARM::VSRAuv2i32:
10029	case ARM::VSRAuv4i32:
10030	case ARM::VSRIv2i32:
10031	case ARM::VSRIv4i32: {
10032	// op: Vd
10033	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
10034	Value \|= (op & UINT64_C(`16`)) << `18`;
10035	Value \|= (op & UINT64_C(`15`)) << `12`;
10036	// op: Vm
10037	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
10038	Value \|= (op & UINT64_C(`16`)) << `1`;
10039	Value \|= (op & UINT64_C(`15`));
10040	// op: SIMM
10041	op = getShiftRight32Imm(MI, `3`, Fixups, STI);
10042	op &= UINT64_C(`31`);
10043	op <<= `16`;
10044	Value \|= op;
10045	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
10046	break;
10047	}
10048	case ARM::VRSRAsv1i64:
10049	case ARM::VRSRAsv2i64:
10050	case ARM::VRSRAuv1i64:
10051	case ARM::VRSRAuv2i64:
10052	case ARM::VSRAsv1i64:
10053	case ARM::VSRAsv2i64:
10054	case ARM::VSRAuv1i64:
10055	case ARM::VSRAuv2i64:
10056	case ARM::VSRIv1i64:
10057	case ARM::VSRIv2i64: {
10058	// op: Vd
10059	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
10060	Value \|= (op & UINT64_C(`16`)) << `18`;
10061	Value \|= (op & UINT64_C(`15`)) << `12`;
10062	// op: Vm
10063	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
10064	Value \|= (op & UINT64_C(`16`)) << `1`;
10065	Value \|= (op & UINT64_C(`15`));
10066	// op: SIMM
10067	op = getShiftRight64Imm(MI, `3`, Fixups, STI);
10068	op &= UINT64_C(`63`);
10069	op <<= `16`;
10070	Value \|= op;
10071	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
10072	break;
10073	}
10074	case ARM::VRSRAsv16i8:
10075	case ARM::VRSRAsv8i8:
10076	case ARM::VRSRAuv16i8:
10077	case ARM::VRSRAuv8i8:
10078	case ARM::VSRAsv16i8:
10079	case ARM::VSRAsv8i8:
10080	case ARM::VSRAuv16i8:
10081	case ARM::VSRAuv8i8:
10082	case ARM::VSRIv16i8:
10083	case ARM::VSRIv8i8: {
10084	// op: Vd
10085	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
10086	Value \|= (op & UINT64_C(`16`)) << `18`;
10087	Value \|= (op & UINT64_C(`15`)) << `12`;
10088	// op: Vm
10089	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
10090	Value \|= (op & UINT64_C(`16`)) << `1`;
10091	Value \|= (op & UINT64_C(`15`));
10092	// op: SIMM
10093	op = getShiftRight8Imm(MI, `3`, Fixups, STI);
10094	op &= UINT64_C(`7`);
10095	op <<= `16`;
10096	Value \|= op;
10097	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
10098	break;
10099	}
10100	case ARM::AESD:
10101	case ARM::AESE:
10102	case ARM::SHA1SU1:
10103	case ARM::SHA256SU0:
10104	case ARM::VPADALsv16i8:
10105	case ARM::VPADALsv2i32:
10106	case ARM::VPADALsv4i16:
10107	case ARM::VPADALsv4i32:
10108	case ARM::VPADALsv8i16:
10109	case ARM::VPADALsv8i8:
10110	case ARM::VPADALuv16i8:
10111	case ARM::VPADALuv2i32:
10112	case ARM::VPADALuv4i16:
10113	case ARM::VPADALuv4i32:
10114	case ARM::VPADALuv8i16:
10115	case ARM::VPADALuv8i8: {
10116	// op: Vd
10117	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
10118	Value \|= (op & UINT64_C(`16`)) << `18`;
10119	Value \|= (op & UINT64_C(`15`)) << `12`;
10120	// op: Vm
10121	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
10122	Value \|= (op & UINT64_C(`16`)) << `1`;
10123	Value \|= (op & UINT64_C(`15`));
10124	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
10125	break;
10126	}
10127	case ARM::VFMALQ:
10128	case ARM::VFMSLQ: {
10129	// op: Vd
10130	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
10131	Value \|= (op & UINT64_C(`16`)) << `18`;
10132	Value \|= (op & UINT64_C(`15`)) << `12`;
10133	// op: Vn
10134	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
10135	Value \|= (op & UINT64_C(`15`)) << `16`;
10136	Value \|= (op & UINT64_C(`16`)) << `3`;
10137	// op: Vm
10138	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
10139	Value \|= (op & UINT64_C(`16`)) << `1`;
10140	Value \|= (op & UINT64_C(`15`));
10141	break;
10142	}
10143	case ARM::VEXTd32: {
10144	// op: Vd
10145	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
10146	Value \|= (op & UINT64_C(`16`)) << `18`;
10147	Value \|= (op & UINT64_C(`15`)) << `12`;
10148	// op: Vn
10149	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
10150	Value \|= (op & UINT64_C(`15`)) << `16`;
10151	Value \|= (op & UINT64_C(`16`)) << `3`;
10152	// op: Vm
10153	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
10154	Value \|= (op & UINT64_C(`16`)) << `1`;
10155	Value \|= (op & UINT64_C(`15`));
10156	// op: index
10157	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
10158	op &= UINT64_C(`1`);
10159	op <<= `10`;
10160	Value \|= op;
10161	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
10162	break;
10163	}
10164	case ARM::VEXTq64: {
10165	// op: Vd
10166	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
10167	Value \|= (op & UINT64_C(`16`)) << `18`;
10168	Value \|= (op & UINT64_C(`15`)) << `12`;
10169	// op: Vn
10170	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
10171	Value \|= (op & UINT64_C(`15`)) << `16`;
10172	Value \|= (op & UINT64_C(`16`)) << `3`;
10173	// op: Vm
10174	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
10175	Value \|= (op & UINT64_C(`16`)) << `1`;
10176	Value \|= (op & UINT64_C(`15`));
10177	// op: index
10178	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
10179	op &= UINT64_C(`1`);
10180	op <<= `11`;
10181	Value \|= op;
10182	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
10183	break;
10184	}
10185	case ARM::VEXTq8: {
10186	// op: Vd
10187	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
10188	Value \|= (op & UINT64_C(`16`)) << `18`;
10189	Value \|= (op & UINT64_C(`15`)) << `12`;
10190	// op: Vn
10191	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
10192	Value \|= (op & UINT64_C(`15`)) << `16`;
10193	Value \|= (op & UINT64_C(`16`)) << `3`;
10194	// op: Vm
10195	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
10196	Value \|= (op & UINT64_C(`16`)) << `1`;
10197	Value \|= (op & UINT64_C(`15`));
10198	// op: index
10199	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
10200	op &= UINT64_C(`15`);
10201	op <<= `8`;
10202	Value \|= op;
10203	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
10204	break;
10205	}
10206	case ARM::VEXTq32: {
10207	// op: Vd
10208	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
10209	Value \|= (op & UINT64_C(`16`)) << `18`;
10210	Value \|= (op & UINT64_C(`15`)) << `12`;
10211	// op: Vn
10212	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
10213	Value \|= (op & UINT64_C(`15`)) << `16`;
10214	Value \|= (op & UINT64_C(`16`)) << `3`;
10215	// op: Vm
10216	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
10217	Value \|= (op & UINT64_C(`16`)) << `1`;
10218	Value \|= (op & UINT64_C(`15`));
10219	// op: index
10220	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
10221	op &= UINT64_C(`3`);
10222	op <<= `10`;
10223	Value \|= op;
10224	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
10225	break;
10226	}
10227	case ARM::VEXTd16: {
10228	// op: Vd
10229	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
10230	Value \|= (op & UINT64_C(`16`)) << `18`;
10231	Value \|= (op & UINT64_C(`15`)) << `12`;
10232	// op: Vn
10233	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
10234	Value \|= (op & UINT64_C(`15`)) << `16`;
10235	Value \|= (op & UINT64_C(`16`)) << `3`;
10236	// op: Vm
10237	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
10238	Value \|= (op & UINT64_C(`16`)) << `1`;
10239	Value \|= (op & UINT64_C(`15`));
10240	// op: index
10241	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
10242	op &= UINT64_C(`3`);
10243	op <<= `9`;
10244	Value \|= op;
10245	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
10246	break;
10247	}
10248	case ARM::VEXTd8: {
10249	// op: Vd
10250	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
10251	Value \|= (op & UINT64_C(`16`)) << `18`;
10252	Value \|= (op & UINT64_C(`15`)) << `12`;
10253	// op: Vn
10254	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
10255	Value \|= (op & UINT64_C(`15`)) << `16`;
10256	Value \|= (op & UINT64_C(`16`)) << `3`;
10257	// op: Vm
10258	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
10259	Value \|= (op & UINT64_C(`16`)) << `1`;
10260	Value \|= (op & UINT64_C(`15`));
10261	// op: index
10262	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
10263	op &= UINT64_C(`7`);
10264	op <<= `8`;
10265	Value \|= op;
10266	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
10267	break;
10268	}
10269	case ARM::VEXTq16: {
10270	// op: Vd
10271	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
10272	Value \|= (op & UINT64_C(`16`)) << `18`;
10273	Value \|= (op & UINT64_C(`15`)) << `12`;
10274	// op: Vn
10275	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
10276	Value \|= (op & UINT64_C(`15`)) << `16`;
10277	Value \|= (op & UINT64_C(`16`)) << `3`;
10278	// op: Vm
10279	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
10280	Value \|= (op & UINT64_C(`16`)) << `1`;
10281	Value \|= (op & UINT64_C(`15`));
10282	// op: index
10283	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
10284	op &= UINT64_C(`7`);
10285	op <<= `9`;
10286	Value \|= op;
10287	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
10288	break;
10289	}
10290	case ARM::VCADDv2f32:
10291	case ARM::VCADDv4f16:
10292	case ARM::VCADDv4f32:
10293	case ARM::VCADDv8f16: {
10294	// op: Vd
10295	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
10296	Value \|= (op & UINT64_C(`16`)) << `18`;
10297	Value \|= (op & UINT64_C(`15`)) << `12`;
10298	// op: Vn
10299	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
10300	Value \|= (op & UINT64_C(`15`)) << `16`;
10301	Value \|= (op & UINT64_C(`16`)) << `3`;
10302	// op: Vm
10303	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
10304	Value \|= (op & UINT64_C(`16`)) << `1`;
10305	Value \|= (op & UINT64_C(`15`));
10306	// op: rot
10307	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
10308	op &= UINT64_C(`1`);
10309	op <<= `24`;
10310	Value \|= op;
10311	break;
10312	}
10313	case ARM::VABDLsv2i64:
10314	case ARM::VABDLsv4i32:
10315	case ARM::VABDLsv8i16:
10316	case ARM::VABDLuv2i64:
10317	case ARM::VABDLuv4i32:
10318	case ARM::VABDLuv8i16:
10319	case ARM::VABDfd:
10320	case ARM::VABDfq:
10321	case ARM::VABDhd:
10322	case ARM::VABDhq:
10323	case ARM::VABDsv16i8:
10324	case ARM::VABDsv2i32:
10325	case ARM::VABDsv4i16:
10326	case ARM::VABDsv4i32:
10327	case ARM::VABDsv8i16:
10328	case ARM::VABDsv8i8:
10329	case ARM::VABDuv16i8:
10330	case ARM::VABDuv2i32:
10331	case ARM::VABDuv4i16:
10332	case ARM::VABDuv4i32:
10333	case ARM::VABDuv8i16:
10334	case ARM::VABDuv8i8:
10335	case ARM::VACGEfd:
10336	case ARM::VACGEfq:
10337	case ARM::VACGEhd:
10338	case ARM::VACGEhq:
10339	case ARM::VACGTfd:
10340	case ARM::VACGTfq:
10341	case ARM::VACGThd:
10342	case ARM::VACGThq:
10343	case ARM::VADDHNv2i32:
10344	case ARM::VADDHNv4i16:
10345	case ARM::VADDHNv8i8:
10346	case ARM::VADDLsv2i64:
10347	case ARM::VADDLsv4i32:
10348	case ARM::VADDLsv8i16:
10349	case ARM::VADDLuv2i64:
10350	case ARM::VADDLuv4i32:
10351	case ARM::VADDLuv8i16:
10352	case ARM::VADDWsv2i64:
10353	case ARM::VADDWsv4i32:
10354	case ARM::VADDWsv8i16:
10355	case ARM::VADDWuv2i64:
10356	case ARM::VADDWuv4i32:
10357	case ARM::VADDWuv8i16:
10358	case ARM::VADDfd:
10359	case ARM::VADDfq:
10360	case ARM::VADDhd:
10361	case ARM::VADDhq:
10362	case ARM::VADDv16i8:
10363	case ARM::VADDv1i64:
10364	case ARM::VADDv2i32:
10365	case ARM::VADDv2i64:
10366	case ARM::VADDv4i16:
10367	case ARM::VADDv4i32:
10368	case ARM::VADDv8i16:
10369	case ARM::VADDv8i8:
10370	case ARM::VANDd:
10371	case ARM::VANDq:
10372	case ARM::VBICd:
10373	case ARM::VBICq:
10374	case ARM::VCEQfd:
10375	case ARM::VCEQfq:
10376	case ARM::VCEQhd:
10377	case ARM::VCEQhq:
10378	case ARM::VCEQv16i8:
10379	case ARM::VCEQv2i32:
10380	case ARM::VCEQv4i16:
10381	case ARM::VCEQv4i32:
10382	case ARM::VCEQv8i16:
10383	case ARM::VCEQv8i8:
10384	case ARM::VCGEfd:
10385	case ARM::VCGEfq:
10386	case ARM::VCGEhd:
10387	case ARM::VCGEhq:
10388	case ARM::VCGEsv16i8:
10389	case ARM::VCGEsv2i32:
10390	case ARM::VCGEsv4i16:
10391	case ARM::VCGEsv4i32:
10392	case ARM::VCGEsv8i16:
10393	case ARM::VCGEsv8i8:
10394	case ARM::VCGEuv16i8:
10395	case ARM::VCGEuv2i32:
10396	case ARM::VCGEuv4i16:
10397	case ARM::VCGEuv4i32:
10398	case ARM::VCGEuv8i16:
10399	case ARM::VCGEuv8i8:
10400	case ARM::VCGTfd:
10401	case ARM::VCGTfq:
10402	case ARM::VCGThd:
10403	case ARM::VCGThq:
10404	case ARM::VCGTsv16i8:
10405	case ARM::VCGTsv2i32:
10406	case ARM::VCGTsv4i16:
10407	case ARM::VCGTsv4i32:
10408	case ARM::VCGTsv8i16:
10409	case ARM::VCGTsv8i8:
10410	case ARM::VCGTuv16i8:
10411	case ARM::VCGTuv2i32:
10412	case ARM::VCGTuv4i16:
10413	case ARM::VCGTuv4i32:
10414	case ARM::VCGTuv8i16:
10415	case ARM::VCGTuv8i8:
10416	case ARM::VEORd:
10417	case ARM::VEORq:
10418	case ARM::VHADDsv16i8:
10419	case ARM::VHADDsv2i32:
10420	case ARM::VHADDsv4i16:
10421	case ARM::VHADDsv4i32:
10422	case ARM::VHADDsv8i16:
10423	case ARM::VHADDsv8i8:
10424	case ARM::VHADDuv16i8:
10425	case ARM::VHADDuv2i32:
10426	case ARM::VHADDuv4i16:
10427	case ARM::VHADDuv4i32:
10428	case ARM::VHADDuv8i16:
10429	case ARM::VHADDuv8i8:
10430	case ARM::VHSUBsv16i8:
10431	case ARM::VHSUBsv2i32:
10432	case ARM::VHSUBsv4i16:
10433	case ARM::VHSUBsv4i32:
10434	case ARM::VHSUBsv8i16:
10435	case ARM::VHSUBsv8i8:
10436	case ARM::VHSUBuv16i8:
10437	case ARM::VHSUBuv2i32:
10438	case ARM::VHSUBuv4i16:
10439	case ARM::VHSUBuv4i32:
10440	case ARM::VHSUBuv8i16:
10441	case ARM::VHSUBuv8i8:
10442	case ARM::VMAXfd:
10443	case ARM::VMAXfq:
10444	case ARM::VMAXhd:
10445	case ARM::VMAXhq:
10446	case ARM::VMAXsv16i8:
10447	case ARM::VMAXsv2i32:
10448	case ARM::VMAXsv4i16:
10449	case ARM::VMAXsv4i32:
10450	case ARM::VMAXsv8i16:
10451	case ARM::VMAXsv8i8:
10452	case ARM::VMAXuv16i8:
10453	case ARM::VMAXuv2i32:
10454	case ARM::VMAXuv4i16:
10455	case ARM::VMAXuv4i32:
10456	case ARM::VMAXuv8i16:
10457	case ARM::VMAXuv8i8:
10458	case ARM::VMINfd:
10459	case ARM::VMINfq:
10460	case ARM::VMINhd:
10461	case ARM::VMINhq:
10462	case ARM::VMINsv16i8:
10463	case ARM::VMINsv2i32:
10464	case ARM::VMINsv4i16:
10465	case ARM::VMINsv4i32:
10466	case ARM::VMINsv8i16:
10467	case ARM::VMINsv8i8:
10468	case ARM::VMINuv16i8:
10469	case ARM::VMINuv2i32:
10470	case ARM::VMINuv4i16:
10471	case ARM::VMINuv4i32:
10472	case ARM::VMINuv8i16:
10473	case ARM::VMINuv8i8:
10474	case ARM::VMULLp64:
10475	case ARM::VMULLp8:
10476	case ARM::VMULLsv2i64:
10477	case ARM::VMULLsv4i32:
10478	case ARM::VMULLsv8i16:
10479	case ARM::VMULLuv2i64:
10480	case ARM::VMULLuv4i32:
10481	case ARM::VMULLuv8i16:
10482	case ARM::VMULfd:
10483	case ARM::VMULfq:
10484	case ARM::VMULhd:
10485	case ARM::VMULhq:
10486	case ARM::VMULpd:
10487	case ARM::VMULpq:
10488	case ARM::VMULv16i8:
10489	case ARM::VMULv2i32:
10490	case ARM::VMULv4i16:
10491	case ARM::VMULv4i32:
10492	case ARM::VMULv8i16:
10493	case ARM::VMULv8i8:
10494	case ARM::VORNd:
10495	case ARM::VORNq:
10496	case ARM::VORRd:
10497	case ARM::VORRq:
10498	case ARM::VPADDf:
10499	case ARM::VPADDh:
10500	case ARM::VPADDi16:
10501	case ARM::VPADDi32:
10502	case ARM::VPADDi8:
10503	case ARM::VPMAXf:
10504	case ARM::VPMAXh:
10505	case ARM::VPMAXs16:
10506	case ARM::VPMAXs32:
10507	case ARM::VPMAXs8:
10508	case ARM::VPMAXu16:
10509	case ARM::VPMAXu32:
10510	case ARM::VPMAXu8:
10511	case ARM::VPMINf:
10512	case ARM::VPMINh:
10513	case ARM::VPMINs16:
10514	case ARM::VPMINs32:
10515	case ARM::VPMINs8:
10516	case ARM::VPMINu16:
10517	case ARM::VPMINu32:
10518	case ARM::VPMINu8:
10519	case ARM::VQADDsv16i8:
10520	case ARM::VQADDsv1i64:
10521	case ARM::VQADDsv2i32:
10522	case ARM::VQADDsv2i64:
10523	case ARM::VQADDsv4i16:
10524	case ARM::VQADDsv4i32:
10525	case ARM::VQADDsv8i16:
10526	case ARM::VQADDsv8i8:
10527	case ARM::VQADDuv16i8:
10528	case ARM::VQADDuv1i64:
10529	case ARM::VQADDuv2i32:
10530	case ARM::VQADDuv2i64:
10531	case ARM::VQADDuv4i16:
10532	case ARM::VQADDuv4i32:
10533	case ARM::VQADDuv8i16:
10534	case ARM::VQADDuv8i8:
10535	case ARM::VQDMULHv2i32:
10536	case ARM::VQDMULHv4i16:
10537	case ARM::VQDMULHv4i32:
10538	case ARM::VQDMULHv8i16:
10539	case ARM::VQDMULLv2i64:
10540	case ARM::VQDMULLv4i32:
10541	case ARM::VQRDMULHv2i32:
10542	case ARM::VQRDMULHv4i16:
10543	case ARM::VQRDMULHv4i32:
10544	case ARM::VQRDMULHv8i16:
10545	case ARM::VQSUBsv16i8:
10546	case ARM::VQSUBsv1i64:
10547	case ARM::VQSUBsv2i32:
10548	case ARM::VQSUBsv2i64:
10549	case ARM::VQSUBsv4i16:
10550	case ARM::VQSUBsv4i32:
10551	case ARM::VQSUBsv8i16:
10552	case ARM::VQSUBsv8i8:
10553	case ARM::VQSUBuv16i8:
10554	case ARM::VQSUBuv1i64:
10555	case ARM::VQSUBuv2i32:
10556	case ARM::VQSUBuv2i64:
10557	case ARM::VQSUBuv4i16:
10558	case ARM::VQSUBuv4i32:
10559	case ARM::VQSUBuv8i16:
10560	case ARM::VQSUBuv8i8:
10561	case ARM::VRADDHNv2i32:
10562	case ARM::VRADDHNv4i16:
10563	case ARM::VRADDHNv8i8:
10564	case ARM::VRECPSfd:
10565	case ARM::VRECPSfq:
10566	case ARM::VRECPShd:
10567	case ARM::VRECPShq:
10568	case ARM::VRHADDsv16i8:
10569	case ARM::VRHADDsv2i32:
10570	case ARM::VRHADDsv4i16:
10571	case ARM::VRHADDsv4i32:
10572	case ARM::VRHADDsv8i16:
10573	case ARM::VRHADDsv8i8:
10574	case ARM::VRHADDuv16i8:
10575	case ARM::VRHADDuv2i32:
10576	case ARM::VRHADDuv4i16:
10577	case ARM::VRHADDuv4i32:
10578	case ARM::VRHADDuv8i16:
10579	case ARM::VRHADDuv8i8:
10580	case ARM::VRSQRTSfd:
10581	case ARM::VRSQRTSfq:
10582	case ARM::VRSQRTShd:
10583	case ARM::VRSQRTShq:
10584	case ARM::VRSUBHNv2i32:
10585	case ARM::VRSUBHNv4i16:
10586	case ARM::VRSUBHNv8i8:
10587	case ARM::VSUBHNv2i32:
10588	case ARM::VSUBHNv4i16:
10589	case ARM::VSUBHNv8i8:
10590	case ARM::VSUBLsv2i64:
10591	case ARM::VSUBLsv4i32:
10592	case ARM::VSUBLsv8i16:
10593	case ARM::VSUBLuv2i64:
10594	case ARM::VSUBLuv4i32:
10595	case ARM::VSUBLuv8i16:
10596	case ARM::VSUBWsv2i64:
10597	case ARM::VSUBWsv4i32:
10598	case ARM::VSUBWsv8i16:
10599	case ARM::VSUBWuv2i64:
10600	case ARM::VSUBWuv4i32:
10601	case ARM::VSUBWuv8i16:
10602	case ARM::VSUBfd:
10603	case ARM::VSUBfq:
10604	case ARM::VSUBhd:
10605	case ARM::VSUBhq:
10606	case ARM::VSUBv16i8:
10607	case ARM::VSUBv1i64:
10608	case ARM::VSUBv2i32:
10609	case ARM::VSUBv2i64:
10610	case ARM::VSUBv4i16:
10611	case ARM::VSUBv4i32:
10612	case ARM::VSUBv8i16:
10613	case ARM::VSUBv8i8:
10614	case ARM::VTBL1:
10615	case ARM::VTBL2:
10616	case ARM::VTBL3:
10617	case ARM::VTBL4:
10618	case ARM::VTSTv16i8:
10619	case ARM::VTSTv2i32:
10620	case ARM::VTSTv4i16:
10621	case ARM::VTSTv4i32:
10622	case ARM::VTSTv8i16:
10623	case ARM::VTSTv8i8: {
10624	// op: Vd
10625	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
10626	Value \|= (op & UINT64_C(`16`)) << `18`;
10627	Value \|= (op & UINT64_C(`15`)) << `12`;
10628	// op: Vn
10629	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
10630	Value \|= (op & UINT64_C(`15`)) << `16`;
10631	Value \|= (op & UINT64_C(`16`)) << `3`;
10632	// op: Vm
10633	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
10634	Value \|= (op & UINT64_C(`16`)) << `1`;
10635	Value \|= (op & UINT64_C(`15`));
10636	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
10637	break;
10638	}
10639	case ARM::NEON_VMAXNMNDf:
10640	case ARM::NEON_VMAXNMNDh:
10641	case ARM::NEON_VMAXNMNQf:
10642	case ARM::NEON_VMAXNMNQh:
10643	case ARM::NEON_VMINNMNDf:
10644	case ARM::NEON_VMINNMNDh:
10645	case ARM::NEON_VMINNMNQf:
10646	case ARM::NEON_VMINNMNQh: {
10647	// op: Vd
10648	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
10649	Value \|= (op & UINT64_C(`16`)) << `18`;
10650	Value \|= (op & UINT64_C(`15`)) << `12`;
10651	// op: Vn
10652	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
10653	Value \|= (op & UINT64_C(`15`)) << `16`;
10654	Value \|= (op & UINT64_C(`16`)) << `3`;
10655	// op: Vm
10656	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
10657	Value \|= (op & UINT64_C(`16`)) << `1`;
10658	Value \|= (op & UINT64_C(`15`));
10659	Value = NEONThumb2V8PostEncoder(MI, Value, STI);
10660	break;
10661	}
10662	case ARM::VMULLslsv2i32:
10663	case ARM::VMULLsluv2i32:
10664	case ARM::VMULslfd:
10665	case ARM::VMULslfq:
10666	case ARM::VMULslv2i32:
10667	case ARM::VMULslv4i32:
10668	case ARM::VQDMULHslv2i32:
10669	case ARM::VQDMULHslv4i32:
10670	case ARM::VQDMULLslv2i32:
10671	case ARM::VQRDMULHslv2i32:
10672	case ARM::VQRDMULHslv4i32: {
10673	// op: Vd
10674	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
10675	Value \|= (op & UINT64_C(`16`)) << `18`;
10676	Value \|= (op & UINT64_C(`15`)) << `12`;
10677	// op: Vn
10678	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
10679	Value \|= (op & UINT64_C(`15`)) << `16`;
10680	Value \|= (op & UINT64_C(`16`)) << `3`;
10681	// op: Vm
10682	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
10683	op &= UINT64_C(`15`);
10684	Value \|= op;
10685	// op: lane
10686	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
10687	op &= UINT64_C(`1`);
10688	op <<= `5`;
10689	Value \|= op;
10690	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
10691	break;
10692	}
10693	case ARM::VFMALQI:
10694	case ARM::VFMSLQI: {
10695	// op: Vd
10696	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
10697	Value \|= (op & UINT64_C(`16`)) << `18`;
10698	Value \|= (op & UINT64_C(`15`)) << `12`;
10699	// op: Vn
10700	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
10701	Value \|= (op & UINT64_C(`15`)) << `16`;
10702	Value \|= (op & UINT64_C(`16`)) << `3`;
10703	// op: Vm
10704	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
10705	op &= UINT64_C(`7`);
10706	Value \|= op;
10707	// op: idx
10708	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
10709	Value \|= (op & UINT64_C(`2`)) << `4`;
10710	Value \|= (op & UINT64_C(`1`)) << `3`;
10711	break;
10712	}
10713	case ARM::VMULLslsv4i16:
10714	case ARM::VMULLsluv4i16:
10715	case ARM::VMULslhd:
10716	case ARM::VMULslhq:
10717	case ARM::VMULslv4i16:
10718	case ARM::VMULslv8i16:
10719	case ARM::VQDMULHslv4i16:
10720	case ARM::VQDMULHslv8i16:
10721	case ARM::VQDMULLslv4i16:
10722	case ARM::VQRDMULHslv4i16:
10723	case ARM::VQRDMULHslv8i16: {
10724	// op: Vd
10725	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
10726	Value \|= (op & UINT64_C(`16`)) << `18`;
10727	Value \|= (op & UINT64_C(`15`)) << `12`;
10728	// op: Vn
10729	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
10730	Value \|= (op & UINT64_C(`15`)) << `16`;
10731	Value \|= (op & UINT64_C(`16`)) << `3`;
10732	// op: Vm
10733	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
10734	op &= UINT64_C(`7`);
10735	Value \|= op;
10736	// op: lane
10737	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
10738	Value \|= (op & UINT64_C(`2`)) << `4`;
10739	Value \|= (op & UINT64_C(`1`)) << `3`;
10740	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
10741	break;
10742	}
10743	case ARM::VFMALDI:
10744	case ARM::VFMSLDI: {
10745	// op: Vd
10746	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
10747	Value \|= (op & UINT64_C(`16`)) << `18`;
10748	Value \|= (op & UINT64_C(`15`)) << `12`;
10749	// op: Vn
10750	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
10751	Value \|= (op & UINT64_C(`30`)) << `15`;
10752	Value \|= (op & UINT64_C(`1`)) << `7`;
10753	// op: Vm
10754	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
10755	Value \|= (op & UINT64_C(`1`)) << `5`;
10756	Value \|= (op & UINT64_C(`14`)) >> `1`;
10757	// op: idx
10758	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
10759	op &= UINT64_C(`1`);
10760	op <<= `3`;
10761	Value \|= op;
10762	break;
10763	}
10764	case ARM::VFMALD:
10765	case ARM::VFMSLD: {
10766	// op: Vd
10767	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
10768	Value \|= (op & UINT64_C(`16`)) << `18`;
10769	Value \|= (op & UINT64_C(`15`)) << `12`;
10770	// op: Vn
10771	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
10772	Value \|= (op & UINT64_C(`30`)) << `15`;
10773	Value \|= (op & UINT64_C(`1`)) << `7`;
10774	// op: Vm
10775	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
10776	Value \|= (op & UINT64_C(`1`)) << `5`;
10777	Value \|= (op & UINT64_C(`30`)) >> `1`;
10778	break;
10779	}
10780	case ARM::VQRSHLsv16i8:
10781	case ARM::VQRSHLsv1i64:
10782	case ARM::VQRSHLsv2i32:
10783	case ARM::VQRSHLsv2i64:
10784	case ARM::VQRSHLsv4i16:
10785	case ARM::VQRSHLsv4i32:
10786	case ARM::VQRSHLsv8i16:
10787	case ARM::VQRSHLsv8i8:
10788	case ARM::VQRSHLuv16i8:
10789	case ARM::VQRSHLuv1i64:
10790	case ARM::VQRSHLuv2i32:
10791	case ARM::VQRSHLuv2i64:
10792	case ARM::VQRSHLuv4i16:
10793	case ARM::VQRSHLuv4i32:
10794	case ARM::VQRSHLuv8i16:
10795	case ARM::VQRSHLuv8i8:
10796	case ARM::VQSHLsv16i8:
10797	case ARM::VQSHLsv1i64:
10798	case ARM::VQSHLsv2i32:
10799	case ARM::VQSHLsv2i64:
10800	case ARM::VQSHLsv4i16:
10801	case ARM::VQSHLsv4i32:
10802	case ARM::VQSHLsv8i16:
10803	case ARM::VQSHLsv8i8:
10804	case ARM::VQSHLuv16i8:
10805	case ARM::VQSHLuv1i64:
10806	case ARM::VQSHLuv2i32:
10807	case ARM::VQSHLuv2i64:
10808	case ARM::VQSHLuv4i16:
10809	case ARM::VQSHLuv4i32:
10810	case ARM::VQSHLuv8i16:
10811	case ARM::VQSHLuv8i8:
10812	case ARM::VRSHLsv16i8:
10813	case ARM::VRSHLsv1i64:
10814	case ARM::VRSHLsv2i32:
10815	case ARM::VRSHLsv2i64:
10816	case ARM::VRSHLsv4i16:
10817	case ARM::VRSHLsv4i32:
10818	case ARM::VRSHLsv8i16:
10819	case ARM::VRSHLsv8i8:
10820	case ARM::VRSHLuv16i8:
10821	case ARM::VRSHLuv1i64:
10822	case ARM::VRSHLuv2i32:
10823	case ARM::VRSHLuv2i64:
10824	case ARM::VRSHLuv4i16:
10825	case ARM::VRSHLuv4i32:
10826	case ARM::VRSHLuv8i16:
10827	case ARM::VRSHLuv8i8:
10828	case ARM::VSHLsv16i8:
10829	case ARM::VSHLsv1i64:
10830	case ARM::VSHLsv2i32:
10831	case ARM::VSHLsv2i64:
10832	case ARM::VSHLsv4i16:
10833	case ARM::VSHLsv4i32:
10834	case ARM::VSHLsv8i16:
10835	case ARM::VSHLsv8i8:
10836	case ARM::VSHLuv16i8:
10837	case ARM::VSHLuv1i64:
10838	case ARM::VSHLuv2i32:
10839	case ARM::VSHLuv2i64:
10840	case ARM::VSHLuv4i16:
10841	case ARM::VSHLuv4i32:
10842	case ARM::VSHLuv8i16:
10843	case ARM::VSHLuv8i8: {
10844	// op: Vd
10845	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
10846	Value \|= (op & UINT64_C(`16`)) << `18`;
10847	Value \|= (op & UINT64_C(`15`)) << `12`;
10848	// op: Vn
10849	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
10850	Value \|= (op & UINT64_C(`15`)) << `16`;
10851	Value \|= (op & UINT64_C(`16`)) << `3`;
10852	// op: Vm
10853	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
10854	Value \|= (op & UINT64_C(`16`)) << `1`;
10855	Value \|= (op & UINT64_C(`15`));
10856	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
10857	break;
10858	}
10859	case ARM::VCMLAv2f32:
10860	case ARM::VCMLAv4f16:
10861	case ARM::VCMLAv4f32:
10862	case ARM::VCMLAv8f16: {
10863	// op: Vd
10864	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
10865	Value \|= (op & UINT64_C(`16`)) << `18`;
10866	Value \|= (op & UINT64_C(`15`)) << `12`;
10867	// op: Vn
10868	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
10869	Value \|= (op & UINT64_C(`15`)) << `16`;
10870	Value \|= (op & UINT64_C(`16`)) << `3`;
10871	// op: Vm
10872	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
10873	Value \|= (op & UINT64_C(`16`)) << `1`;
10874	Value \|= (op & UINT64_C(`15`));
10875	// op: rot
10876	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
10877	op &= UINT64_C(`3`);
10878	op <<= `23`;
10879	Value \|= op;
10880	break;
10881	}
10882	case ARM::VCMLAv2f32_indexed:
10883	case ARM::VCMLAv4f32_indexed: {
10884	// op: Vd
10885	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
10886	Value \|= (op & UINT64_C(`16`)) << `18`;
10887	Value \|= (op & UINT64_C(`15`)) << `12`;
10888	// op: Vn
10889	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
10890	Value \|= (op & UINT64_C(`15`)) << `16`;
10891	Value \|= (op & UINT64_C(`16`)) << `3`;
10892	// op: Vm
10893	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
10894	Value \|= (op & UINT64_C(`16`)) << `1`;
10895	Value \|= (op & UINT64_C(`15`));
10896	// op: rot
10897	op = getMachineOpValue(MI, MI.getOperand(`5`), Fixups, STI);
10898	op &= UINT64_C(`3`);
10899	op <<= `20`;
10900	Value \|= op;
10901	break;
10902	}
10903	case ARM::SHA1C:
10904	case ARM::SHA1M:
10905	case ARM::SHA1P:
10906	case ARM::SHA1SU0:
10907	case ARM::SHA256H:
10908	case ARM::SHA256H2:
10909	case ARM::SHA256SU1:
10910	case ARM::VABALsv2i64:
10911	case ARM::VABALsv4i32:
10912	case ARM::VABALsv8i16:
10913	case ARM::VABALuv2i64:
10914	case ARM::VABALuv4i32:
10915	case ARM::VABALuv8i16:
10916	case ARM::VABAsv16i8:
10917	case ARM::VABAsv2i32:
10918	case ARM::VABAsv4i16:
10919	case ARM::VABAsv4i32:
10920	case ARM::VABAsv8i16:
10921	case ARM::VABAsv8i8:
10922	case ARM::VABAuv16i8:
10923	case ARM::VABAuv2i32:
10924	case ARM::VABAuv4i16:
10925	case ARM::VABAuv4i32:
10926	case ARM::VABAuv8i16:
10927	case ARM::VABAuv8i8:
10928	case ARM::VBIFd:
10929	case ARM::VBIFq:
10930	case ARM::VBITd:
10931	case ARM::VBITq:
10932	case ARM::VBSLd:
10933	case ARM::VBSLq:
10934	case ARM::VFMAfd:
10935	case ARM::VFMAfq:
10936	case ARM::VFMAhd:
10937	case ARM::VFMAhq:
10938	case ARM::VFMSfd:
10939	case ARM::VFMSfq:
10940	case ARM::VFMShd:
10941	case ARM::VFMShq:
10942	case ARM::VMLALsv2i64:
10943	case ARM::VMLALsv4i32:
10944	case ARM::VMLALsv8i16:
10945	case ARM::VMLALuv2i64:
10946	case ARM::VMLALuv4i32:
10947	case ARM::VMLALuv8i16:
10948	case ARM::VMLAfd:
10949	case ARM::VMLAfq:
10950	case ARM::VMLAhd:
10951	case ARM::VMLAhq:
10952	case ARM::VMLAv16i8:
10953	case ARM::VMLAv2i32:
10954	case ARM::VMLAv4i16:
10955	case ARM::VMLAv4i32:
10956	case ARM::VMLAv8i16:
10957	case ARM::VMLAv8i8:
10958	case ARM::VMLSLsv2i64:
10959	case ARM::VMLSLsv4i32:
10960	case ARM::VMLSLsv8i16:
10961	case ARM::VMLSLuv2i64:
10962	case ARM::VMLSLuv4i32:
10963	case ARM::VMLSLuv8i16:
10964	case ARM::VMLSfd:
10965	case ARM::VMLSfq:
10966	case ARM::VMLShd:
10967	case ARM::VMLShq:
10968	case ARM::VMLSv16i8:
10969	case ARM::VMLSv2i32:
10970	case ARM::VMLSv4i16:
10971	case ARM::VMLSv4i32:
10972	case ARM::VMLSv8i16:
10973	case ARM::VMLSv8i8:
10974	case ARM::VQDMLALv2i64:
10975	case ARM::VQDMLALv4i32:
10976	case ARM::VQDMLSLv2i64:
10977	case ARM::VQDMLSLv4i32:
10978	case ARM::VQRDMLAHv2i32:
10979	case ARM::VQRDMLAHv4i16:
10980	case ARM::VQRDMLAHv4i32:
10981	case ARM::VQRDMLAHv8i16:
10982	case ARM::VQRDMLSHv2i32:
10983	case ARM::VQRDMLSHv4i16:
10984	case ARM::VQRDMLSHv4i32:
10985	case ARM::VQRDMLSHv8i16:
10986	case ARM::VTBX1:
10987	case ARM::VTBX2:
10988	case ARM::VTBX3:
10989	case ARM::VTBX4: {
10990	// op: Vd
10991	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
10992	Value \|= (op & UINT64_C(`16`)) << `18`;
10993	Value \|= (op & UINT64_C(`15`)) << `12`;
10994	// op: Vn
10995	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
10996	Value \|= (op & UINT64_C(`15`)) << `16`;
10997	Value \|= (op & UINT64_C(`16`)) << `3`;
10998	// op: Vm
10999	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
11000	Value \|= (op & UINT64_C(`16`)) << `1`;
11001	Value \|= (op & UINT64_C(`15`));
11002	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
11003	break;
11004	}
11005	case ARM::VMLALslsv2i32:
11006	case ARM::VMLALsluv2i32:
11007	case ARM::VMLAslfd:
11008	case ARM::VMLAslfq:
11009	case ARM::VMLAslv2i32:
11010	case ARM::VMLAslv4i32:
11011	case ARM::VMLSLslsv2i32:
11012	case ARM::VMLSLsluv2i32:
11013	case ARM::VMLSslfd:
11014	case ARM::VMLSslfq:
11015	case ARM::VMLSslv2i32:
11016	case ARM::VMLSslv4i32:
11017	case ARM::VQDMLALslv2i32:
11018	case ARM::VQDMLSLslv2i32:
11019	case ARM::VQRDMLAHslv2i32:
11020	case ARM::VQRDMLAHslv4i32:
11021	case ARM::VQRDMLSHslv2i32:
11022	case ARM::VQRDMLSHslv4i32: {
11023	// op: Vd
11024	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
11025	Value \|= (op & UINT64_C(`16`)) << `18`;
11026	Value \|= (op & UINT64_C(`15`)) << `12`;
11027	// op: Vn
11028	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
11029	Value \|= (op & UINT64_C(`15`)) << `16`;
11030	Value \|= (op & UINT64_C(`16`)) << `3`;
11031	// op: Vm
11032	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
11033	op &= UINT64_C(`15`);
11034	Value \|= op;
11035	// op: lane
11036	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
11037	op &= UINT64_C(`1`);
11038	op <<= `5`;
11039	Value \|= op;
11040	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
11041	break;
11042	}
11043	case ARM::VCMLAv4f16_indexed:
11044	case ARM::VCMLAv8f16_indexed: {
11045	// op: Vd
11046	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
11047	Value \|= (op & UINT64_C(`16`)) << `18`;
11048	Value \|= (op & UINT64_C(`15`)) << `12`;
11049	// op: Vn
11050	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
11051	Value \|= (op & UINT64_C(`15`)) << `16`;
11052	Value \|= (op & UINT64_C(`16`)) << `3`;
11053	// op: Vm
11054	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
11055	op &= UINT64_C(`15`);
11056	Value \|= op;
11057	// op: rot
11058	op = getMachineOpValue(MI, MI.getOperand(`5`), Fixups, STI);
11059	op &= UINT64_C(`3`);
11060	op <<= `20`;
11061	Value \|= op;
11062	// op: lane
11063	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
11064	op &= UINT64_C(`1`);
11065	op <<= `5`;
11066	Value \|= op;
11067	break;
11068	}
11069	case ARM::VMLALslsv4i16:
11070	case ARM::VMLALsluv4i16:
11071	case ARM::VMLAslhd:
11072	case ARM::VMLAslhq:
11073	case ARM::VMLAslv4i16:
11074	case ARM::VMLAslv8i16:
11075	case ARM::VMLSLslsv4i16:
11076	case ARM::VMLSLsluv4i16:
11077	case ARM::VMLSslhd:
11078	case ARM::VMLSslhq:
11079	case ARM::VMLSslv4i16:
11080	case ARM::VMLSslv8i16:
11081	case ARM::VQDMLALslv4i16:
11082	case ARM::VQDMLSLslv4i16:
11083	case ARM::VQRDMLAHslv4i16:
11084	case ARM::VQRDMLAHslv8i16:
11085	case ARM::VQRDMLSHslv4i16:
11086	case ARM::VQRDMLSHslv8i16: {
11087	// op: Vd
11088	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
11089	Value \|= (op & UINT64_C(`16`)) << `18`;
11090	Value \|= (op & UINT64_C(`15`)) << `12`;
11091	// op: Vn
11092	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
11093	Value \|= (op & UINT64_C(`15`)) << `16`;
11094	Value \|= (op & UINT64_C(`16`)) << `3`;
11095	// op: Vm
11096	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
11097	op &= UINT64_C(`7`);
11098	Value \|= op;
11099	// op: lane
11100	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
11101	Value \|= (op & UINT64_C(`2`)) << `4`;
11102	Value \|= (op & UINT64_C(`1`)) << `3`;
11103	Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
11104	break;
11105	}
11106	case ARM::BF16VDOTS_VDOTD:
11107	case ARM::BF16VDOTS_VDOTQ:
11108	case ARM::VBF16MALBQ:
11109	case ARM::VBF16MALTQ:
11110	case ARM::VMMLA:
11111	case ARM::VSDOTD:
11112	case ARM::VSDOTQ:
11113	case ARM::VSMMLA:
11114	case ARM::VUDOTD:
11115	case ARM::VUDOTQ:
11116	case ARM::VUMMLA:
11117	case ARM::VUSDOTD:
11118	case ARM::VUSDOTQ:
11119	case ARM::VUSMMLA: {
11120	// op: Vd
11121	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
11122	Value \|= (op & UINT64_C(`16`)) << `18`;
11123	Value \|= (op & UINT64_C(`15`)) << `12`;
11124	// op: Vn
11125	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
11126	Value \|= (op & UINT64_C(`15`)) << `16`;
11127	Value \|= (op & UINT64_C(`16`)) << `3`;
11128	// op: Vm
11129	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
11130	Value \|= (op & UINT64_C(`16`)) << `1`;
11131	Value \|= (op & UINT64_C(`15`));
11132	break;
11133	}
11134	case ARM::BF16VDOTI_VDOTD:
11135	case ARM::BF16VDOTI_VDOTQ:
11136	case ARM::VSDOTDI:
11137	case ARM::VSDOTQI:
11138	case ARM::VSUDOTDI:
11139	case ARM::VSUDOTQI:
11140	case ARM::VUDOTDI:
11141	case ARM::VUDOTQI:
11142	case ARM::VUSDOTDI:
11143	case ARM::VUSDOTQI: {
11144	// op: Vd
11145	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
11146	Value \|= (op & UINT64_C(`16`)) << `18`;
11147	Value \|= (op & UINT64_C(`15`)) << `12`;
11148	// op: Vn
11149	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
11150	Value \|= (op & UINT64_C(`15`)) << `16`;
11151	Value \|= (op & UINT64_C(`16`)) << `3`;
11152	// op: Vm
11153	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
11154	op &= UINT64_C(`15`);
11155	Value \|= op;
11156	// op: lane
11157	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
11158	op &= UINT64_C(`1`);
11159	op <<= `5`;
11160	Value \|= op;
11161	break;
11162	}
11163	case ARM::VBF16MALBQI:
11164	case ARM::VBF16MALTQI: {
11165	// op: Vd
11166	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
11167	Value \|= (op & UINT64_C(`16`)) << `18`;
11168	Value \|= (op & UINT64_C(`15`)) << `12`;
11169	// op: Vn
11170	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
11171	Value \|= (op & UINT64_C(`15`)) << `16`;
11172	Value \|= (op & UINT64_C(`16`)) << `3`;
11173	// op: Vm
11174	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
11175	op &= UINT64_C(`7`);
11176	Value \|= op;
11177	// op: idx
11178	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
11179	Value \|= (op & UINT64_C(`2`)) << `4`;
11180	Value \|= (op & UINT64_C(`1`)) << `3`;
11181	break;
11182	}
11183	case ARM::VST1LNd16: {
11184	// op: Vd
11185	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
11186	Value \|= (op & UINT64_C(`16`)) << `18`;
11187	Value \|= (op & UINT64_C(`15`)) << `12`;
11188	// op: Rn
11189	op = getAddrMode6AddressOpValue(MI, `0`, Fixups, STI);
11190	Value \|= (op & UINT64_C(`15`)) << `16`;
11191	Value \|= (op & UINT64_C(`16`));
11192	// op: lane
11193	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
11194	op &= UINT64_C(`3`);
11195	op <<= `6`;
11196	Value \|= op;
11197	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11198	break;
11199	}
11200	case ARM::VST2LNd32:
11201	case ARM::VST2LNq32: {
11202	// op: Vd
11203	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
11204	Value \|= (op & UINT64_C(`16`)) << `18`;
11205	Value \|= (op & UINT64_C(`15`)) << `12`;
11206	// op: Rn
11207	op = getAddrMode6AddressOpValue(MI, `0`, Fixups, STI);
11208	Value \|= (op & UINT64_C(`15`)) << `16`;
11209	Value \|= (op & UINT64_C(`16`));
11210	// op: lane
11211	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
11212	op &= UINT64_C(`1`);
11213	op <<= `7`;
11214	Value \|= op;
11215	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11216	break;
11217	}
11218	case ARM::VST2LNd16:
11219	case ARM::VST2LNq16: {
11220	// op: Vd
11221	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
11222	Value \|= (op & UINT64_C(`16`)) << `18`;
11223	Value \|= (op & UINT64_C(`15`)) << `12`;
11224	// op: Rn
11225	op = getAddrMode6AddressOpValue(MI, `0`, Fixups, STI);
11226	Value \|= (op & UINT64_C(`15`)) << `16`;
11227	Value \|= (op & UINT64_C(`16`));
11228	// op: lane
11229	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
11230	op &= UINT64_C(`3`);
11231	op <<= `6`;
11232	Value \|= op;
11233	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11234	break;
11235	}
11236	case ARM::VST2LNd8: {
11237	// op: Vd
11238	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
11239	Value \|= (op & UINT64_C(`16`)) << `18`;
11240	Value \|= (op & UINT64_C(`15`)) << `12`;
11241	// op: Rn
11242	op = getAddrMode6AddressOpValue(MI, `0`, Fixups, STI);
11243	Value \|= (op & UINT64_C(`15`)) << `16`;
11244	Value \|= (op & UINT64_C(`16`));
11245	// op: lane
11246	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
11247	op &= UINT64_C(`7`);
11248	op <<= `5`;
11249	Value \|= op;
11250	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11251	break;
11252	}
11253	case ARM::VST4LNd16:
11254	case ARM::VST4LNq16: {
11255	// op: Vd
11256	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
11257	Value \|= (op & UINT64_C(`16`)) << `18`;
11258	Value \|= (op & UINT64_C(`15`)) << `12`;
11259	// op: Rn
11260	op = getAddrMode6AddressOpValue(MI, `0`, Fixups, STI);
11261	Value \|= (op & UINT64_C(`15`)) << `16`;
11262	Value \|= (op & UINT64_C(`16`));
11263	// op: lane
11264	op = getMachineOpValue(MI, MI.getOperand(`6`), Fixups, STI);
11265	op &= UINT64_C(`3`);
11266	op <<= `6`;
11267	Value \|= op;
11268	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11269	break;
11270	}
11271	case ARM::VST4LNd8: {
11272	// op: Vd
11273	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
11274	Value \|= (op & UINT64_C(`16`)) << `18`;
11275	Value \|= (op & UINT64_C(`15`)) << `12`;
11276	// op: Rn
11277	op = getAddrMode6AddressOpValue(MI, `0`, Fixups, STI);
11278	Value \|= (op & UINT64_C(`15`)) << `16`;
11279	Value \|= (op & UINT64_C(`16`));
11280	// op: lane
11281	op = getMachineOpValue(MI, MI.getOperand(`6`), Fixups, STI);
11282	op &= UINT64_C(`7`);
11283	op <<= `5`;
11284	Value \|= op;
11285	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11286	break;
11287	}
11288	case ARM::VST1d16:
11289	case ARM::VST1d16T:
11290	case ARM::VST1d32:
11291	case ARM::VST1d32T:
11292	case ARM::VST1d64:
11293	case ARM::VST1d64T:
11294	case ARM::VST1d8:
11295	case ARM::VST1d8T:
11296	case ARM::VST3d16:
11297	case ARM::VST3d32:
11298	case ARM::VST3d8:
11299	case ARM::VST3q16:
11300	case ARM::VST3q32:
11301	case ARM::VST3q8: {
11302	// op: Vd
11303	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
11304	Value \|= (op & UINT64_C(`16`)) << `18`;
11305	Value \|= (op & UINT64_C(`15`)) << `12`;
11306	// op: Rn
11307	op = getAddrMode6AddressOpValue(MI, `0`, Fixups, STI);
11308	Value \|= (op & UINT64_C(`15`)) << `16`;
11309	Value \|= (op & UINT64_C(`16`));
11310	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11311	break;
11312	}
11313	case ARM::VST4LNd32:
11314	case ARM::VST4LNq32: {
11315	// op: Vd
11316	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
11317	Value \|= (op & UINT64_C(`16`)) << `18`;
11318	Value \|= (op & UINT64_C(`15`)) << `12`;
11319	// op: Rn
11320	op = getAddrMode6AddressOpValue(MI, `0`, Fixups, STI);
11321	Value \|= (op & UINT64_C(`15`)) << `16`;
11322	Value \|= (op & UINT64_C(`48`));
11323	// op: lane
11324	op = getMachineOpValue(MI, MI.getOperand(`6`), Fixups, STI);
11325	op &= UINT64_C(`1`);
11326	op <<= `7`;
11327	Value \|= op;
11328	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11329	break;
11330	}
11331	case ARM::VST1d16Q:
11332	case ARM::VST1d32Q:
11333	case ARM::VST1d64Q:
11334	case ARM::VST1d8Q:
11335	case ARM::VST1q16:
11336	case ARM::VST1q32:
11337	case ARM::VST1q64:
11338	case ARM::VST1q8:
11339	case ARM::VST2b16:
11340	case ARM::VST2b32:
11341	case ARM::VST2b8:
11342	case ARM::VST2d16:
11343	case ARM::VST2d32:
11344	case ARM::VST2d8:
11345	case ARM::VST2q16:
11346	case ARM::VST2q32:
11347	case ARM::VST2q8:
11348	case ARM::VST4d16:
11349	case ARM::VST4d32:
11350	case ARM::VST4d8:
11351	case ARM::VST4q16:
11352	case ARM::VST4q32:
11353	case ARM::VST4q8: {
11354	// op: Vd
11355	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
11356	Value \|= (op & UINT64_C(`16`)) << `18`;
11357	Value \|= (op & UINT64_C(`15`)) << `12`;
11358	// op: Rn
11359	op = getAddrMode6AddressOpValue(MI, `0`, Fixups, STI);
11360	Value \|= (op & UINT64_C(`15`)) << `16`;
11361	Value \|= (op & UINT64_C(`48`));
11362	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11363	break;
11364	}
11365	case ARM::VST1LNd8: {
11366	// op: Vd
11367	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
11368	Value \|= (op & UINT64_C(`16`)) << `18`;
11369	Value \|= (op & UINT64_C(`15`)) << `12`;
11370	// op: Rn
11371	op = getAddrMode6AddressOpValue(MI, `0`, Fixups, STI);
11372	op &= UINT64_C(`15`);
11373	op <<= `16`;
11374	Value \|= op;
11375	// op: lane
11376	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
11377	op &= UINT64_C(`7`);
11378	op <<= `5`;
11379	Value \|= op;
11380	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11381	break;
11382	}
11383	case ARM::VST3LNd32:
11384	case ARM::VST3LNq32: {
11385	// op: Vd
11386	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
11387	Value \|= (op & UINT64_C(`16`)) << `18`;
11388	Value \|= (op & UINT64_C(`15`)) << `12`;
11389	// op: Rn
11390	op = getAddrMode6AddressOpValue(MI, `0`, Fixups, STI);
11391	op &= UINT64_C(`15`);
11392	op <<= `16`;
11393	Value \|= op;
11394	// op: lane
11395	op = getMachineOpValue(MI, MI.getOperand(`5`), Fixups, STI);
11396	op &= UINT64_C(`1`);
11397	op <<= `7`;
11398	Value \|= op;
11399	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11400	break;
11401	}
11402	case ARM::VST3LNd16:
11403	case ARM::VST3LNq16: {
11404	// op: Vd
11405	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
11406	Value \|= (op & UINT64_C(`16`)) << `18`;
11407	Value \|= (op & UINT64_C(`15`)) << `12`;
11408	// op: Rn
11409	op = getAddrMode6AddressOpValue(MI, `0`, Fixups, STI);
11410	op &= UINT64_C(`15`);
11411	op <<= `16`;
11412	Value \|= op;
11413	// op: lane
11414	op = getMachineOpValue(MI, MI.getOperand(`5`), Fixups, STI);
11415	op &= UINT64_C(`3`);
11416	op <<= `6`;
11417	Value \|= op;
11418	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11419	break;
11420	}
11421	case ARM::VST3LNd8: {
11422	// op: Vd
11423	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
11424	Value \|= (op & UINT64_C(`16`)) << `18`;
11425	Value \|= (op & UINT64_C(`15`)) << `12`;
11426	// op: Rn
11427	op = getAddrMode6AddressOpValue(MI, `0`, Fixups, STI);
11428	op &= UINT64_C(`15`);
11429	op <<= `16`;
11430	Value \|= op;
11431	// op: lane
11432	op = getMachineOpValue(MI, MI.getOperand(`5`), Fixups, STI);
11433	op &= UINT64_C(`7`);
11434	op <<= `5`;
11435	Value \|= op;
11436	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11437	break;
11438	}
11439	case ARM::VST1LNd32: {
11440	// op: Vd
11441	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
11442	Value \|= (op & UINT64_C(`16`)) << `18`;
11443	Value \|= (op & UINT64_C(`15`)) << `12`;
11444	// op: Rn
11445	op = getAddrMode6OneLane32AddressOpValue(MI, `0`, Fixups, STI);
11446	Value \|= (op & UINT64_C(`15`)) << `16`;
11447	Value \|= (op & UINT64_C(`48`));
11448	// op: lane
11449	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
11450	op &= UINT64_C(`1`);
11451	op <<= `7`;
11452	Value \|= op;
11453	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11454	break;
11455	}
11456	case ARM::VST1d16wb_fixed:
11457	case ARM::VST1d32wb_fixed:
11458	case ARM::VST1d64wb_fixed:
11459	case ARM::VST1d8wb_fixed: {
11460	// op: Vd
11461	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
11462	Value \|= (op & UINT64_C(`16`)) << `18`;
11463	Value \|= (op & UINT64_C(`15`)) << `12`;
11464	// op: Rn
11465	op = getAddrMode6AddressOpValue(MI, `1`, Fixups, STI);
11466	Value \|= (op & UINT64_C(`15`)) << `16`;
11467	Value \|= (op & UINT64_C(`16`));
11468	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11469	break;
11470	}
11471	case ARM::VST1d16Qwb_fixed:
11472	case ARM::VST1d16Twb_fixed:
11473	case ARM::VST1d32Qwb_fixed:
11474	case ARM::VST1d32Twb_fixed:
11475	case ARM::VST1d64Qwb_fixed:
11476	case ARM::VST1d64Twb_fixed:
11477	case ARM::VST1d8Qwb_fixed:
11478	case ARM::VST1d8Twb_fixed:
11479	case ARM::VST1q16wb_fixed:
11480	case ARM::VST1q32wb_fixed:
11481	case ARM::VST1q64wb_fixed:
11482	case ARM::VST1q8wb_fixed:
11483	case ARM::VST2b16wb_fixed:
11484	case ARM::VST2b32wb_fixed:
11485	case ARM::VST2b8wb_fixed:
11486	case ARM::VST2d16wb_fixed:
11487	case ARM::VST2d32wb_fixed:
11488	case ARM::VST2d8wb_fixed:
11489	case ARM::VST2q16wb_fixed:
11490	case ARM::VST2q32wb_fixed:
11491	case ARM::VST2q8wb_fixed: {
11492	// op: Vd
11493	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
11494	Value \|= (op & UINT64_C(`16`)) << `18`;
11495	Value \|= (op & UINT64_C(`15`)) << `12`;
11496	// op: Rn
11497	op = getAddrMode6AddressOpValue(MI, `1`, Fixups, STI);
11498	Value \|= (op & UINT64_C(`15`)) << `16`;
11499	Value \|= (op & UINT64_C(`48`));
11500	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11501	break;
11502	}
11503	case ARM::VST1LNd16_UPD: {
11504	// op: Vd
11505	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
11506	Value \|= (op & UINT64_C(`16`)) << `18`;
11507	Value \|= (op & UINT64_C(`15`)) << `12`;
11508	// op: Rn
11509	op = getAddrMode6AddressOpValue(MI, `1`, Fixups, STI);
11510	Value \|= (op & UINT64_C(`15`)) << `16`;
11511	Value \|= (op & UINT64_C(`16`));
11512	// op: Rm
11513	op = getAddrMode6OffsetOpValue(MI, `3`, Fixups, STI);
11514	op &= UINT64_C(`15`);
11515	Value \|= op;
11516	// op: lane
11517	op = getMachineOpValue(MI, MI.getOperand(`5`), Fixups, STI);
11518	op &= UINT64_C(`3`);
11519	op <<= `6`;
11520	Value \|= op;
11521	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11522	break;
11523	}
11524	case ARM::VST2LNd32_UPD:
11525	case ARM::VST2LNq32_UPD: {
11526	// op: Vd
11527	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
11528	Value \|= (op & UINT64_C(`16`)) << `18`;
11529	Value \|= (op & UINT64_C(`15`)) << `12`;
11530	// op: Rn
11531	op = getAddrMode6AddressOpValue(MI, `1`, Fixups, STI);
11532	Value \|= (op & UINT64_C(`15`)) << `16`;
11533	Value \|= (op & UINT64_C(`16`));
11534	// op: Rm
11535	op = getAddrMode6OffsetOpValue(MI, `3`, Fixups, STI);
11536	op &= UINT64_C(`15`);
11537	Value \|= op;
11538	// op: lane
11539	op = getMachineOpValue(MI, MI.getOperand(`6`), Fixups, STI);
11540	op &= UINT64_C(`1`);
11541	op <<= `7`;
11542	Value \|= op;
11543	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11544	break;
11545	}
11546	case ARM::VST2LNd16_UPD:
11547	case ARM::VST2LNq16_UPD: {
11548	// op: Vd
11549	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
11550	Value \|= (op & UINT64_C(`16`)) << `18`;
11551	Value \|= (op & UINT64_C(`15`)) << `12`;
11552	// op: Rn
11553	op = getAddrMode6AddressOpValue(MI, `1`, Fixups, STI);
11554	Value \|= (op & UINT64_C(`15`)) << `16`;
11555	Value \|= (op & UINT64_C(`16`));
11556	// op: Rm
11557	op = getAddrMode6OffsetOpValue(MI, `3`, Fixups, STI);
11558	op &= UINT64_C(`15`);
11559	Value \|= op;
11560	// op: lane
11561	op = getMachineOpValue(MI, MI.getOperand(`6`), Fixups, STI);
11562	op &= UINT64_C(`3`);
11563	op <<= `6`;
11564	Value \|= op;
11565	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11566	break;
11567	}
11568	case ARM::VST2LNd8_UPD: {
11569	// op: Vd
11570	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
11571	Value \|= (op & UINT64_C(`16`)) << `18`;
11572	Value \|= (op & UINT64_C(`15`)) << `12`;
11573	// op: Rn
11574	op = getAddrMode6AddressOpValue(MI, `1`, Fixups, STI);
11575	Value \|= (op & UINT64_C(`15`)) << `16`;
11576	Value \|= (op & UINT64_C(`16`));
11577	// op: Rm
11578	op = getAddrMode6OffsetOpValue(MI, `3`, Fixups, STI);
11579	op &= UINT64_C(`15`);
11580	Value \|= op;
11581	// op: lane
11582	op = getMachineOpValue(MI, MI.getOperand(`6`), Fixups, STI);
11583	op &= UINT64_C(`7`);
11584	op <<= `5`;
11585	Value \|= op;
11586	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11587	break;
11588	}
11589	case ARM::VST4LNd16_UPD:
11590	case ARM::VST4LNq16_UPD: {
11591	// op: Vd
11592	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
11593	Value \|= (op & UINT64_C(`16`)) << `18`;
11594	Value \|= (op & UINT64_C(`15`)) << `12`;
11595	// op: Rn
11596	op = getAddrMode6AddressOpValue(MI, `1`, Fixups, STI);
11597	Value \|= (op & UINT64_C(`15`)) << `16`;
11598	Value \|= (op & UINT64_C(`16`));
11599	// op: Rm
11600	op = getAddrMode6OffsetOpValue(MI, `3`, Fixups, STI);
11601	op &= UINT64_C(`15`);
11602	Value \|= op;
11603	// op: lane
11604	op = getMachineOpValue(MI, MI.getOperand(`8`), Fixups, STI);
11605	op &= UINT64_C(`3`);
11606	op <<= `6`;
11607	Value \|= op;
11608	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11609	break;
11610	}
11611	case ARM::VST4LNd8_UPD: {
11612	// op: Vd
11613	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
11614	Value \|= (op & UINT64_C(`16`)) << `18`;
11615	Value \|= (op & UINT64_C(`15`)) << `12`;
11616	// op: Rn
11617	op = getAddrMode6AddressOpValue(MI, `1`, Fixups, STI);
11618	Value \|= (op & UINT64_C(`15`)) << `16`;
11619	Value \|= (op & UINT64_C(`16`));
11620	// op: Rm
11621	op = getAddrMode6OffsetOpValue(MI, `3`, Fixups, STI);
11622	op &= UINT64_C(`15`);
11623	Value \|= op;
11624	// op: lane
11625	op = getMachineOpValue(MI, MI.getOperand(`8`), Fixups, STI);
11626	op &= UINT64_C(`7`);
11627	op <<= `5`;
11628	Value \|= op;
11629	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11630	break;
11631	}
11632	case ARM::VST3d16_UPD:
11633	case ARM::VST3d32_UPD:
11634	case ARM::VST3d8_UPD:
11635	case ARM::VST3q16_UPD:
11636	case ARM::VST3q32_UPD:
11637	case ARM::VST3q8_UPD: {
11638	// op: Vd
11639	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
11640	Value \|= (op & UINT64_C(`16`)) << `18`;
11641	Value \|= (op & UINT64_C(`15`)) << `12`;
11642	// op: Rn
11643	op = getAddrMode6AddressOpValue(MI, `1`, Fixups, STI);
11644	Value \|= (op & UINT64_C(`15`)) << `16`;
11645	Value \|= (op & UINT64_C(`16`));
11646	// op: Rm
11647	op = getAddrMode6OffsetOpValue(MI, `3`, Fixups, STI);
11648	op &= UINT64_C(`15`);
11649	Value \|= op;
11650	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11651	break;
11652	}
11653	case ARM::VST1d16wb_register:
11654	case ARM::VST1d32wb_register:
11655	case ARM::VST1d64wb_register:
11656	case ARM::VST1d8wb_register: {
11657	// op: Vd
11658	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
11659	Value \|= (op & UINT64_C(`16`)) << `18`;
11660	Value \|= (op & UINT64_C(`15`)) << `12`;
11661	// op: Rn
11662	op = getAddrMode6AddressOpValue(MI, `1`, Fixups, STI);
11663	Value \|= (op & UINT64_C(`15`)) << `16`;
11664	Value \|= (op & UINT64_C(`16`));
11665	// op: Rm
11666	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
11667	op &= UINT64_C(`15`);
11668	Value \|= op;
11669	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11670	break;
11671	}
11672	case ARM::VST4LNd32_UPD:
11673	case ARM::VST4LNq32_UPD: {
11674	// op: Vd
11675	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
11676	Value \|= (op & UINT64_C(`16`)) << `18`;
11677	Value \|= (op & UINT64_C(`15`)) << `12`;
11678	// op: Rn
11679	op = getAddrMode6AddressOpValue(MI, `1`, Fixups, STI);
11680	Value \|= (op & UINT64_C(`15`)) << `16`;
11681	Value \|= (op & UINT64_C(`48`));
11682	// op: Rm
11683	op = getAddrMode6OffsetOpValue(MI, `3`, Fixups, STI);
11684	op &= UINT64_C(`15`);
11685	Value \|= op;
11686	// op: lane
11687	op = getMachineOpValue(MI, MI.getOperand(`8`), Fixups, STI);
11688	op &= UINT64_C(`1`);
11689	op <<= `7`;
11690	Value \|= op;
11691	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11692	break;
11693	}
11694	case ARM::VST4d16_UPD:
11695	case ARM::VST4d32_UPD:
11696	case ARM::VST4d8_UPD:
11697	case ARM::VST4q16_UPD:
11698	case ARM::VST4q32_UPD:
11699	case ARM::VST4q8_UPD: {
11700	// op: Vd
11701	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
11702	Value \|= (op & UINT64_C(`16`)) << `18`;
11703	Value \|= (op & UINT64_C(`15`)) << `12`;
11704	// op: Rn
11705	op = getAddrMode6AddressOpValue(MI, `1`, Fixups, STI);
11706	Value \|= (op & UINT64_C(`15`)) << `16`;
11707	Value \|= (op & UINT64_C(`48`));
11708	// op: Rm
11709	op = getAddrMode6OffsetOpValue(MI, `3`, Fixups, STI);
11710	op &= UINT64_C(`15`);
11711	Value \|= op;
11712	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11713	break;
11714	}
11715	case ARM::VST1d16Qwb_register:
11716	case ARM::VST1d16Twb_register:
11717	case ARM::VST1d32Qwb_register:
11718	case ARM::VST1d32Twb_register:
11719	case ARM::VST1d64Qwb_register:
11720	case ARM::VST1d64Twb_register:
11721	case ARM::VST1d8Qwb_register:
11722	case ARM::VST1d8Twb_register:
11723	case ARM::VST1q16wb_register:
11724	case ARM::VST1q32wb_register:
11725	case ARM::VST1q64wb_register:
11726	case ARM::VST1q8wb_register:
11727	case ARM::VST2b16wb_register:
11728	case ARM::VST2b32wb_register:
11729	case ARM::VST2b8wb_register:
11730	case ARM::VST2d16wb_register:
11731	case ARM::VST2d32wb_register:
11732	case ARM::VST2d8wb_register:
11733	case ARM::VST2q16wb_register:
11734	case ARM::VST2q32wb_register:
11735	case ARM::VST2q8wb_register: {
11736	// op: Vd
11737	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
11738	Value \|= (op & UINT64_C(`16`)) << `18`;
11739	Value \|= (op & UINT64_C(`15`)) << `12`;
11740	// op: Rn
11741	op = getAddrMode6AddressOpValue(MI, `1`, Fixups, STI);
11742	Value \|= (op & UINT64_C(`15`)) << `16`;
11743	Value \|= (op & UINT64_C(`48`));
11744	// op: Rm
11745	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
11746	op &= UINT64_C(`15`);
11747	Value \|= op;
11748	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11749	break;
11750	}
11751	case ARM::VST1LNd8_UPD: {
11752	// op: Vd
11753	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
11754	Value \|= (op & UINT64_C(`16`)) << `18`;
11755	Value \|= (op & UINT64_C(`15`)) << `12`;
11756	// op: Rn
11757	op = getAddrMode6AddressOpValue(MI, `1`, Fixups, STI);
11758	op &= UINT64_C(`15`);
11759	op <<= `16`;
11760	Value \|= op;
11761	// op: Rm
11762	op = getAddrMode6OffsetOpValue(MI, `3`, Fixups, STI);
11763	op &= UINT64_C(`15`);
11764	Value \|= op;
11765	// op: lane
11766	op = getMachineOpValue(MI, MI.getOperand(`5`), Fixups, STI);
11767	op &= UINT64_C(`7`);
11768	op <<= `5`;
11769	Value \|= op;
11770	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11771	break;
11772	}
11773	case ARM::VST3LNd32_UPD:
11774	case ARM::VST3LNq32_UPD: {
11775	// op: Vd
11776	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
11777	Value \|= (op & UINT64_C(`16`)) << `18`;
11778	Value \|= (op & UINT64_C(`15`)) << `12`;
11779	// op: Rn
11780	op = getAddrMode6AddressOpValue(MI, `1`, Fixups, STI);
11781	op &= UINT64_C(`15`);
11782	op <<= `16`;
11783	Value \|= op;
11784	// op: Rm
11785	op = getAddrMode6OffsetOpValue(MI, `3`, Fixups, STI);
11786	op &= UINT64_C(`15`);
11787	Value \|= op;
11788	// op: lane
11789	op = getMachineOpValue(MI, MI.getOperand(`7`), Fixups, STI);
11790	op &= UINT64_C(`1`);
11791	op <<= `7`;
11792	Value \|= op;
11793	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11794	break;
11795	}
11796	case ARM::VST3LNd16_UPD:
11797	case ARM::VST3LNq16_UPD: {
11798	// op: Vd
11799	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
11800	Value \|= (op & UINT64_C(`16`)) << `18`;
11801	Value \|= (op & UINT64_C(`15`)) << `12`;
11802	// op: Rn
11803	op = getAddrMode6AddressOpValue(MI, `1`, Fixups, STI);
11804	op &= UINT64_C(`15`);
11805	op <<= `16`;
11806	Value \|= op;
11807	// op: Rm
11808	op = getAddrMode6OffsetOpValue(MI, `3`, Fixups, STI);
11809	op &= UINT64_C(`15`);
11810	Value \|= op;
11811	// op: lane
11812	op = getMachineOpValue(MI, MI.getOperand(`7`), Fixups, STI);
11813	op &= UINT64_C(`3`);
11814	op <<= `6`;
11815	Value \|= op;
11816	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11817	break;
11818	}
11819	case ARM::VST3LNd8_UPD: {
11820	// op: Vd
11821	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
11822	Value \|= (op & UINT64_C(`16`)) << `18`;
11823	Value \|= (op & UINT64_C(`15`)) << `12`;
11824	// op: Rn
11825	op = getAddrMode6AddressOpValue(MI, `1`, Fixups, STI);
11826	op &= UINT64_C(`15`);
11827	op <<= `16`;
11828	Value \|= op;
11829	// op: Rm
11830	op = getAddrMode6OffsetOpValue(MI, `3`, Fixups, STI);
11831	op &= UINT64_C(`15`);
11832	Value \|= op;
11833	// op: lane
11834	op = getMachineOpValue(MI, MI.getOperand(`7`), Fixups, STI);
11835	op &= UINT64_C(`7`);
11836	op <<= `5`;
11837	Value \|= op;
11838	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11839	break;
11840	}
11841	case ARM::VST1LNd32_UPD: {
11842	// op: Vd
11843	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
11844	Value \|= (op & UINT64_C(`16`)) << `18`;
11845	Value \|= (op & UINT64_C(`15`)) << `12`;
11846	// op: Rn
11847	op = getAddrMode6OneLane32AddressOpValue(MI, `1`, Fixups, STI);
11848	Value \|= (op & UINT64_C(`15`)) << `16`;
11849	Value \|= (op & UINT64_C(`48`));
11850	// op: Rm
11851	op = getAddrMode6OffsetOpValue(MI, `3`, Fixups, STI);
11852	op &= UINT64_C(`15`);
11853	Value \|= op;
11854	// op: lane
11855	op = getMachineOpValue(MI, MI.getOperand(`5`), Fixups, STI);
11856	op &= UINT64_C(`1`);
11857	op <<= `7`;
11858	Value \|= op;
11859	Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
11860	break;
11861	}
11862	case ARM::LDC2L_OFFSET:
11863	case ARM::LDC2L_PRE:
11864	case ARM::LDC2_OFFSET:
11865	case ARM::LDC2_PRE:
11866	case ARM::STC2L_OFFSET:
11867	case ARM::STC2L_PRE:
11868	case ARM::STC2_OFFSET:
11869	case ARM::STC2_PRE:
11870	case ARM::t2LDC2L_OFFSET:
11871	case ARM::t2LDC2L_PRE:
11872	case ARM::t2LDC2_OFFSET:
11873	case ARM::t2LDC2_PRE:
11874	case ARM::t2LDCL_OFFSET:
11875	case ARM::t2LDCL_PRE:
11876	case ARM::t2LDC_OFFSET:
11877	case ARM::t2LDC_PRE:
11878	case ARM::t2STC2L_OFFSET:
11879	case ARM::t2STC2L_PRE:
11880	case ARM::t2STC2_OFFSET:
11881	case ARM::t2STC2_PRE:
11882	case ARM::t2STCL_OFFSET:
11883	case ARM::t2STCL_PRE:
11884	case ARM::t2STC_OFFSET:
11885	case ARM::t2STC_PRE: {
11886	// op: addr
11887	op = getAddrMode5OpValue(MI, `2`, Fixups, STI);
11888	Value \|= (op & UINT64_C(`256`)) << `15`;
11889	Value \|= (op & UINT64_C(`7680`)) << `7`;
11890	Value \|= (op & UINT64_C(`255`));
11891	// op: cop
11892	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
11893	op &= UINT64_C(`15`);
11894	op <<= `8`;
11895	Value \|= op;
11896	// op: CRd
11897	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
11898	op &= UINT64_C(`15`);
11899	op <<= `12`;
11900	Value \|= op;
11901	break;
11902	}
11903	case ARM::t2PLDWi12:
11904	case ARM::t2PLDi12:
11905	case ARM::t2PLIi12: {
11906	// op: addr
11907	op = getAddrModeImm12OpValue(MI, `0`, Fixups, STI);
11908	Value \|= (op & UINT64_C(`122880`)) << `3`;
11909	Value \|= (op & UINT64_C(`4095`));
11910	break;
11911	}
11912	case ARM::PLDWi12:
11913	case ARM::PLDi12:
11914	case ARM::PLIi12: {
11915	// op: addr
11916	op = getAddrModeImm12OpValue(MI, `0`, Fixups, STI);
11917	Value \|= (op & UINT64_C(`4096`)) << `11`;
11918	Value \|= (op & UINT64_C(`122880`)) << `3`;
11919	Value \|= (op & UINT64_C(`4095`));
11920	break;
11921	}
11922	case ARM::t2PLDpci:
11923	case ARM::t2PLIpci: {
11924	// op: addr
11925	op = getAddrModeImm12OpValue(MI, `0`, Fixups, STI);
11926	Value \|= (op & UINT64_C(`4096`)) << `11`;
11927	Value \|= (op & UINT64_C(`4095`));
11928	break;
11929	}
11930	case ARM::t2LDAEXB:
11931	case ARM::t2LDAEXH:
11932	case ARM::t2LDREXB:
11933	case ARM::t2LDREXH: {
11934	// op: addr
11935	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
11936	op &= UINT64_C(`15`);
11937	op <<= `16`;
11938	Value \|= op;
11939	// op: Rt
11940	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
11941	op &= UINT64_C(`15`);
11942	op <<= `12`;
11943	Value \|= op;
11944	break;
11945	}
11946	case ARM::t2LDAEXD:
11947	case ARM::t2LDREXD: {
11948	// op: addr
11949	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
11950	op &= UINT64_C(`15`);
11951	op <<= `16`;
11952	Value \|= op;
11953	// op: Rt
11954	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
11955	op &= UINT64_C(`15`);
11956	op <<= `12`;
11957	Value \|= op;
11958	// op: Rt2
11959	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
11960	op &= UINT64_C(`15`);
11961	op <<= `8`;
11962	Value \|= op;
11963	break;
11964	}
11965	case ARM::t2PLDWi8:
11966	case ARM::t2PLDi8:
11967	case ARM::t2PLIi8: {
11968	// op: addr
11969	op = getT2AddrModeImmOpValue<`8`,`0`>(MI, `0`, Fixups, STI);
11970	Value \|= (op & UINT64_C(`7680`)) << `7`;
11971	Value \|= (op & UINT64_C(`255`));
11972	break;
11973	}
11974	case ARM::t2PLDWs:
11975	case ARM::t2PLDs:
11976	case ARM::t2PLIs: {
11977	// op: addr
11978	op = getT2AddrModeSORegOpValue(MI, `0`, Fixups, STI);
11979	Value \|= (op & UINT64_C(`960`)) << `10`;
11980	Value \|= (op & UINT64_C(`3`)) << `4`;
11981	Value \|= (op & UINT64_C(`60`)) >> `2`;
11982	break;
11983	}
11984	case ARM::t2BFLr:
11985	case ARM::t2BFr: {
11986	// op: b_label
11987	op = getBFTargetOpValue<false, ARM::fixup_bf_branch>(MI, `0`, Fixups, STI);
11988	op &= UINT64_C(`15`);
11989	op <<= `23`;
11990	Value \|= op;
11991	// op: Rn
11992	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
11993	op &= UINT64_C(`15`);
11994	op <<= `16`;
11995	Value \|= op;
11996	break;
11997	}
11998	case ARM::t2BFi: {
11999	// op: b_label
12000	op = getBFTargetOpValue<false, ARM::fixup_bf_branch>(MI, `0`, Fixups, STI);
12001	op &= UINT64_C(`15`);
12002	op <<= `23`;
12003	Value \|= op;
12004	// op: label
12005	op = getBFTargetOpValue<false, ARM::fixup_bf_target>(MI, `1`, Fixups, STI);
12006	Value \|= (op & UINT64_C(`63488`)) << `5`;
12007	Value \|= (op & UINT64_C(`1`)) << `11`;
12008	Value \|= (op & UINT64_C(`2046`));
12009	break;
12010	}
12011	case ARM::t2BFLi: {
12012	// op: b_label
12013	op = getBFTargetOpValue<false, ARM::fixup_bf_branch>(MI, `0`, Fixups, STI);
12014	op &= UINT64_C(`15`);
12015	op <<= `23`;
12016	Value \|= op;
12017	// op: label
12018	op = getBFTargetOpValue<false, ARM::fixup_bfl_target>(MI, `1`, Fixups, STI);
12019	Value \|= (op & UINT64_C(`260096`)) << `5`;
12020	Value \|= (op & UINT64_C(`1`)) << `11`;
12021	Value \|= (op & UINT64_C(`2046`));
12022	break;
12023	}
12024	case ARM::t2MSRbanked: {
12025	// op: banked
12026	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12027	Value \|= (op & UINT64_C(`32`)) << `15`;
12028	Value \|= (op & UINT64_C(`15`)) << `8`;
12029	Value \|= (op & UINT64_C(`16`));
12030	// op: Rn
12031	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12032	op &= UINT64_C(`15`);
12033	op <<= `16`;
12034	Value \|= op;
12035	break;
12036	}
12037	case ARM::t2MRSbanked: {
12038	// op: banked
12039	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12040	Value \|= (op & UINT64_C(`32`)) << `15`;
12041	Value \|= (op & UINT64_C(`15`)) << `16`;
12042	Value \|= (op & UINT64_C(`16`));
12043	// op: Rd
12044	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12045	op &= UINT64_C(`15`);
12046	op <<= `8`;
12047	Value \|= op;
12048	break;
12049	}
12050	case ARM::t2BFic: {
12051	// op: bcond
12052	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
12053	op &= UINT64_C(`15`);
12054	op <<= `18`;
12055	Value \|= op;
12056	// op: label
12057	op = getBFTargetOpValue<false, ARM::fixup_bfc_target>(MI, `1`, Fixups, STI);
12058	Value \|= (op & UINT64_C(`2048`)) << `5`;
12059	Value \|= (op & UINT64_C(`1`)) << `11`;
12060	Value \|= (op & UINT64_C(`2046`));
12061	// op: ba_label
12062	op = getBFAfterTargetOpValue(MI, `2`, Fixups, STI);
12063	op &= UINT64_C(`1`);
12064	op <<= `17`;
12065	Value \|= op;
12066	// op: b_label
12067	op = getBFTargetOpValue<false, ARM::fixup_bf_branch>(MI, `0`, Fixups, STI);
12068	op &= UINT64_C(`15`);
12069	op <<= `23`;
12070	Value \|= op;
12071	break;
12072	}
12073	case ARM::t2IT: {
12074	// op: cc
12075	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12076	op &= UINT64_C(`15`);
12077	op <<= `4`;
12078	Value \|= op;
12079	// op: mask
12080	op = getITMaskOpValue(MI, `1`, Fixups, STI);
12081	op &= UINT64_C(`15`);
12082	Value \|= op;
12083	break;
12084	}
12085	case ARM::CDE_VCX1_fpsp: {
12086	// op: coproc
12087	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12088	op &= UINT64_C(`7`);
12089	op <<= `8`;
12090	Value \|= op;
12091	// op: imm
12092	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
12093	Value \|= (op & UINT64_C(`1920`)) << `9`;
12094	Value \|= (op & UINT64_C(`64`)) << `1`;
12095	Value \|= (op & UINT64_C(`63`));
12096	// op: Vd
12097	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12098	Value \|= (op & UINT64_C(`1`)) << `22`;
12099	Value \|= (op & UINT64_C(`30`)) << `11`;
12100	break;
12101	}
12102	case ARM::CDE_VCX1_fpdp: {
12103	// op: coproc
12104	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12105	op &= UINT64_C(`7`);
12106	op <<= `8`;
12107	Value \|= op;
12108	// op: imm
12109	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
12110	Value \|= (op & UINT64_C(`1920`)) << `9`;
12111	Value \|= (op & UINT64_C(`64`)) << `1`;
12112	Value \|= (op & UINT64_C(`63`));
12113	// op: Vd
12114	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12115	Value \|= (op & UINT64_C(`16`)) << `18`;
12116	Value \|= (op & UINT64_C(`15`)) << `12`;
12117	break;
12118	}
12119	case ARM::CDE_VCX1_vec: {
12120	// op: coproc
12121	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12122	op &= UINT64_C(`7`);
12123	op <<= `8`;
12124	Value \|= op;
12125	// op: imm
12126	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
12127	Value \|= (op & UINT64_C(`2048`)) << `13`;
12128	Value \|= (op & UINT64_C(`1920`)) << `9`;
12129	Value \|= (op & UINT64_C(`64`)) << `1`;
12130	Value \|= (op & UINT64_C(`63`));
12131	// op: Qd
12132	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12133	op &= UINT64_C(`7`);
12134	op <<= `13`;
12135	Value \|= op;
12136	break;
12137	}
12138	case ARM::CDE_CX1:
12139	case ARM::CDE_CX1D: {
12140	// op: coproc
12141	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12142	op &= UINT64_C(`7`);
12143	op <<= `8`;
12144	Value \|= op;
12145	// op: imm
12146	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
12147	Value \|= (op & UINT64_C(`8064`)) << `9`;
12148	Value \|= (op & UINT64_C(`64`)) << `1`;
12149	Value \|= (op & UINT64_C(`63`));
12150	// op: Rd
12151	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12152	op &= UINT64_C(`15`);
12153	op <<= `12`;
12154	Value \|= op;
12155	break;
12156	}
12157	case ARM::CDE_VCX1A_fpsp: {
12158	// op: coproc
12159	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12160	op &= UINT64_C(`7`);
12161	op <<= `8`;
12162	Value \|= op;
12163	// op: imm
12164	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
12165	Value \|= (op & UINT64_C(`1920`)) << `9`;
12166	Value \|= (op & UINT64_C(`64`)) << `1`;
12167	Value \|= (op & UINT64_C(`63`));
12168	// op: Vd
12169	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12170	Value \|= (op & UINT64_C(`1`)) << `22`;
12171	Value \|= (op & UINT64_C(`30`)) << `11`;
12172	break;
12173	}
12174	case ARM::CDE_VCX1A_fpdp: {
12175	// op: coproc
12176	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12177	op &= UINT64_C(`7`);
12178	op <<= `8`;
12179	Value \|= op;
12180	// op: imm
12181	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
12182	Value \|= (op & UINT64_C(`1920`)) << `9`;
12183	Value \|= (op & UINT64_C(`64`)) << `1`;
12184	Value \|= (op & UINT64_C(`63`));
12185	// op: Vd
12186	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12187	Value \|= (op & UINT64_C(`16`)) << `18`;
12188	Value \|= (op & UINT64_C(`15`)) << `12`;
12189	break;
12190	}
12191	case ARM::CDE_VCX1A_vec: {
12192	// op: coproc
12193	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12194	op &= UINT64_C(`7`);
12195	op <<= `8`;
12196	Value \|= op;
12197	// op: imm
12198	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
12199	Value \|= (op & UINT64_C(`2048`)) << `13`;
12200	Value \|= (op & UINT64_C(`1920`)) << `9`;
12201	Value \|= (op & UINT64_C(`64`)) << `1`;
12202	Value \|= (op & UINT64_C(`63`));
12203	// op: Qd
12204	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12205	op &= UINT64_C(`7`);
12206	op <<= `13`;
12207	Value \|= op;
12208	break;
12209	}
12210	case ARM::CDE_CX2:
12211	case ARM::CDE_CX2D: {
12212	// op: coproc
12213	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12214	op &= UINT64_C(`7`);
12215	op <<= `8`;
12216	Value \|= op;
12217	// op: imm
12218	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
12219	Value \|= (op & UINT64_C(`384`)) << `13`;
12220	Value \|= (op & UINT64_C(`64`)) << `1`;
12221	Value \|= (op & UINT64_C(`63`));
12222	// op: Rd
12223	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12224	op &= UINT64_C(`15`);
12225	op <<= `12`;
12226	Value \|= op;
12227	// op: Rn
12228	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
12229	op &= UINT64_C(`15`);
12230	op <<= `16`;
12231	Value \|= op;
12232	break;
12233	}
12234	case ARM::CDE_VCX2_fpsp: {
12235	// op: coproc
12236	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12237	op &= UINT64_C(`7`);
12238	op <<= `8`;
12239	Value \|= op;
12240	// op: imm
12241	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
12242	Value \|= (op & UINT64_C(`60`)) << `14`;
12243	Value \|= (op & UINT64_C(`2`)) << `6`;
12244	Value \|= (op & UINT64_C(`1`)) << `4`;
12245	// op: Vd
12246	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12247	Value \|= (op & UINT64_C(`1`)) << `22`;
12248	Value \|= (op & UINT64_C(`30`)) << `11`;
12249	// op: Vm
12250	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
12251	Value \|= (op & UINT64_C(`1`)) << `5`;
12252	Value \|= (op & UINT64_C(`30`)) >> `1`;
12253	break;
12254	}
12255	case ARM::CDE_VCX2_fpdp: {
12256	// op: coproc
12257	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12258	op &= UINT64_C(`7`);
12259	op <<= `8`;
12260	Value \|= op;
12261	// op: imm
12262	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
12263	Value \|= (op & UINT64_C(`60`)) << `14`;
12264	Value \|= (op & UINT64_C(`2`)) << `6`;
12265	Value \|= (op & UINT64_C(`1`)) << `4`;
12266	// op: Vd
12267	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12268	Value \|= (op & UINT64_C(`16`)) << `18`;
12269	Value \|= (op & UINT64_C(`15`)) << `12`;
12270	// op: Vm
12271	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
12272	Value \|= (op & UINT64_C(`16`)) << `1`;
12273	Value \|= (op & UINT64_C(`15`));
12274	break;
12275	}
12276	case ARM::CDE_VCX2_vec: {
12277	// op: coproc
12278	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12279	op &= UINT64_C(`7`);
12280	op <<= `8`;
12281	Value \|= op;
12282	// op: imm
12283	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
12284	Value \|= (op & UINT64_C(`64`)) << `18`;
12285	Value \|= (op & UINT64_C(`60`)) << `14`;
12286	Value \|= (op & UINT64_C(`2`)) << `6`;
12287	Value \|= (op & UINT64_C(`1`)) << `4`;
12288	// op: Qd
12289	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12290	op &= UINT64_C(`7`);
12291	op <<= `13`;
12292	Value \|= op;
12293	// op: Qm
12294	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
12295	op &= UINT64_C(`7`);
12296	op <<= `1`;
12297	Value \|= op;
12298	break;
12299	}
12300	case ARM::CDE_CX1A:
12301	case ARM::CDE_CX1DA: {
12302	// op: coproc
12303	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12304	op &= UINT64_C(`7`);
12305	op <<= `8`;
12306	Value \|= op;
12307	// op: imm
12308	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
12309	Value \|= (op & UINT64_C(`8064`)) << `9`;
12310	Value \|= (op & UINT64_C(`64`)) << `1`;
12311	Value \|= (op & UINT64_C(`63`));
12312	// op: Rd
12313	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12314	op &= UINT64_C(`15`);
12315	op <<= `12`;
12316	Value \|= op;
12317	break;
12318	}
12319	case ARM::CDE_CX2A:
12320	case ARM::CDE_CX2DA: {
12321	// op: coproc
12322	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12323	op &= UINT64_C(`7`);
12324	op <<= `8`;
12325	Value \|= op;
12326	// op: imm
12327	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
12328	Value \|= (op & UINT64_C(`384`)) << `13`;
12329	Value \|= (op & UINT64_C(`64`)) << `1`;
12330	Value \|= (op & UINT64_C(`63`));
12331	// op: Rd
12332	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12333	op &= UINT64_C(`15`);
12334	op <<= `12`;
12335	Value \|= op;
12336	// op: Rn
12337	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
12338	op &= UINT64_C(`15`);
12339	op <<= `16`;
12340	Value \|= op;
12341	break;
12342	}
12343	case ARM::CDE_CX3:
12344	case ARM::CDE_CX3D: {
12345	// op: coproc
12346	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12347	op &= UINT64_C(`7`);
12348	op <<= `8`;
12349	Value \|= op;
12350	// op: imm
12351	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
12352	Value \|= (op & UINT64_C(`56`)) << `17`;
12353	Value \|= (op & UINT64_C(`4`)) << `5`;
12354	Value \|= (op & UINT64_C(`3`)) << `4`;
12355	// op: Rd
12356	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12357	op &= UINT64_C(`15`);
12358	Value \|= op;
12359	// op: Rn
12360	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
12361	op &= UINT64_C(`15`);
12362	op <<= `16`;
12363	Value \|= op;
12364	// op: Rm
12365	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
12366	op &= UINT64_C(`15`);
12367	op <<= `12`;
12368	Value \|= op;
12369	break;
12370	}
12371	case ARM::CDE_VCX3_fpsp: {
12372	// op: coproc
12373	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12374	op &= UINT64_C(`7`);
12375	op <<= `8`;
12376	Value \|= op;
12377	// op: imm
12378	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
12379	Value \|= (op & UINT64_C(`6`)) << `19`;
12380	Value \|= (op & UINT64_C(`1`)) << `4`;
12381	// op: Vd
12382	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12383	Value \|= (op & UINT64_C(`1`)) << `22`;
12384	Value \|= (op & UINT64_C(`30`)) << `11`;
12385	// op: Vm
12386	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
12387	Value \|= (op & UINT64_C(`1`)) << `5`;
12388	Value \|= (op & UINT64_C(`30`)) >> `1`;
12389	// op: Vn
12390	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
12391	Value \|= (op & UINT64_C(`30`)) << `15`;
12392	Value \|= (op & UINT64_C(`1`)) << `7`;
12393	break;
12394	}
12395	case ARM::CDE_VCX3_fpdp: {
12396	// op: coproc
12397	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12398	op &= UINT64_C(`7`);
12399	op <<= `8`;
12400	Value \|= op;
12401	// op: imm
12402	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
12403	Value \|= (op & UINT64_C(`6`)) << `19`;
12404	Value \|= (op & UINT64_C(`1`)) << `4`;
12405	// op: Vd
12406	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12407	Value \|= (op & UINT64_C(`16`)) << `18`;
12408	Value \|= (op & UINT64_C(`15`)) << `12`;
12409	// op: Vm
12410	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
12411	Value \|= (op & UINT64_C(`16`)) << `1`;
12412	Value \|= (op & UINT64_C(`15`));
12413	// op: Vn
12414	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
12415	Value \|= (op & UINT64_C(`15`)) << `16`;
12416	Value \|= (op & UINT64_C(`16`)) << `3`;
12417	break;
12418	}
12419	case ARM::CDE_VCX2A_fpsp: {
12420	// op: coproc
12421	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12422	op &= UINT64_C(`7`);
12423	op <<= `8`;
12424	Value \|= op;
12425	// op: imm
12426	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
12427	Value \|= (op & UINT64_C(`60`)) << `14`;
12428	Value \|= (op & UINT64_C(`2`)) << `6`;
12429	Value \|= (op & UINT64_C(`1`)) << `4`;
12430	// op: Vd
12431	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12432	Value \|= (op & UINT64_C(`1`)) << `22`;
12433	Value \|= (op & UINT64_C(`30`)) << `11`;
12434	// op: Vm
12435	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
12436	Value \|= (op & UINT64_C(`1`)) << `5`;
12437	Value \|= (op & UINT64_C(`30`)) >> `1`;
12438	break;
12439	}
12440	case ARM::CDE_VCX2A_fpdp: {
12441	// op: coproc
12442	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12443	op &= UINT64_C(`7`);
12444	op <<= `8`;
12445	Value \|= op;
12446	// op: imm
12447	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
12448	Value \|= (op & UINT64_C(`60`)) << `14`;
12449	Value \|= (op & UINT64_C(`2`)) << `6`;
12450	Value \|= (op & UINT64_C(`1`)) << `4`;
12451	// op: Vd
12452	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12453	Value \|= (op & UINT64_C(`16`)) << `18`;
12454	Value \|= (op & UINT64_C(`15`)) << `12`;
12455	// op: Vm
12456	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
12457	Value \|= (op & UINT64_C(`16`)) << `1`;
12458	Value \|= (op & UINT64_C(`15`));
12459	break;
12460	}
12461	case ARM::CDE_VCX2A_vec: {
12462	// op: coproc
12463	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12464	op &= UINT64_C(`7`);
12465	op <<= `8`;
12466	Value \|= op;
12467	// op: imm
12468	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
12469	Value \|= (op & UINT64_C(`64`)) << `18`;
12470	Value \|= (op & UINT64_C(`60`)) << `14`;
12471	Value \|= (op & UINT64_C(`2`)) << `6`;
12472	Value \|= (op & UINT64_C(`1`)) << `4`;
12473	// op: Qd
12474	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12475	op &= UINT64_C(`7`);
12476	op <<= `13`;
12477	Value \|= op;
12478	// op: Qm
12479	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
12480	op &= UINT64_C(`7`);
12481	op <<= `1`;
12482	Value \|= op;
12483	break;
12484	}
12485	case ARM::CDE_VCX3_vec: {
12486	// op: coproc
12487	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12488	op &= UINT64_C(`7`);
12489	op <<= `8`;
12490	Value \|= op;
12491	// op: imm
12492	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
12493	Value \|= (op & UINT64_C(`8`)) << `21`;
12494	Value \|= (op & UINT64_C(`6`)) << `19`;
12495	Value \|= (op & UINT64_C(`1`)) << `4`;
12496	// op: Qd
12497	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12498	op &= UINT64_C(`7`);
12499	op <<= `13`;
12500	Value \|= op;
12501	// op: Qm
12502	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
12503	op &= UINT64_C(`7`);
12504	op <<= `1`;
12505	Value \|= op;
12506	// op: Qn
12507	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
12508	op &= UINT64_C(`7`);
12509	op <<= `17`;
12510	Value \|= op;
12511	break;
12512	}
12513	case ARM::CDE_CX3A:
12514	case ARM::CDE_CX3DA: {
12515	// op: coproc
12516	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12517	op &= UINT64_C(`7`);
12518	op <<= `8`;
12519	Value \|= op;
12520	// op: imm
12521	op = getMachineOpValue(MI, MI.getOperand(`5`), Fixups, STI);
12522	Value \|= (op & UINT64_C(`56`)) << `17`;
12523	Value \|= (op & UINT64_C(`4`)) << `5`;
12524	Value \|= (op & UINT64_C(`3`)) << `4`;
12525	// op: Rd
12526	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12527	op &= UINT64_C(`15`);
12528	Value \|= op;
12529	// op: Rn
12530	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
12531	op &= UINT64_C(`15`);
12532	op <<= `16`;
12533	Value \|= op;
12534	// op: Rm
12535	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
12536	op &= UINT64_C(`15`);
12537	op <<= `12`;
12538	Value \|= op;
12539	break;
12540	}
12541	case ARM::CDE_VCX3A_fpsp: {
12542	// op: coproc
12543	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12544	op &= UINT64_C(`7`);
12545	op <<= `8`;
12546	Value \|= op;
12547	// op: imm
12548	op = getMachineOpValue(MI, MI.getOperand(`5`), Fixups, STI);
12549	Value \|= (op & UINT64_C(`6`)) << `19`;
12550	Value \|= (op & UINT64_C(`1`)) << `4`;
12551	// op: Vd
12552	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12553	Value \|= (op & UINT64_C(`1`)) << `22`;
12554	Value \|= (op & UINT64_C(`30`)) << `11`;
12555	// op: Vm
12556	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
12557	Value \|= (op & UINT64_C(`1`)) << `5`;
12558	Value \|= (op & UINT64_C(`30`)) >> `1`;
12559	// op: Vn
12560	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
12561	Value \|= (op & UINT64_C(`30`)) << `15`;
12562	Value \|= (op & UINT64_C(`1`)) << `7`;
12563	break;
12564	}
12565	case ARM::CDE_VCX3A_fpdp: {
12566	// op: coproc
12567	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12568	op &= UINT64_C(`7`);
12569	op <<= `8`;
12570	Value \|= op;
12571	// op: imm
12572	op = getMachineOpValue(MI, MI.getOperand(`5`), Fixups, STI);
12573	Value \|= (op & UINT64_C(`6`)) << `19`;
12574	Value \|= (op & UINT64_C(`1`)) << `4`;
12575	// op: Vd
12576	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12577	Value \|= (op & UINT64_C(`16`)) << `18`;
12578	Value \|= (op & UINT64_C(`15`)) << `12`;
12579	// op: Vm
12580	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
12581	Value \|= (op & UINT64_C(`16`)) << `1`;
12582	Value \|= (op & UINT64_C(`15`));
12583	// op: Vn
12584	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
12585	Value \|= (op & UINT64_C(`15`)) << `16`;
12586	Value \|= (op & UINT64_C(`16`)) << `3`;
12587	break;
12588	}
12589	case ARM::CDE_VCX3A_vec: {
12590	// op: coproc
12591	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12592	op &= UINT64_C(`7`);
12593	op <<= `8`;
12594	Value \|= op;
12595	// op: imm
12596	op = getMachineOpValue(MI, MI.getOperand(`5`), Fixups, STI);
12597	Value \|= (op & UINT64_C(`8`)) << `21`;
12598	Value \|= (op & UINT64_C(`6`)) << `19`;
12599	Value \|= (op & UINT64_C(`1`)) << `4`;
12600	// op: Qd
12601	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12602	op &= UINT64_C(`7`);
12603	op <<= `13`;
12604	Value \|= op;
12605	// op: Qm
12606	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
12607	op &= UINT64_C(`7`);
12608	op <<= `1`;
12609	Value \|= op;
12610	// op: Qn
12611	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
12612	op &= UINT64_C(`7`);
12613	op <<= `17`;
12614	Value \|= op;
12615	break;
12616	}
12617	case ARM::BX: {
12618	// op: dst
12619	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12620	op &= UINT64_C(`15`);
12621	Value \|= op;
12622	break;
12623	}
12624	case ARM::tPICADD: {
12625	// op: dst
12626	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12627	op &= UINT64_C(`7`);
12628	Value \|= op;
12629	break;
12630	}
12631	case ARM::tADDrSPi: {
12632	// op: dst
12633	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12634	op &= UINT64_C(`7`);
12635	op <<= `8`;
12636	Value \|= op;
12637	// op: imm
12638	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
12639	op &= UINT64_C(`255`);
12640	Value \|= op;
12641	break;
12642	}
12643	case ARM::tSETEND: {
12644	// op: end
12645	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12646	op &= UINT64_C(`1`);
12647	op <<= `3`;
12648	Value \|= op;
12649	break;
12650	}
12651	case ARM::SETEND: {
12652	// op: end
12653	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12654	op &= UINT64_C(`1`);
12655	op <<= `9`;
12656	Value \|= op;
12657	break;
12658	}
12659	case ARM::MVE_VPTv16s8r:
12660	case ARM::MVE_VPTv4s32r:
12661	case ARM::MVE_VPTv8s16r: {
12662	// op: fc
12663	op = getRestrictedCondCodeOpValue(MI, `3`, Fixups, STI);
12664	Value \|= (op & UINT64_C(`1`)) << `7`;
12665	Value \|= (op & UINT64_C(`2`)) << `4`;
12666	// op: Mk
12667	op = getVPTMaskOpValue(MI, `0`, Fixups, STI);
12668	Value \|= (op & UINT64_C(`8`)) << `19`;
12669	Value \|= (op & UINT64_C(`7`)) << `13`;
12670	// op: Qn
12671	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12672	op &= UINT64_C(`7`);
12673	op <<= `17`;
12674	Value \|= op;
12675	// op: Rm
12676	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
12677	op &= UINT64_C(`15`);
12678	Value \|= op;
12679	break;
12680	}
12681	case ARM::MVE_VCMPs16r:
12682	case ARM::MVE_VCMPs32r:
12683	case ARM::MVE_VCMPs8r: {
12684	// op: fc
12685	op = getRestrictedCondCodeOpValue(MI, `3`, Fixups, STI);
12686	Value \|= (op & UINT64_C(`1`)) << `7`;
12687	Value \|= (op & UINT64_C(`2`)) << `4`;
12688	// op: Qn
12689	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12690	op &= UINT64_C(`7`);
12691	op <<= `17`;
12692	Value \|= op;
12693	// op: Rm
12694	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
12695	op &= UINT64_C(`15`);
12696	Value \|= op;
12697	break;
12698	}
12699	case ARM::MVE_VPTv16s8:
12700	case ARM::MVE_VPTv4s32:
12701	case ARM::MVE_VPTv8s16: {
12702	// op: fc
12703	op = getRestrictedCondCodeOpValue(MI, `3`, Fixups, STI);
12704	Value \|= (op & UINT64_C(`1`)) << `7`;
12705	Value \|= (op & UINT64_C(`2`)) >> `1`;
12706	// op: Mk
12707	op = getVPTMaskOpValue(MI, `0`, Fixups, STI);
12708	Value \|= (op & UINT64_C(`8`)) << `19`;
12709	Value \|= (op & UINT64_C(`7`)) << `13`;
12710	// op: Qn
12711	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12712	op &= UINT64_C(`7`);
12713	op <<= `17`;
12714	Value \|= op;
12715	// op: Qm
12716	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
12717	Value \|= (op & UINT64_C(`8`)) << `2`;
12718	Value \|= (op & UINT64_C(`7`)) << `1`;
12719	break;
12720	}
12721	case ARM::MVE_VCMPs16:
12722	case ARM::MVE_VCMPs32:
12723	case ARM::MVE_VCMPs8: {
12724	// op: fc
12725	op = getRestrictedCondCodeOpValue(MI, `3`, Fixups, STI);
12726	Value \|= (op & UINT64_C(`1`)) << `7`;
12727	Value \|= (op & UINT64_C(`2`)) >> `1`;
12728	// op: Qn
12729	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12730	op &= UINT64_C(`7`);
12731	op <<= `17`;
12732	Value \|= op;
12733	// op: Qm
12734	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
12735	Value \|= (op & UINT64_C(`8`)) << `2`;
12736	Value \|= (op & UINT64_C(`7`)) << `1`;
12737	break;
12738	}
12739	case ARM::MVE_VPTv4f32r:
12740	case ARM::MVE_VPTv8f16r: {
12741	// op: fc
12742	op = getRestrictedCondCodeOpValue(MI, `3`, Fixups, STI);
12743	Value \|= (op & UINT64_C(`4`)) << `10`;
12744	Value \|= (op & UINT64_C(`1`)) << `7`;
12745	Value \|= (op & UINT64_C(`2`)) << `4`;
12746	// op: Mk
12747	op = getVPTMaskOpValue(MI, `0`, Fixups, STI);
12748	Value \|= (op & UINT64_C(`8`)) << `19`;
12749	Value \|= (op & UINT64_C(`7`)) << `13`;
12750	// op: Qn
12751	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12752	op &= UINT64_C(`7`);
12753	op <<= `17`;
12754	Value \|= op;
12755	// op: Rm
12756	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
12757	op &= UINT64_C(`15`);
12758	Value \|= op;
12759	break;
12760	}
12761	case ARM::MVE_VCMPf16r:
12762	case ARM::MVE_VCMPf32r: {
12763	// op: fc
12764	op = getRestrictedCondCodeOpValue(MI, `3`, Fixups, STI);
12765	Value \|= (op & UINT64_C(`4`)) << `10`;
12766	Value \|= (op & UINT64_C(`1`)) << `7`;
12767	Value \|= (op & UINT64_C(`2`)) << `4`;
12768	// op: Qn
12769	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12770	op &= UINT64_C(`7`);
12771	op <<= `17`;
12772	Value \|= op;
12773	// op: Rm
12774	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
12775	op &= UINT64_C(`15`);
12776	Value \|= op;
12777	break;
12778	}
12779	case ARM::MVE_VPTv4f32:
12780	case ARM::MVE_VPTv8f16: {
12781	// op: fc
12782	op = getRestrictedCondCodeOpValue(MI, `3`, Fixups, STI);
12783	Value \|= (op & UINT64_C(`4`)) << `10`;
12784	Value \|= (op & UINT64_C(`1`)) << `7`;
12785	Value \|= (op & UINT64_C(`2`)) >> `1`;
12786	// op: Mk
12787	op = getVPTMaskOpValue(MI, `0`, Fixups, STI);
12788	Value \|= (op & UINT64_C(`8`)) << `19`;
12789	Value \|= (op & UINT64_C(`7`)) << `13`;
12790	// op: Qn
12791	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12792	op &= UINT64_C(`7`);
12793	op <<= `17`;
12794	Value \|= op;
12795	// op: Qm
12796	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
12797	Value \|= (op & UINT64_C(`8`)) << `2`;
12798	Value \|= (op & UINT64_C(`7`)) << `1`;
12799	break;
12800	}
12801	case ARM::MVE_VCMPf16:
12802	case ARM::MVE_VCMPf32: {
12803	// op: fc
12804	op = getRestrictedCondCodeOpValue(MI, `3`, Fixups, STI);
12805	Value \|= (op & UINT64_C(`4`)) << `10`;
12806	Value \|= (op & UINT64_C(`1`)) << `7`;
12807	Value \|= (op & UINT64_C(`2`)) >> `1`;
12808	// op: Qn
12809	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12810	op &= UINT64_C(`7`);
12811	op <<= `17`;
12812	Value \|= op;
12813	// op: Qm
12814	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
12815	Value \|= (op & UINT64_C(`8`)) << `2`;
12816	Value \|= (op & UINT64_C(`7`)) << `1`;
12817	break;
12818	}
12819	case ARM::MVE_VPTv16i8:
12820	case ARM::MVE_VPTv16u8:
12821	case ARM::MVE_VPTv4i32:
12822	case ARM::MVE_VPTv4u32:
12823	case ARM::MVE_VPTv8i16:
12824	case ARM::MVE_VPTv8u16: {
12825	// op: fc
12826	op = getRestrictedCondCodeOpValue(MI, `3`, Fixups, STI);
12827	op &= UINT64_C(`1`);
12828	op <<= `7`;
12829	Value \|= op;
12830	// op: Mk
12831	op = getVPTMaskOpValue(MI, `0`, Fixups, STI);
12832	Value \|= (op & UINT64_C(`8`)) << `19`;
12833	Value \|= (op & UINT64_C(`7`)) << `13`;
12834	// op: Qn
12835	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12836	op &= UINT64_C(`7`);
12837	op <<= `17`;
12838	Value \|= op;
12839	// op: Qm
12840	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
12841	Value \|= (op & UINT64_C(`8`)) << `2`;
12842	Value \|= (op & UINT64_C(`7`)) << `1`;
12843	break;
12844	}
12845	case ARM::MVE_VPTv16i8r:
12846	case ARM::MVE_VPTv16u8r:
12847	case ARM::MVE_VPTv4i32r:
12848	case ARM::MVE_VPTv4u32r:
12849	case ARM::MVE_VPTv8i16r:
12850	case ARM::MVE_VPTv8u16r: {
12851	// op: fc
12852	op = getRestrictedCondCodeOpValue(MI, `3`, Fixups, STI);
12853	op &= UINT64_C(`1`);
12854	op <<= `7`;
12855	Value \|= op;
12856	// op: Mk
12857	op = getVPTMaskOpValue(MI, `0`, Fixups, STI);
12858	Value \|= (op & UINT64_C(`8`)) << `19`;
12859	Value \|= (op & UINT64_C(`7`)) << `13`;
12860	// op: Qn
12861	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12862	op &= UINT64_C(`7`);
12863	op <<= `17`;
12864	Value \|= op;
12865	// op: Rm
12866	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
12867	op &= UINT64_C(`15`);
12868	Value \|= op;
12869	break;
12870	}
12871	case ARM::MVE_VCMPi16:
12872	case ARM::MVE_VCMPi32:
12873	case ARM::MVE_VCMPi8:
12874	case ARM::MVE_VCMPu16:
12875	case ARM::MVE_VCMPu32:
12876	case ARM::MVE_VCMPu8: {
12877	// op: fc
12878	op = getRestrictedCondCodeOpValue(MI, `3`, Fixups, STI);
12879	op &= UINT64_C(`1`);
12880	op <<= `7`;
12881	Value \|= op;
12882	// op: Qn
12883	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12884	op &= UINT64_C(`7`);
12885	op <<= `17`;
12886	Value \|= op;
12887	// op: Qm
12888	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
12889	Value \|= (op & UINT64_C(`8`)) << `2`;
12890	Value \|= (op & UINT64_C(`7`)) << `1`;
12891	break;
12892	}
12893	case ARM::MVE_VCMPi16r:
12894	case ARM::MVE_VCMPi32r:
12895	case ARM::MVE_VCMPi8r:
12896	case ARM::MVE_VCMPu16r:
12897	case ARM::MVE_VCMPu32r:
12898	case ARM::MVE_VCMPu8r: {
12899	// op: fc
12900	op = getRestrictedCondCodeOpValue(MI, `3`, Fixups, STI);
12901	op &= UINT64_C(`1`);
12902	op <<= `7`;
12903	Value \|= op;
12904	// op: Qn
12905	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
12906	op &= UINT64_C(`7`);
12907	op <<= `17`;
12908	Value \|= op;
12909	// op: Rm
12910	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
12911	op &= UINT64_C(`15`);
12912	Value \|= op;
12913	break;
12914	}
12915	case ARM::BL: {
12916	// op: func
12917	op = getARMBLTargetOpValue(MI, `0`, Fixups, STI);
12918	op &= UINT64_C(`16777215`);
12919	Value \|= op;
12920	break;
12921	}
12922	case ARM::BLX: {
12923	// op: func
12924	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12925	op &= UINT64_C(`15`);
12926	Value \|= op;
12927	break;
12928	}
12929	case ARM::t2BXJ: {
12930	// op: func
12931	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12932	op &= UINT64_C(`15`);
12933	op <<= `16`;
12934	Value \|= op;
12935	break;
12936	}
12937	case ARM::tBLXNSr:
12938	case ARM::tBLXr: {
12939	// op: func
12940	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
12941	op &= UINT64_C(`15`);
12942	op <<= `3`;
12943	Value \|= op;
12944	break;
12945	}
12946	case ARM::tBL: {
12947	// op: func
12948	op = getThumbBLTargetOpValue(MI, `2`, Fixups, STI);
12949	Value \|= (op & UINT64_C(`8388608`)) << `3`;
12950	Value \|= (op & UINT64_C(`2095104`)) << `5`;
12951	Value \|= (op & UINT64_C(`4194304`)) >> `9`;
12952	Value \|= (op & UINT64_C(`2097152`)) >> `10`;
12953	Value \|= (op & UINT64_C(`2047`));
12954	break;
12955	}
12956	case ARM::tBLXi: {
12957	// op: func
12958	op = getThumbBLXTargetOpValue(MI, `2`, Fixups, STI);
12959	Value \|= (op & UINT64_C(`8388608`)) << `3`;
12960	Value \|= (op & UINT64_C(`2095104`)) << `5`;
12961	Value \|= (op & UINT64_C(`4194304`)) >> `9`;
12962	Value \|= (op & UINT64_C(`2097152`)) >> `10`;
12963	Value \|= (op & UINT64_C(`2046`));
12964	break;
12965	}
12966	case ARM::HVC: {
12967	// op: imm
12968	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12969	Value \|= (op & UINT64_C(`65520`)) << `4`;
12970	Value \|= (op & UINT64_C(`15`));
12971	break;
12972	}
12973	case ARM::t2SETPAN: {
12974	// op: imm
12975	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12976	op &= UINT64_C(`1`);
12977	op <<= `3`;
12978	Value \|= op;
12979	break;
12980	}
12981	case ARM::SETPAN: {
12982	// op: imm
12983	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12984	op &= UINT64_C(`1`);
12985	op <<= `9`;
12986	Value \|= op;
12987	break;
12988	}
12989	case ARM::tHINT: {
12990	// op: imm
12991	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
12992	op &= UINT64_C(`15`);
12993	op <<= `4`;
12994	Value \|= op;
12995	break;
12996	}
12997	case ARM::t2HINT:
12998	case ARM::t2SUBS_PC_LR:
12999	case ARM::tSVC: {
13000	// op: imm
13001	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13002	op &= UINT64_C(`255`);
13003	Value \|= op;
13004	break;
13005	}
13006	case ARM::MVE_VMOVimmf32:
13007	case ARM::MVE_VMOVimmi64:
13008	case ARM::MVE_VMOVimmi8: {
13009	// op: imm
13010	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13011	Value \|= (op & UINT64_C(`128`)) << `21`;
13012	Value \|= (op & UINT64_C(`112`)) << `12`;
13013	Value \|= (op & UINT64_C(`15`));
13014	// op: Qd
13015	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13016	Value \|= (op & UINT64_C(`8`)) << `19`;
13017	Value \|= (op & UINT64_C(`7`)) << `13`;
13018	break;
13019	}
13020	case ARM::MVE_VMOVimmi32:
13021	case ARM::MVE_VMVNimmi32: {
13022	// op: imm
13023	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13024	Value \|= (op & UINT64_C(`128`)) << `21`;
13025	Value \|= (op & UINT64_C(`112`)) << `12`;
13026	Value \|= (op & UINT64_C(`3840`));
13027	Value \|= (op & UINT64_C(`15`));
13028	// op: Qd
13029	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13030	Value \|= (op & UINT64_C(`8`)) << `19`;
13031	Value \|= (op & UINT64_C(`7`)) << `13`;
13032	break;
13033	}
13034	case ARM::MVE_VMOVimmi16:
13035	case ARM::MVE_VMVNimmi16: {
13036	// op: imm
13037	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13038	Value \|= (op & UINT64_C(`128`)) << `21`;
13039	Value \|= (op & UINT64_C(`112`)) << `12`;
13040	Value \|= (op & UINT64_C(`512`));
13041	Value \|= (op & UINT64_C(`15`));
13042	// op: Qd
13043	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13044	Value \|= (op & UINT64_C(`8`)) << `19`;
13045	Value \|= (op & UINT64_C(`7`)) << `13`;
13046	break;
13047	}
13048	case ARM::MVE_VBICimmi32:
13049	case ARM::MVE_VORRimmi32: {
13050	// op: imm
13051	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
13052	Value \|= (op & UINT64_C(`128`)) << `21`;
13053	Value \|= (op & UINT64_C(`112`)) << `12`;
13054	Value \|= (op & UINT64_C(`1536`));
13055	Value \|= (op & UINT64_C(`15`));
13056	// op: Qd
13057	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13058	Value \|= (op & UINT64_C(`8`)) << `19`;
13059	Value \|= (op & UINT64_C(`7`)) << `13`;
13060	break;
13061	}
13062	case ARM::MVE_VBICimmi16:
13063	case ARM::MVE_VORRimmi16: {
13064	// op: imm
13065	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
13066	Value \|= (op & UINT64_C(`128`)) << `21`;
13067	Value \|= (op & UINT64_C(`112`)) << `12`;
13068	Value \|= (op & UINT64_C(`512`));
13069	Value \|= (op & UINT64_C(`15`));
13070	// op: Qd
13071	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13072	Value \|= (op & UINT64_C(`8`)) << `19`;
13073	Value \|= (op & UINT64_C(`7`)) << `13`;
13074	break;
13075	}
13076	case ARM::t2ADDspImm12:
13077	case ARM::t2SUBspImm12: {
13078	// op: imm
13079	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
13080	Value \|= (op & UINT64_C(`2048`)) << `15`;
13081	Value \|= (op & UINT64_C(`1792`)) << `4`;
13082	Value \|= (op & UINT64_C(`255`));
13083	break;
13084	}
13085	case ARM::tADDspi:
13086	case ARM::tSUBspi: {
13087	// op: imm
13088	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
13089	op &= UINT64_C(`127`);
13090	Value \|= op;
13091	break;
13092	}
13093	case ARM::MVE_VSHLC: {
13094	// op: imm
13095	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
13096	op &= UINT64_C(`31`);
13097	op <<= `16`;
13098	Value \|= op;
13099	// op: Qd
13100	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13101	Value \|= (op & UINT64_C(`8`)) << `19`;
13102	Value \|= (op & UINT64_C(`7`)) << `13`;
13103	// op: RdmDest
13104	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13105	op &= UINT64_C(`15`);
13106	Value \|= op;
13107	break;
13108	}
13109	case ARM::t2HVC:
13110	case ARM::t2UDF: {
13111	// op: imm16
13112	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13113	Value \|= (op & UINT64_C(`61440`)) << `4`;
13114	Value \|= (op & UINT64_C(`4095`));
13115	break;
13116	}
13117	case ARM::UDF: {
13118	// op: imm16
13119	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13120	Value \|= (op & UINT64_C(`65520`)) << `4`;
13121	Value \|= (op & UINT64_C(`15`));
13122	break;
13123	}
13124	case ARM::tUDF: {
13125	// op: imm8
13126	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13127	op &= UINT64_C(`255`);
13128	Value \|= op;
13129	break;
13130	}
13131	case ARM::tCPS: {
13132	// op: imod
13133	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13134	op &= UINT64_C(`1`);
13135	op <<= `4`;
13136	Value \|= op;
13137	// op: iflags
13138	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13139	op &= UINT64_C(`7`);
13140	Value \|= op;
13141	break;
13142	}
13143	case ARM::CPS2p: {
13144	// op: imod
13145	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13146	op &= UINT64_C(`3`);
13147	op <<= `18`;
13148	Value \|= op;
13149	// op: iflags
13150	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13151	op &= UINT64_C(`7`);
13152	op <<= `6`;
13153	Value \|= op;
13154	break;
13155	}
13156	case ARM::CPS3p: {
13157	// op: imod
13158	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13159	op &= UINT64_C(`3`);
13160	op <<= `18`;
13161	Value \|= op;
13162	// op: iflags
13163	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13164	op &= UINT64_C(`7`);
13165	op <<= `6`;
13166	Value \|= op;
13167	// op: mode
13168	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
13169	op &= UINT64_C(`31`);
13170	Value \|= op;
13171	break;
13172	}
13173	case ARM::t2CPS2p: {
13174	// op: imod
13175	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13176	op &= UINT64_C(`3`);
13177	op <<= `9`;
13178	Value \|= op;
13179	// op: iflags
13180	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13181	op &= UINT64_C(`7`);
13182	op <<= `5`;
13183	Value \|= op;
13184	break;
13185	}
13186	case ARM::t2CPS3p: {
13187	// op: imod
13188	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13189	op &= UINT64_C(`3`);
13190	op <<= `9`;
13191	Value \|= op;
13192	// op: iflags
13193	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13194	op &= UINT64_C(`7`);
13195	op <<= `5`;
13196	Value \|= op;
13197	// op: mode
13198	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
13199	op &= UINT64_C(`31`);
13200	Value \|= op;
13201	break;
13202	}
13203	case ARM::t2LE: {
13204	// op: label
13205	op = getBFTargetOpValue<true, ARM::fixup_le>(MI, `0`, Fixups, STI);
13206	Value \|= (op & UINT64_C(`1`)) << `11`;
13207	Value \|= (op & UINT64_C(`2046`));
13208	break;
13209	}
13210	case ARM::MVE_LETP:
13211	case ARM::t2LEUpdate: {
13212	// op: label
13213	op = getBFTargetOpValue<true, ARM::fixup_le>(MI, `2`, Fixups, STI);
13214	Value \|= (op & UINT64_C(`1`)) << `11`;
13215	Value \|= (op & UINT64_C(`2046`));
13216	break;
13217	}
13218	case ARM::t2MSR_AR: {
13219	// op: mask
13220	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13221	Value \|= (op & UINT64_C(`16`)) << `16`;
13222	Value \|= (op & UINT64_C(`15`)) << `8`;
13223	// op: Rn
13224	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13225	op &= UINT64_C(`15`);
13226	op <<= `16`;
13227	Value \|= op;
13228	break;
13229	}
13230	case ARM::CPS1p:
13231	case ARM::SRSDA:
13232	case ARM::SRSDA_UPD:
13233	case ARM::SRSDB:
13234	case ARM::SRSDB_UPD:
13235	case ARM::SRSIA:
13236	case ARM::SRSIA_UPD:
13237	case ARM::SRSIB:
13238	case ARM::SRSIB_UPD:
13239	case ARM::t2CPS1p:
13240	case ARM::t2SRSDB:
13241	case ARM::t2SRSDB_UPD:
13242	case ARM::t2SRSIA:
13243	case ARM::t2SRSIA_UPD: {
13244	// op: mode
13245	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13246	op &= UINT64_C(`31`);
13247	Value \|= op;
13248	break;
13249	}
13250	case ARM::LDC2L_POST:
13251	case ARM::LDC2_POST:
13252	case ARM::STC2L_POST:
13253	case ARM::STC2_POST:
13254	case ARM::t2LDC2L_POST:
13255	case ARM::t2LDC2_POST:
13256	case ARM::t2LDCL_POST:
13257	case ARM::t2LDC_POST:
13258	case ARM::t2STC2L_POST:
13259	case ARM::t2STC2_POST:
13260	case ARM::t2STCL_POST:
13261	case ARM::t2STC_POST: {
13262	// op: offset
13263	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
13264	Value \|= (op & UINT64_C(`256`)) << `15`;
13265	Value \|= (op & UINT64_C(`255`));
13266	// op: addr
13267	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
13268	op &= UINT64_C(`15`);
13269	op <<= `16`;
13270	Value \|= op;
13271	// op: cop
13272	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13273	op &= UINT64_C(`15`);
13274	op <<= `8`;
13275	Value \|= op;
13276	// op: CRd
13277	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13278	op &= UINT64_C(`15`);
13279	op <<= `12`;
13280	Value \|= op;
13281	break;
13282	}
13283	case ARM::CDP2:
13284	case ARM::t2CDP:
13285	case ARM::t2CDP2: {
13286	// op: opc1
13287	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13288	op &= UINT64_C(`15`);
13289	op <<= `20`;
13290	Value \|= op;
13291	// op: CRn
13292	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
13293	op &= UINT64_C(`15`);
13294	op <<= `16`;
13295	Value \|= op;
13296	// op: CRd
13297	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
13298	op &= UINT64_C(`15`);
13299	op <<= `12`;
13300	Value \|= op;
13301	// op: cop
13302	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13303	op &= UINT64_C(`15`);
13304	op <<= `8`;
13305	Value \|= op;
13306	// op: opc2
13307	op = getMachineOpValue(MI, MI.getOperand(`5`), Fixups, STI);
13308	op &= UINT64_C(`7`);
13309	op <<= `5`;
13310	Value \|= op;
13311	// op: CRm
13312	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
13313	op &= UINT64_C(`15`);
13314	Value \|= op;
13315	break;
13316	}
13317	case ARM::DMB:
13318	case ARM::DSB:
13319	case ARM::ISB:
13320	case ARM::t2DBG:
13321	case ARM::t2DMB:
13322	case ARM::t2DSB:
13323	case ARM::t2ISB: {
13324	// op: opt
13325	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13326	op &= UINT64_C(`15`);
13327	Value \|= op;
13328	break;
13329	}
13330	case ARM::t2SMC: {
13331	// op: opt
13332	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13333	op &= UINT64_C(`15`);
13334	op <<= `16`;
13335	Value \|= op;
13336	break;
13337	}
13338	case ARM::LDC2L_OPTION:
13339	case ARM::LDC2_OPTION:
13340	case ARM::STC2L_OPTION:
13341	case ARM::STC2_OPTION:
13342	case ARM::t2LDC2L_OPTION:
13343	case ARM::t2LDC2_OPTION:
13344	case ARM::t2LDCL_OPTION:
13345	case ARM::t2LDC_OPTION:
13346	case ARM::t2STC2L_OPTION:
13347	case ARM::t2STC2_OPTION:
13348	case ARM::t2STCL_OPTION:
13349	case ARM::t2STC_OPTION: {
13350	// op: option
13351	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
13352	op &= UINT64_C(`255`);
13353	Value \|= op;
13354	// op: addr
13355	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
13356	op &= UINT64_C(`15`);
13357	op <<= `16`;
13358	Value \|= op;
13359	// op: cop
13360	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13361	op &= UINT64_C(`15`);
13362	op <<= `8`;
13363	Value \|= op;
13364	// op: CRd
13365	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13366	op &= UINT64_C(`15`);
13367	op <<= `12`;
13368	Value \|= op;
13369	break;
13370	}
13371	case ARM::BX_RET:
13372	case ARM::ERET:
13373	case ARM::MOVPCLR: {
13374	// op: p
13375	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13376	op &= UINT64_C(`15`);
13377	op <<= `28`;
13378	Value \|= op;
13379	break;
13380	}
13381	case ARM::FMSTAT: {
13382	// op: p
13383	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13384	op &= UINT64_C(`15`);
13385	op <<= `28`;
13386	Value \|= op;
13387	Value = VFPThumb2PostEncoder(MI, Value, STI);
13388	break;
13389	}
13390	case ARM::t2Bcc: {
13391	// op: p
13392	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13393	op &= UINT64_C(`15`);
13394	op <<= `22`;
13395	Value \|= op;
13396	// op: target
13397	op = getBranchTargetOpValue(MI, `0`, Fixups, STI);
13398	Value \|= (op & UINT64_C(`1048576`)) << `6`;
13399	Value \|= (op & UINT64_C(`258048`)) << `4`;
13400	Value \|= (op & UINT64_C(`262144`)) >> `5`;
13401	Value \|= (op & UINT64_C(`524288`)) >> `8`;
13402	Value \|= (op & UINT64_C(`4094`)) >> `1`;
13403	break;
13404	}
13405	case ARM::VCMPEZD:
13406	case ARM::VCMPZD: {
13407	// op: p
13408	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13409	op &= UINT64_C(`15`);
13410	op <<= `28`;
13411	Value \|= op;
13412	// op: Dd
13413	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13414	Value \|= (op & UINT64_C(`16`)) << `18`;
13415	Value \|= (op & UINT64_C(`15`)) << `12`;
13416	Value = VFPThumb2PostEncoder(MI, Value, STI);
13417	break;
13418	}
13419	case ARM::MRS:
13420	case ARM::MRSsys: {
13421	// op: p
13422	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13423	op &= UINT64_C(`15`);
13424	op <<= `28`;
13425	Value \|= op;
13426	// op: Rd
13427	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13428	op &= UINT64_C(`15`);
13429	op <<= `12`;
13430	Value \|= op;
13431	break;
13432	}
13433	case ARM::VLDMSIA:
13434	case ARM::VSTMSIA: {
13435	// op: p
13436	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13437	op &= UINT64_C(`15`);
13438	op <<= `28`;
13439	Value \|= op;
13440	// op: Rn
13441	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13442	op &= UINT64_C(`15`);
13443	op <<= `16`;
13444	Value \|= op;
13445	// op: regs
13446	op = getRegisterListOpValue(MI, `3`, Fixups, STI);
13447	Value \|= (op & UINT64_C(`256`)) << `14`;
13448	Value \|= (op & UINT64_C(`7680`)) << `3`;
13449	Value \|= (op & UINT64_C(`255`));
13450	Value = VFPThumb2PostEncoder(MI, Value, STI);
13451	break;
13452	}
13453	case ARM::FLDMXIA:
13454	case ARM::FSTMXIA: {
13455	// op: p
13456	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13457	op &= UINT64_C(`15`);
13458	op <<= `28`;
13459	Value \|= op;
13460	// op: Rn
13461	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13462	op &= UINT64_C(`15`);
13463	op <<= `16`;
13464	Value \|= op;
13465	// op: regs
13466	op = getRegisterListOpValue(MI, `3`, Fixups, STI);
13467	Value \|= (op & UINT64_C(`3840`)) << `4`;
13468	Value \|= (op & UINT64_C(`254`));
13469	Value = VFPThumb2PostEncoder(MI, Value, STI);
13470	break;
13471	}
13472	case ARM::VLDMDIA:
13473	case ARM::VSTMDIA: {
13474	// op: p
13475	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13476	op &= UINT64_C(`15`);
13477	op <<= `28`;
13478	Value \|= op;
13479	// op: Rn
13480	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13481	op &= UINT64_C(`15`);
13482	op <<= `16`;
13483	Value \|= op;
13484	// op: regs
13485	op = getRegisterListOpValue(MI, `3`, Fixups, STI);
13486	Value \|= (op & UINT64_C(`4096`)) << `10`;
13487	Value \|= (op & UINT64_C(`3840`)) << `4`;
13488	Value \|= (op & UINT64_C(`254`));
13489	Value = VFPThumb2PostEncoder(MI, Value, STI);
13490	break;
13491	}
13492	case ARM::VLLDM:
13493	case ARM::VLSTM: {
13494	// op: p
13495	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13496	op &= UINT64_C(`15`);
13497	op <<= `28`;
13498	Value \|= op;
13499	// op: Rn
13500	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13501	op &= UINT64_C(`15`);
13502	op <<= `16`;
13503	Value \|= op;
13504	Value = VFPThumb2PostEncoder(MI, Value, STI);
13505	break;
13506	}
13507	case ARM::VMRS:
13508	case ARM::VMRS_FPCXTNS:
13509	case ARM::VMRS_FPCXTS:
13510	case ARM::VMRS_FPEXC:
13511	case ARM::VMRS_FPINST:
13512	case ARM::VMRS_FPINST2:
13513	case ARM::VMRS_FPSID:
13514	case ARM::VMRS_MVFR0:
13515	case ARM::VMRS_MVFR1:
13516	case ARM::VMRS_MVFR2:
13517	case ARM::VMRS_VPR:
13518	case ARM::VMSR:
13519	case ARM::VMSR_FPCXTNS:
13520	case ARM::VMSR_FPCXTS:
13521	case ARM::VMSR_FPEXC:
13522	case ARM::VMSR_FPINST:
13523	case ARM::VMSR_FPINST2:
13524	case ARM::VMSR_FPSID:
13525	case ARM::VMSR_VPR: {
13526	// op: p
13527	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13528	op &= UINT64_C(`15`);
13529	op <<= `28`;
13530	Value \|= op;
13531	// op: Rt
13532	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13533	op &= UINT64_C(`15`);
13534	op <<= `12`;
13535	Value \|= op;
13536	Value = VFPThumb2PostEncoder(MI, Value, STI);
13537	break;
13538	}
13539	case ARM::VCMPEZH:
13540	case ARM::VCMPEZS:
13541	case ARM::VCMPZH:
13542	case ARM::VCMPZS: {
13543	// op: p
13544	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13545	op &= UINT64_C(`15`);
13546	op <<= `28`;
13547	Value \|= op;
13548	// op: Sd
13549	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13550	Value \|= (op & UINT64_C(`1`)) << `22`;
13551	Value \|= (op & UINT64_C(`30`)) << `11`;
13552	Value = VFPThumb2PostEncoder(MI, Value, STI);
13553	break;
13554	}
13555	case ARM::BX_pred: {
13556	// op: p
13557	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13558	op &= UINT64_C(`15`);
13559	op <<= `28`;
13560	Value \|= op;
13561	// op: dst
13562	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13563	op &= UINT64_C(`15`);
13564	Value \|= op;
13565	break;
13566	}
13567	case ARM::BL_pred: {
13568	// op: p
13569	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13570	op &= UINT64_C(`15`);
13571	op <<= `28`;
13572	Value \|= op;
13573	// op: func
13574	op = getARMBLTargetOpValue(MI, `0`, Fixups, STI);
13575	op &= UINT64_C(`16777215`);
13576	Value \|= op;
13577	break;
13578	}
13579	case ARM::BLX_pred:
13580	case ARM::BXJ: {
13581	// op: p
13582	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13583	op &= UINT64_C(`15`);
13584	op <<= `28`;
13585	Value \|= op;
13586	// op: func
13587	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13588	op &= UINT64_C(`15`);
13589	Value \|= op;
13590	break;
13591	}
13592	case ARM::HINT: {
13593	// op: p
13594	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13595	op &= UINT64_C(`15`);
13596	op <<= `28`;
13597	Value \|= op;
13598	// op: imm
13599	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13600	op &= UINT64_C(`255`);
13601	Value \|= op;
13602	break;
13603	}
13604	case ARM::DBG:
13605	case ARM::SMC: {
13606	// op: p
13607	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13608	op &= UINT64_C(`15`);
13609	op <<= `28`;
13610	Value \|= op;
13611	// op: opt
13612	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13613	op &= UINT64_C(`15`);
13614	Value \|= op;
13615	break;
13616	}
13617	case ARM::LDMDA:
13618	case ARM::LDMDB:
13619	case ARM::LDMIA:
13620	case ARM::LDMIB:
13621	case ARM::STMDA:
13622	case ARM::STMDB:
13623	case ARM::STMIA:
13624	case ARM::STMIB:
13625	case ARM::sysLDMDA:
13626	case ARM::sysLDMDB:
13627	case ARM::sysLDMIA:
13628	case ARM::sysLDMIB:
13629	case ARM::sysSTMDA:
13630	case ARM::sysSTMDB:
13631	case ARM::sysSTMIA:
13632	case ARM::sysSTMIB: {
13633	// op: p
13634	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13635	op &= UINT64_C(`15`);
13636	op <<= `28`;
13637	Value \|= op;
13638	// op: regs
13639	op = getRegisterListOpValue(MI, `3`, Fixups, STI);
13640	op &= UINT64_C(`65535`);
13641	Value \|= op;
13642	// op: Rn
13643	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13644	op &= UINT64_C(`15`);
13645	op <<= `16`;
13646	Value \|= op;
13647	break;
13648	}
13649	case ARM::SVC: {
13650	// op: p
13651	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13652	op &= UINT64_C(`15`);
13653	op <<= `28`;
13654	Value \|= op;
13655	// op: svc
13656	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13657	op &= UINT64_C(`16777215`);
13658	Value \|= op;
13659	break;
13660	}
13661	case ARM::Bcc: {
13662	// op: p
13663	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13664	op &= UINT64_C(`15`);
13665	op <<= `28`;
13666	Value \|= op;
13667	// op: target
13668	op = getARMBranchTargetOpValue(MI, `0`, Fixups, STI);
13669	op &= UINT64_C(`16777215`);
13670	Value \|= op;
13671	break;
13672	}
13673	case ARM::tBcc: {
13674	// op: p
13675	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13676	op &= UINT64_C(`15`);
13677	op <<= `8`;
13678	Value \|= op;
13679	// op: target
13680	op = getThumbBCCTargetOpValue(MI, `0`, Fixups, STI);
13681	op &= UINT64_C(`255`);
13682	Value \|= op;
13683	break;
13684	}
13685	case ARM::VABSD:
13686	case ARM::VCMPD:
13687	case ARM::VCMPED:
13688	case ARM::VMOVD:
13689	case ARM::VNEGD:
13690	case ARM::VRINTRD:
13691	case ARM::VRINTXD:
13692	case ARM::VRINTZD:
13693	case ARM::VSQRTD: {
13694	// op: p
13695	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
13696	op &= UINT64_C(`15`);
13697	op <<= `28`;
13698	Value \|= op;
13699	// op: Dd
13700	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13701	Value \|= (op & UINT64_C(`16`)) << `18`;
13702	Value \|= (op & UINT64_C(`15`)) << `12`;
13703	// op: Dm
13704	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13705	Value \|= (op & UINT64_C(`16`)) << `1`;
13706	Value \|= (op & UINT64_C(`15`));
13707	Value = VFPThumb2PostEncoder(MI, Value, STI);
13708	break;
13709	}
13710	case ARM::VCVTBHD:
13711	case ARM::VCVTTHD:
13712	case ARM::VSITOD:
13713	case ARM::VUITOD: {
13714	// op: p
13715	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
13716	op &= UINT64_C(`15`);
13717	op <<= `28`;
13718	Value \|= op;
13719	// op: Dd
13720	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13721	Value \|= (op & UINT64_C(`16`)) << `18`;
13722	Value \|= (op & UINT64_C(`15`)) << `12`;
13723	// op: Sm
13724	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13725	Value \|= (op & UINT64_C(`1`)) << `5`;
13726	Value \|= (op & UINT64_C(`30`)) >> `1`;
13727	Value = VFPThumb2PostEncoder(MI, Value, STI);
13728	break;
13729	}
13730	case ARM::FCONSTD: {
13731	// op: p
13732	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
13733	op &= UINT64_C(`15`);
13734	op <<= `28`;
13735	Value \|= op;
13736	// op: Dd
13737	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13738	Value \|= (op & UINT64_C(`16`)) << `18`;
13739	Value \|= (op & UINT64_C(`15`)) << `12`;
13740	// op: imm
13741	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13742	Value \|= (op & UINT64_C(`240`)) << `12`;
13743	Value \|= (op & UINT64_C(`15`));
13744	Value = VFPThumb2PostEncoder(MI, Value, STI);
13745	break;
13746	}
13747	case ARM::VCVTBDH:
13748	case ARM::VCVTTDH: {
13749	// op: p
13750	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
13751	op &= UINT64_C(`15`);
13752	op <<= `28`;
13753	Value \|= op;
13754	// op: Dm
13755	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13756	Value \|= (op & UINT64_C(`16`)) << `1`;
13757	Value \|= (op & UINT64_C(`15`));
13758	// op: Sd
13759	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13760	Value \|= (op & UINT64_C(`1`)) << `22`;
13761	Value \|= (op & UINT64_C(`30`)) << `11`;
13762	Value = VFPThumb2PostEncoder(MI, Value, STI);
13763	break;
13764	}
13765	case ARM::CLZ:
13766	case ARM::RBIT:
13767	case ARM::REV:
13768	case ARM::REV16:
13769	case ARM::REVSH: {
13770	// op: p
13771	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
13772	op &= UINT64_C(`15`);
13773	op <<= `28`;
13774	Value \|= op;
13775	// op: Rd
13776	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13777	op &= UINT64_C(`15`);
13778	op <<= `12`;
13779	Value \|= op;
13780	// op: Rm
13781	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13782	op &= UINT64_C(`15`);
13783	Value \|= op;
13784	break;
13785	}
13786	case ARM::MOVi16: {
13787	// op: p
13788	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
13789	op &= UINT64_C(`15`);
13790	op <<= `28`;
13791	Value \|= op;
13792	// op: Rd
13793	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13794	op &= UINT64_C(`15`);
13795	op <<= `12`;
13796	Value \|= op;
13797	// op: imm
13798	op = getHiLo16ImmOpValue(MI, `1`, Fixups, STI);
13799	Value \|= (op & UINT64_C(`61440`)) << `4`;
13800	Value \|= (op & UINT64_C(`4095`));
13801	break;
13802	}
13803	case ARM::ADR: {
13804	// op: p
13805	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
13806	op &= UINT64_C(`15`);
13807	op <<= `28`;
13808	Value \|= op;
13809	// op: Rd
13810	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13811	op &= UINT64_C(`15`);
13812	op <<= `12`;
13813	Value \|= op;
13814	// op: label
13815	op = getAdrLabelOpValue(MI, `1`, Fixups, STI);
13816	Value \|= (op & UINT64_C(`12288`)) << `10`;
13817	Value \|= (op & UINT64_C(`4095`));
13818	break;
13819	}
13820	case ARM::CMNzrr:
13821	case ARM::CMPrr:
13822	case ARM::TEQrr:
13823	case ARM::TSTrr: {
13824	// op: p
13825	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
13826	op &= UINT64_C(`15`);
13827	op <<= `28`;
13828	Value \|= op;
13829	// op: Rn
13830	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13831	op &= UINT64_C(`15`);
13832	op <<= `16`;
13833	Value \|= op;
13834	// op: Rm
13835	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13836	op &= UINT64_C(`15`);
13837	Value \|= op;
13838	break;
13839	}
13840	case ARM::CMNri:
13841	case ARM::CMPri:
13842	case ARM::TEQri:
13843	case ARM::TSTri: {
13844	// op: p
13845	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
13846	op &= UINT64_C(`15`);
13847	op <<= `28`;
13848	Value \|= op;
13849	// op: Rn
13850	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13851	op &= UINT64_C(`15`);
13852	op <<= `16`;
13853	Value \|= op;
13854	// op: imm
13855	op = getModImmOpValue(MI, `1`, Fixups, STI);
13856	op &= UINT64_C(`4095`);
13857	Value \|= op;
13858	break;
13859	}
13860	case ARM::VLDMSDB_UPD:
13861	case ARM::VLDMSIA_UPD:
13862	case ARM::VSTMSDB_UPD:
13863	case ARM::VSTMSIA_UPD: {
13864	// op: p
13865	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
13866	op &= UINT64_C(`15`);
13867	op <<= `28`;
13868	Value \|= op;
13869	// op: Rn
13870	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13871	op &= UINT64_C(`15`);
13872	op <<= `16`;
13873	Value \|= op;
13874	// op: regs
13875	op = getRegisterListOpValue(MI, `4`, Fixups, STI);
13876	Value \|= (op & UINT64_C(`256`)) << `14`;
13877	Value \|= (op & UINT64_C(`7680`)) << `3`;
13878	Value \|= (op & UINT64_C(`255`));
13879	Value = VFPThumb2PostEncoder(MI, Value, STI);
13880	break;
13881	}
13882	case ARM::FLDMXDB_UPD:
13883	case ARM::FLDMXIA_UPD:
13884	case ARM::FSTMXDB_UPD:
13885	case ARM::FSTMXIA_UPD: {
13886	// op: p
13887	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
13888	op &= UINT64_C(`15`);
13889	op <<= `28`;
13890	Value \|= op;
13891	// op: Rn
13892	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13893	op &= UINT64_C(`15`);
13894	op <<= `16`;
13895	Value \|= op;
13896	// op: regs
13897	op = getRegisterListOpValue(MI, `4`, Fixups, STI);
13898	Value \|= (op & UINT64_C(`3840`)) << `4`;
13899	Value \|= (op & UINT64_C(`254`));
13900	Value = VFPThumb2PostEncoder(MI, Value, STI);
13901	break;
13902	}
13903	case ARM::VLDMDDB_UPD:
13904	case ARM::VLDMDIA_UPD:
13905	case ARM::VSTMDDB_UPD:
13906	case ARM::VSTMDIA_UPD: {
13907	// op: p
13908	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
13909	op &= UINT64_C(`15`);
13910	op <<= `28`;
13911	Value \|= op;
13912	// op: Rn
13913	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13914	op &= UINT64_C(`15`);
13915	op <<= `16`;
13916	Value \|= op;
13917	// op: regs
13918	op = getRegisterListOpValue(MI, `4`, Fixups, STI);
13919	Value \|= (op & UINT64_C(`4096`)) << `10`;
13920	Value \|= (op & UINT64_C(`3840`)) << `4`;
13921	Value \|= (op & UINT64_C(`254`));
13922	Value = VFPThumb2PostEncoder(MI, Value, STI);
13923	break;
13924	}
13925	case ARM::STL:
13926	case ARM::STLB:
13927	case ARM::STLH: {
13928	// op: p
13929	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
13930	op &= UINT64_C(`15`);
13931	op <<= `28`;
13932	Value \|= op;
13933	// op: Rt
13934	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13935	op &= UINT64_C(`15`);
13936	Value \|= op;
13937	// op: addr
13938	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13939	op &= UINT64_C(`15`);
13940	op <<= `16`;
13941	Value \|= op;
13942	break;
13943	}
13944	case ARM::VMOVRH:
13945	case ARM::VMOVRS: {
13946	// op: p
13947	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
13948	op &= UINT64_C(`15`);
13949	op <<= `28`;
13950	Value \|= op;
13951	// op: Rt
13952	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13953	op &= UINT64_C(`15`);
13954	op <<= `12`;
13955	Value \|= op;
13956	// op: Sn
13957	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13958	Value \|= (op & UINT64_C(`30`)) << `15`;
13959	Value \|= (op & UINT64_C(`1`)) << `7`;
13960	Value = VFPThumb2PostEncoder(MI, Value, STI);
13961	break;
13962	}
13963	case ARM::LDA:
13964	case ARM::LDAB:
13965	case ARM::LDAEX:
13966	case ARM::LDAEXB:
13967	case ARM::LDAEXD:
13968	case ARM::LDAEXH:
13969	case ARM::LDAH:
13970	case ARM::LDREX:
13971	case ARM::LDREXB:
13972	case ARM::LDREXD:
13973	case ARM::LDREXH: {
13974	// op: p
13975	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
13976	op &= UINT64_C(`15`);
13977	op <<= `28`;
13978	Value \|= op;
13979	// op: Rt
13980	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
13981	op &= UINT64_C(`15`);
13982	op <<= `12`;
13983	Value \|= op;
13984	// op: addr
13985	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
13986	op &= UINT64_C(`15`);
13987	op <<= `16`;
13988	Value \|= op;
13989	break;
13990	}
13991	case ARM::VMRS_FPSCR_NZCVQC:
13992	case ARM::VMRS_P0: {
13993	// op: p
13994	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
13995	op &= UINT64_C(`15`);
13996	op <<= `28`;
13997	Value \|= op;
13998	// op: Rt
13999	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14000	op &= UINT64_C(`15`);
14001	op <<= `12`;
14002	Value \|= op;
14003	Value = VFPThumb2PostEncoder(MI, Value, STI);
14004	break;
14005	}
14006	case ARM::VMSR_FPSCR_NZCVQC:
14007	case ARM::VMSR_P0: {
14008	// op: p
14009	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
14010	op &= UINT64_C(`15`);
14011	op <<= `28`;
14012	Value \|= op;
14013	// op: Rt
14014	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
14015	op &= UINT64_C(`15`);
14016	op <<= `12`;
14017	Value \|= op;
14018	Value = VFPThumb2PostEncoder(MI, Value, STI);
14019	break;
14020	}
14021	case ARM::VCVTSD:
14022	case ARM::VJCVT:
14023	case ARM::VTOSIRD:
14024	case ARM::VTOSIZD:
14025	case ARM::VTOUIRD:
14026	case ARM::VTOUIZD: {
14027	// op: p
14028	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
14029	op &= UINT64_C(`15`);
14030	op <<= `28`;
14031	Value \|= op;
14032	// op: Sd
14033	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14034	Value \|= (op & UINT64_C(`1`)) << `22`;
14035	Value \|= (op & UINT64_C(`30`)) << `11`;
14036	// op: Dm
14037	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
14038	Value \|= (op & UINT64_C(`16`)) << `1`;
14039	Value \|= (op & UINT64_C(`15`));
14040	Value = VFPThumb2PostEncoder(MI, Value, STI);
14041	break;
14042	}
14043	case ARM::VABSH:
14044	case ARM::VABSS:
14045	case ARM::VCMPEH:
14046	case ARM::VCMPES:
14047	case ARM::VCMPH:
14048	case ARM::VCMPS:
14049	case ARM::VCVTBHS:
14050	case ARM::VCVTBSH:
14051	case ARM::VCVTTHS:
14052	case ARM::VCVTTSH:
14053	case ARM::VMOVS:
14054	case ARM::VNEGH:
14055	case ARM::VNEGS:
14056	case ARM::VRINTRH:
14057	case ARM::VRINTRS:
14058	case ARM::VRINTXH:
14059	case ARM::VRINTXS:
14060	case ARM::VRINTZH:
14061	case ARM::VRINTZS:
14062	case ARM::VSITOH:
14063	case ARM::VSITOS:
14064	case ARM::VSQRTH:
14065	case ARM::VSQRTS:
14066	case ARM::VTOSIRH:
14067	case ARM::VTOSIRS:
14068	case ARM::VTOSIZH:
14069	case ARM::VTOSIZS:
14070	case ARM::VTOUIRH:
14071	case ARM::VTOUIRS:
14072	case ARM::VTOUIZH:
14073	case ARM::VTOUIZS:
14074	case ARM::VUITOH:
14075	case ARM::VUITOS: {
14076	// op: p
14077	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
14078	op &= UINT64_C(`15`);
14079	op <<= `28`;
14080	Value \|= op;
14081	// op: Sd
14082	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14083	Value \|= (op & UINT64_C(`1`)) << `22`;
14084	Value \|= (op & UINT64_C(`30`)) << `11`;
14085	// op: Sm
14086	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
14087	Value \|= (op & UINT64_C(`1`)) << `5`;
14088	Value \|= (op & UINT64_C(`30`)) >> `1`;
14089	Value = VFPThumb2PostEncoder(MI, Value, STI);
14090	break;
14091	}
14092	case ARM::FCONSTH:
14093	case ARM::FCONSTS: {
14094	// op: p
14095	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
14096	op &= UINT64_C(`15`);
14097	op <<= `28`;
14098	Value \|= op;
14099	// op: Sd
14100	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14101	Value \|= (op & UINT64_C(`1`)) << `22`;
14102	Value \|= (op & UINT64_C(`30`)) << `11`;
14103	// op: imm
14104	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
14105	Value \|= (op & UINT64_C(`240`)) << `12`;
14106	Value \|= (op & UINT64_C(`15`));
14107	Value = VFPThumb2PostEncoder(MI, Value, STI);
14108	break;
14109	}
14110	case ARM::VCVTDS: {
14111	// op: p
14112	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
14113	op &= UINT64_C(`15`);
14114	op <<= `28`;
14115	Value \|= op;
14116	// op: Sm
14117	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
14118	Value \|= (op & UINT64_C(`1`)) << `5`;
14119	Value \|= (op & UINT64_C(`30`)) >> `1`;
14120	// op: Dd
14121	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14122	Value \|= (op & UINT64_C(`16`)) << `18`;
14123	Value \|= (op & UINT64_C(`15`)) << `12`;
14124	Value = VFPThumb2PostEncoder(MI, Value, STI);
14125	break;
14126	}
14127	case ARM::VMOVHR:
14128	case ARM::VMOVSR: {
14129	// op: p
14130	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
14131	op &= UINT64_C(`15`);
14132	op <<= `28`;
14133	Value \|= op;
14134	// op: Sn
14135	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14136	Value \|= (op & UINT64_C(`30`)) << `15`;
14137	Value \|= (op & UINT64_C(`1`)) << `7`;
14138	// op: Rt
14139	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
14140	op &= UINT64_C(`15`);
14141	op <<= `12`;
14142	Value \|= op;
14143	Value = VFPThumb2PostEncoder(MI, Value, STI);
14144	break;
14145	}
14146	case ARM::VLDR_FPCXTNS_off:
14147	case ARM::VLDR_FPCXTS_off:
14148	case ARM::VLDR_FPSCR_NZCVQC_off:
14149	case ARM::VLDR_FPSCR_off:
14150	case ARM::VLDR_VPR_off:
14151	case ARM::VSTR_FPCXTNS_off:
14152	case ARM::VSTR_FPCXTS_off:
14153	case ARM::VSTR_FPSCR_NZCVQC_off:
14154	case ARM::VSTR_FPSCR_off:
14155	case ARM::VSTR_VPR_off: {
14156	// op: p
14157	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
14158	op &= UINT64_C(`15`);
14159	op <<= `28`;
14160	Value \|= op;
14161	// op: addr
14162	op = getT2AddrModeImm7s4OpValue(MI, `0`, Fixups, STI);
14163	Value \|= (op & UINT64_C(`128`)) << `16`;
14164	Value \|= (op & UINT64_C(`3840`)) << `8`;
14165	Value \|= (op & UINT64_C(`127`));
14166	Value = VFPThumb2PostEncoder(MI, Value, STI);
14167	break;
14168	}
14169	case ARM::MSRbanked: {
14170	// op: p
14171	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
14172	op &= UINT64_C(`15`);
14173	op <<= `28`;
14174	Value \|= op;
14175	// op: banked
14176	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14177	Value \|= (op & UINT64_C(`32`)) << `17`;
14178	Value \|= (op & UINT64_C(`15`)) << `16`;
14179	Value \|= (op & UINT64_C(`16`)) << `4`;
14180	// op: Rn
14181	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
14182	op &= UINT64_C(`15`);
14183	Value \|= op;
14184	break;
14185	}
14186	case ARM::MRSbanked: {
14187	// op: p
14188	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
14189	op &= UINT64_C(`15`);
14190	op <<= `28`;
14191	Value \|= op;
14192	// op: banked
14193	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
14194	Value \|= (op & UINT64_C(`32`)) << `17`;
14195	Value \|= (op & UINT64_C(`15`)) << `16`;
14196	Value \|= (op & UINT64_C(`16`)) << `4`;
14197	// op: Rd
14198	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14199	op &= UINT64_C(`15`);
14200	op <<= `12`;
14201	Value \|= op;
14202	break;
14203	}
14204	case ARM::MSR: {
14205	// op: p
14206	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
14207	op &= UINT64_C(`15`);
14208	op <<= `28`;
14209	Value \|= op;
14210	// op: mask
14211	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14212	Value \|= (op & UINT64_C(`16`)) << `18`;
14213	Value \|= (op & UINT64_C(`15`)) << `16`;
14214	// op: Rn
14215	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
14216	op &= UINT64_C(`15`);
14217	Value \|= op;
14218	break;
14219	}
14220	case ARM::MSRi: {
14221	// op: p
14222	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
14223	op &= UINT64_C(`15`);
14224	op <<= `28`;
14225	Value \|= op;
14226	// op: mask
14227	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14228	Value \|= (op & UINT64_C(`16`)) << `18`;
14229	Value \|= (op & UINT64_C(`15`)) << `16`;
14230	// op: imm
14231	op = getModImmOpValue(MI, `1`, Fixups, STI);
14232	op &= UINT64_C(`4095`);
14233	Value \|= op;
14234	break;
14235	}
14236	case ARM::LDMDA_UPD:
14237	case ARM::LDMDB_UPD:
14238	case ARM::LDMIA_UPD:
14239	case ARM::LDMIB_UPD:
14240	case ARM::STMDA_UPD:
14241	case ARM::STMDB_UPD:
14242	case ARM::STMIA_UPD:
14243	case ARM::STMIB_UPD:
14244	case ARM::sysLDMDA_UPD:
14245	case ARM::sysLDMDB_UPD:
14246	case ARM::sysLDMIA_UPD:
14247	case ARM::sysLDMIB_UPD:
14248	case ARM::sysSTMDA_UPD:
14249	case ARM::sysSTMDB_UPD:
14250	case ARM::sysSTMIA_UPD:
14251	case ARM::sysSTMIB_UPD: {
14252	// op: p
14253	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
14254	op &= UINT64_C(`15`);
14255	op <<= `28`;
14256	Value \|= op;
14257	// op: regs
14258	op = getRegisterListOpValue(MI, `4`, Fixups, STI);
14259	op &= UINT64_C(`65535`);
14260	Value \|= op;
14261	// op: Rn
14262	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
14263	op &= UINT64_C(`15`);
14264	op <<= `16`;
14265	Value \|= op;
14266	break;
14267	}
14268	case ARM::MOVr:
14269	case ARM::MOVr_TC:
14270	case ARM::MVNr: {
14271	// op: p
14272	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
14273	op &= UINT64_C(`15`);
14274	op <<= `28`;
14275	Value \|= op;
14276	// op: s
14277	op = getCCOutOpValue(MI, `4`, Fixups, STI);
14278	op &= UINT64_C(`1`);
14279	op <<= `20`;
14280	Value \|= op;
14281	// op: Rd
14282	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14283	op &= UINT64_C(`15`);
14284	op <<= `12`;
14285	Value \|= op;
14286	// op: Rm
14287	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
14288	op &= UINT64_C(`15`);
14289	Value \|= op;
14290	break;
14291	}
14292	case ARM::MOVi:
14293	case ARM::MVNi: {
14294	// op: p
14295	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
14296	op &= UINT64_C(`15`);
14297	op <<= `28`;
14298	Value \|= op;
14299	// op: s
14300	op = getCCOutOpValue(MI, `4`, Fixups, STI);
14301	op &= UINT64_C(`1`);
14302	op <<= `20`;
14303	Value \|= op;
14304	// op: Rd
14305	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14306	op &= UINT64_C(`15`);
14307	op <<= `12`;
14308	Value \|= op;
14309	// op: imm
14310	op = getModImmOpValue(MI, `1`, Fixups, STI);
14311	op &= UINT64_C(`4095`);
14312	Value \|= op;
14313	break;
14314	}
14315	case ARM::VADDD:
14316	case ARM::VDIVD:
14317	case ARM::VMULD:
14318	case ARM::VNMULD:
14319	case ARM::VSUBD: {
14320	// op: p
14321	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
14322	op &= UINT64_C(`15`);
14323	op <<= `28`;
14324	Value \|= op;
14325	// op: Dd
14326	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14327	Value \|= (op & UINT64_C(`16`)) << `18`;
14328	Value \|= (op & UINT64_C(`15`)) << `12`;
14329	// op: Dn
14330	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
14331	Value \|= (op & UINT64_C(`15`)) << `16`;
14332	Value \|= (op & UINT64_C(`16`)) << `3`;
14333	// op: Dm
14334	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
14335	Value \|= (op & UINT64_C(`16`)) << `1`;
14336	Value \|= (op & UINT64_C(`15`));
14337	Value = VFPThumb2PostEncoder(MI, Value, STI);
14338	break;
14339	}
14340	case ARM::VLDRD:
14341	case ARM::VSTRD: {
14342	// op: p
14343	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
14344	op &= UINT64_C(`15`);
14345	op <<= `28`;
14346	Value \|= op;
14347	// op: Dd
14348	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14349	Value \|= (op & UINT64_C(`16`)) << `18`;
14350	Value \|= (op & UINT64_C(`15`)) << `12`;
14351	// op: addr
14352	op = getAddrMode5OpValue(MI, `1`, Fixups, STI);
14353	Value \|= (op & UINT64_C(`256`)) << `15`;
14354	Value \|= (op & UINT64_C(`7680`)) << `7`;
14355	Value \|= (op & UINT64_C(`255`));
14356	Value = VFPThumb2PostEncoder(MI, Value, STI);
14357	break;
14358	}
14359	case ARM::VMOVDRR: {
14360	// op: p
14361	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
14362	op &= UINT64_C(`15`);
14363	op <<= `28`;
14364	Value \|= op;
14365	// op: Dm
14366	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14367	Value \|= (op & UINT64_C(`16`)) << `1`;
14368	Value \|= (op & UINT64_C(`15`));
14369	// op: Rt
14370	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
14371	op &= UINT64_C(`15`);
14372	op <<= `12`;
14373	Value \|= op;
14374	// op: Rt2
14375	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
14376	op &= UINT64_C(`15`);
14377	op <<= `16`;
14378	Value \|= op;
14379	Value = VFPThumb2PostEncoder(MI, Value, STI);
14380	break;
14381	}
14382	case ARM::VMOVRRD: {
14383	// op: p
14384	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
14385	op &= UINT64_C(`15`);
14386	op <<= `28`;
14387	Value \|= op;
14388	// op: Dm
14389	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
14390	Value \|= (op & UINT64_C(`16`)) << `1`;
14391	Value \|= (op & UINT64_C(`15`));
14392	// op: Rt
14393	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14394	op &= UINT64_C(`15`);
14395	op <<= `12`;
14396	Value \|= op;
14397	// op: Rt2
14398	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
14399	op &= UINT64_C(`15`);
14400	op <<= `16`;
14401	Value \|= op;
14402	Value = VFPThumb2PostEncoder(MI, Value, STI);
14403	break;
14404	}
14405	case ARM::SXTB:
14406	case ARM::SXTB16:
14407	case ARM::SXTH:
14408	case ARM::UXTB:
14409	case ARM::UXTB16:
14410	case ARM::UXTH: {
14411	// op: p
14412	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
14413	op &= UINT64_C(`15`);
14414	op <<= `28`;
14415	Value \|= op;
14416	// op: Rd
14417	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14418	op &= UINT64_C(`15`);
14419	op <<= `12`;
14420	Value \|= op;
14421	// op: Rm
14422	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
14423	op &= UINT64_C(`15`);
14424	Value \|= op;
14425	// op: rot
14426	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
14427	op &= UINT64_C(`3`);
14428	op <<= `10`;
14429	Value \|= op;
14430	break;
14431	}
14432	case ARM::SEL: {
14433	// op: p
14434	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
14435	op &= UINT64_C(`15`);
14436	op <<= `28`;
14437	Value \|= op;
14438	// op: Rd
14439	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14440	op &= UINT64_C(`15`);
14441	op <<= `12`;
14442	Value \|= op;
14443	// op: Rn
14444	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
14445	op &= UINT64_C(`15`);
14446	op <<= `16`;
14447	Value \|= op;
14448	// op: Rm
14449	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
14450	op &= UINT64_C(`15`);
14451	Value \|= op;
14452	break;
14453	}
14454	case ARM::BFC: {
14455	// op: p
14456	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
14457	op &= UINT64_C(`15`);
14458	op <<= `28`;
14459	Value \|= op;
14460	// op: Rd
14461	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14462	op &= UINT64_C(`15`);
14463	op <<= `12`;
14464	Value \|= op;
14465	// op: imm
14466	op = getBitfieldInvertedMaskOpValue(MI, `2`, Fixups, STI);
14467	Value \|= (op & UINT64_C(`992`)) << `11`;
14468	Value \|= (op & UINT64_C(`31`)) << `7`;
14469	break;
14470	}
14471	case ARM::MOVTi16: {
14472	// op: p
14473	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
14474	op &= UINT64_C(`15`);
14475	op <<= `28`;
14476	Value \|= op;
14477	// op: Rd
14478	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14479	op &= UINT64_C(`15`);
14480	op <<= `12`;
14481	Value \|= op;
14482	// op: imm
14483	op = getHiLo16ImmOpValue(MI, `2`, Fixups, STI);
14484	Value \|= (op & UINT64_C(`61440`)) << `4`;
14485	Value \|= (op & UINT64_C(`4095`));
14486	break;
14487	}
14488	case ARM::SSAT16:
14489	case ARM::USAT16: {
14490	// op: p
14491	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
14492	op &= UINT64_C(`15`);
14493	op <<= `28`;
14494	Value \|= op;
14495	// op: Rd
14496	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14497	op &= UINT64_C(`15`);
14498	op <<= `12`;
14499	Value \|= op;
14500	// op: sat_imm
14501	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
14502	op &= UINT64_C(`15`);
14503	op <<= `16`;
14504	Value \|= op;
14505	// op: Rn
14506	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
14507	op &= UINT64_C(`15`);
14508	Value \|= op;
14509	break;
14510	}
14511	case ARM::SDIV:
14512	case ARM::SMMUL:
14513	case ARM::SMMULR:
14514	case ARM::UDIV:
14515	case ARM::USAD8: {
14516	// op: p
14517	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
14518	op &= UINT64_C(`15`);
14519	op <<= `28`;
14520	Value \|= op;
14521	// op: Rd
14522	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14523	op &= UINT64_C(`15`);
14524	op <<= `16`;
14525	Value \|= op;
14526	// op: Rn
14527	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
14528	op &= UINT64_C(`15`);
14529	Value \|= op;
14530	// op: Rm
14531	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
14532	op &= UINT64_C(`15`);
14533	op <<= `8`;
14534	Value \|= op;
14535	break;
14536	}
14537	case ARM::CMNzrsi:
14538	case ARM::CMPrsi:
14539	case ARM::TEQrsi:
14540	case ARM::TSTrsi: {
14541	// op: p
14542	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
14543	op &= UINT64_C(`15`);
14544	op <<= `28`;
14545	Value \|= op;
14546	// op: Rn
14547	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14548	op &= UINT64_C(`15`);
14549	op <<= `16`;
14550	Value \|= op;
14551	// op: shift
14552	op = getSORegImmOpValue(MI, `1`, Fixups, STI);
14553	Value \|= (op & UINT64_C(`4064`));
14554	Value \|= (op & UINT64_C(`15`));
14555	break;
14556	}
14557	case ARM::SMUAD:
14558	case ARM::SMUADX:
14559	case ARM::SMULBB:
14560	case ARM::SMULBT:
14561	case ARM::SMULTB:
14562	case ARM::SMULTT:
14563	case ARM::SMULWB:
14564	case ARM::SMULWT:
14565	case ARM::SMUSD:
14566	case ARM::SMUSDX: {
14567	// op: p
14568	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
14569	op &= UINT64_C(`15`);
14570	op <<= `28`;
14571	Value \|= op;
14572	// op: Rn
14573	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
14574	op &= UINT64_C(`15`);
14575	Value \|= op;
14576	// op: Rm
14577	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
14578	op &= UINT64_C(`15`);
14579	op <<= `8`;
14580	Value \|= op;
14581	// op: Rd
14582	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14583	op &= UINT64_C(`15`);
14584	op <<= `16`;
14585	Value \|= op;
14586	break;
14587	}
14588	case ARM::QADD16:
14589	case ARM::QADD8:
14590	case ARM::QASX:
14591	case ARM::QSAX:
14592	case ARM::QSUB16:
14593	case ARM::QSUB8:
14594	case ARM::SADD16:
14595	case ARM::SADD8:
14596	case ARM::SASX:
14597	case ARM::SHADD16:
14598	case ARM::SHADD8:
14599	case ARM::SHASX:
14600	case ARM::SHSAX:
14601	case ARM::SHSUB16:
14602	case ARM::SHSUB8:
14603	case ARM::SSAX:
14604	case ARM::SSUB16:
14605	case ARM::SSUB8:
14606	case ARM::UADD16:
14607	case ARM::UADD8:
14608	case ARM::UASX:
14609	case ARM::UHADD16:
14610	case ARM::UHADD8:
14611	case ARM::UHASX:
14612	case ARM::UHSAX:
14613	case ARM::UHSUB16:
14614	case ARM::UHSUB8:
14615	case ARM::UQADD16:
14616	case ARM::UQADD8:
14617	case ARM::UQASX:
14618	case ARM::UQSAX:
14619	case ARM::UQSUB16:
14620	case ARM::UQSUB8:
14621	case ARM::USAX:
14622	case ARM::USUB16:
14623	case ARM::USUB8: {
14624	// op: p
14625	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
14626	op &= UINT64_C(`15`);
14627	op <<= `28`;
14628	Value \|= op;
14629	// op: Rn
14630	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
14631	op &= UINT64_C(`15`);
14632	op <<= `16`;
14633	Value \|= op;
14634	// op: Rd
14635	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14636	op &= UINT64_C(`15`);
14637	op <<= `12`;
14638	Value \|= op;
14639	// op: Rm
14640	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
14641	op &= UINT64_C(`15`);
14642	Value \|= op;
14643	break;
14644	}
14645	case ARM::QADD:
14646	case ARM::QDADD:
14647	case ARM::QDSUB:
14648	case ARM::QSUB: {
14649	// op: p
14650	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
14651	op &= UINT64_C(`15`);
14652	op <<= `28`;
14653	Value \|= op;
14654	// op: Rn
14655	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
14656	op &= UINT64_C(`15`);
14657	op <<= `16`;
14658	Value \|= op;
14659	// op: Rd
14660	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14661	op &= UINT64_C(`15`);
14662	op <<= `12`;
14663	Value \|= op;
14664	// op: Rm
14665	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
14666	op &= UINT64_C(`15`);
14667	Value \|= op;
14668	break;
14669	}
14670	case ARM::SWP:
14671	case ARM::SWPB: {
14672	// op: p
14673	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
14674	op &= UINT64_C(`15`);
14675	op <<= `28`;
14676	Value \|= op;
14677	// op: Rt
14678	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14679	op &= UINT64_C(`15`);
14680	op <<= `12`;
14681	Value \|= op;
14682	// op: Rt2
14683	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
14684	op &= UINT64_C(`15`);
14685	Value \|= op;
14686	// op: addr
14687	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
14688	op &= UINT64_C(`15`);
14689	op <<= `16`;
14690	Value \|= op;
14691	break;
14692	}
14693	case ARM::LDRBi12:
14694	case ARM::LDRi12:
14695	case ARM::STRBi12:
14696	case ARM::STRi12: {
14697	// op: p
14698	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
14699	op &= UINT64_C(`15`);
14700	op <<= `28`;
14701	Value \|= op;
14702	// op: Rt
14703	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14704	op &= UINT64_C(`15`);
14705	op <<= `12`;
14706	Value \|= op;
14707	// op: addr
14708	op = getAddrModeImm12OpValue(MI, `1`, Fixups, STI);
14709	Value \|= (op & UINT64_C(`4096`)) << `11`;
14710	Value \|= (op & UINT64_C(`122880`)) << `3`;
14711	Value \|= (op & UINT64_C(`4095`));
14712	break;
14713	}
14714	case ARM::LDRcp: {
14715	// op: p
14716	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
14717	op &= UINT64_C(`15`);
14718	op <<= `28`;
14719	Value \|= op;
14720	// op: Rt
14721	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14722	op &= UINT64_C(`15`);
14723	op <<= `12`;
14724	Value \|= op;
14725	// op: addr
14726	op = getAddrModeImm12OpValue(MI, `1`, Fixups, STI);
14727	Value \|= (op & UINT64_C(`4096`)) << `11`;
14728	Value \|= (op & UINT64_C(`4095`));
14729	break;
14730	}
14731	case ARM::STLEX:
14732	case ARM::STLEXB:
14733	case ARM::STLEXD:
14734	case ARM::STLEXH:
14735	case ARM::STREX:
14736	case ARM::STREXB:
14737	case ARM::STREXD:
14738	case ARM::STREXH: {
14739	// op: p
14740	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
14741	op &= UINT64_C(`15`);
14742	op <<= `28`;
14743	Value \|= op;
14744	// op: Rt
14745	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
14746	op &= UINT64_C(`15`);
14747	Value \|= op;
14748	// op: addr
14749	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
14750	op &= UINT64_C(`15`);
14751	op <<= `16`;
14752	Value \|= op;
14753	// op: Rd
14754	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14755	op &= UINT64_C(`15`);
14756	op <<= `12`;
14757	Value \|= op;
14758	break;
14759	}
14760	case ARM::BF16_VCVTB:
14761	case ARM::BF16_VCVTT: {
14762	// op: p
14763	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
14764	op &= UINT64_C(`15`);
14765	op <<= `28`;
14766	Value \|= op;
14767	// op: Sd
14768	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14769	Value \|= (op & UINT64_C(`1`)) << `22`;
14770	Value \|= (op & UINT64_C(`30`)) << `11`;
14771	// op: Sm
14772	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
14773	Value \|= (op & UINT64_C(`1`)) << `5`;
14774	Value \|= (op & UINT64_C(`30`)) >> `1`;
14775	Value = VFPThumb2PostEncoder(MI, Value, STI);
14776	break;
14777	}
14778	case ARM::VADDH:
14779	case ARM::VADDS:
14780	case ARM::VDIVH:
14781	case ARM::VDIVS:
14782	case ARM::VMULH:
14783	case ARM::VMULS:
14784	case ARM::VNMULH:
14785	case ARM::VNMULS:
14786	case ARM::VSUBH:
14787	case ARM::VSUBS: {
14788	// op: p
14789	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
14790	op &= UINT64_C(`15`);
14791	op <<= `28`;
14792	Value \|= op;
14793	// op: Sd
14794	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14795	Value \|= (op & UINT64_C(`1`)) << `22`;
14796	Value \|= (op & UINT64_C(`30`)) << `11`;
14797	// op: Sn
14798	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
14799	Value \|= (op & UINT64_C(`30`)) << `15`;
14800	Value \|= (op & UINT64_C(`1`)) << `7`;
14801	// op: Sm
14802	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
14803	Value \|= (op & UINT64_C(`1`)) << `5`;
14804	Value \|= (op & UINT64_C(`30`)) >> `1`;
14805	Value = VFPThumb2PostEncoder(MI, Value, STI);
14806	break;
14807	}
14808	case ARM::VLDRH:
14809	case ARM::VSTRH: {
14810	// op: p
14811	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
14812	op &= UINT64_C(`15`);
14813	op <<= `28`;
14814	Value \|= op;
14815	// op: Sd
14816	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14817	Value \|= (op & UINT64_C(`1`)) << `22`;
14818	Value \|= (op & UINT64_C(`30`)) << `11`;
14819	// op: addr
14820	op = getAddrMode5FP16OpValue(MI, `1`, Fixups, STI);
14821	Value \|= (op & UINT64_C(`256`)) << `15`;
14822	Value \|= (op & UINT64_C(`7680`)) << `7`;
14823	Value \|= (op & UINT64_C(`255`));
14824	Value = VFPThumb2PostEncoder(MI, Value, STI);
14825	break;
14826	}
14827	case ARM::VLDRS:
14828	case ARM::VSTRS: {
14829	// op: p
14830	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
14831	op &= UINT64_C(`15`);
14832	op <<= `28`;
14833	Value \|= op;
14834	// op: Sd
14835	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14836	Value \|= (op & UINT64_C(`1`)) << `22`;
14837	Value \|= (op & UINT64_C(`30`)) << `11`;
14838	// op: addr
14839	op = getAddrMode5OpValue(MI, `1`, Fixups, STI);
14840	Value \|= (op & UINT64_C(`256`)) << `15`;
14841	Value \|= (op & UINT64_C(`7680`)) << `7`;
14842	Value \|= (op & UINT64_C(`255`));
14843	Value = VFPThumb2PostEncoder(MI, Value, STI);
14844	break;
14845	}
14846	case ARM::VLDR_FPCXTNS_pre:
14847	case ARM::VLDR_FPCXTS_pre:
14848	case ARM::VLDR_FPSCR_NZCVQC_pre:
14849	case ARM::VLDR_FPSCR_pre:
14850	case ARM::VLDR_P0_off:
14851	case ARM::VLDR_VPR_pre:
14852	case ARM::VSTR_FPCXTNS_pre:
14853	case ARM::VSTR_FPCXTS_pre:
14854	case ARM::VSTR_FPSCR_NZCVQC_pre:
14855	case ARM::VSTR_FPSCR_pre:
14856	case ARM::VSTR_P0_off:
14857	case ARM::VSTR_VPR_pre: {
14858	// op: p
14859	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
14860	op &= UINT64_C(`15`);
14861	op <<= `28`;
14862	Value \|= op;
14863	// op: addr
14864	op = getT2AddrModeImm7s4OpValue(MI, `1`, Fixups, STI);
14865	Value \|= (op & UINT64_C(`128`)) << `16`;
14866	Value \|= (op & UINT64_C(`3840`)) << `8`;
14867	Value \|= (op & UINT64_C(`127`));
14868	Value = VFPThumb2PostEncoder(MI, Value, STI);
14869	break;
14870	}
14871	case ARM::VLDR_FPCXTNS_post:
14872	case ARM::VLDR_FPCXTS_post:
14873	case ARM::VLDR_FPSCR_NZCVQC_post:
14874	case ARM::VLDR_FPSCR_post:
14875	case ARM::VLDR_VPR_post:
14876	case ARM::VSTR_FPCXTNS_post:
14877	case ARM::VSTR_FPCXTS_post:
14878	case ARM::VSTR_FPSCR_NZCVQC_post:
14879	case ARM::VSTR_FPSCR_post:
14880	case ARM::VSTR_VPR_post: {
14881	// op: p
14882	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
14883	op &= UINT64_C(`15`);
14884	op <<= `28`;
14885	Value \|= op;
14886	// op: addr
14887	op = getT2ScaledImmOpValue<`7`,`2`>(MI, `2`, Fixups, STI);
14888	Value \|= (op & UINT64_C(`128`)) << `16`;
14889	Value \|= (op & UINT64_C(`127`));
14890	// op: Rn
14891	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
14892	op &= UINT64_C(`15`);
14893	op <<= `16`;
14894	Value \|= op;
14895	Value = VFPThumb2PostEncoder(MI, Value, STI);
14896	break;
14897	}
14898	case ARM::VSHTOH:
14899	case ARM::VSHTOS:
14900	case ARM::VSLTOH:
14901	case ARM::VSLTOS:
14902	case ARM::VTOSHH:
14903	case ARM::VTOSHS:
14904	case ARM::VTOSLH:
14905	case ARM::VTOSLS:
14906	case ARM::VTOUHH:
14907	case ARM::VTOUHS:
14908	case ARM::VTOULH:
14909	case ARM::VTOULS:
14910	case ARM::VUHTOH:
14911	case ARM::VUHTOS:
14912	case ARM::VULTOH:
14913	case ARM::VULTOS: {
14914	// op: p
14915	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
14916	op &= UINT64_C(`15`);
14917	op <<= `28`;
14918	Value \|= op;
14919	// op: fbits
14920	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
14921	Value \|= (op & UINT64_C(`1`)) << `5`;
14922	Value \|= (op & UINT64_C(`30`)) >> `1`;
14923	// op: dst
14924	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14925	Value \|= (op & UINT64_C(`1`)) << `22`;
14926	Value \|= (op & UINT64_C(`30`)) << `11`;
14927	Value = VFPThumb2PostEncoder(MI, Value, STI);
14928	break;
14929	}
14930	case ARM::VSHTOD:
14931	case ARM::VSLTOD:
14932	case ARM::VTOSHD:
14933	case ARM::VTOSLD:
14934	case ARM::VTOUHD:
14935	case ARM::VTOULD:
14936	case ARM::VUHTOD:
14937	case ARM::VULTOD: {
14938	// op: p
14939	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
14940	op &= UINT64_C(`15`);
14941	op <<= `28`;
14942	Value \|= op;
14943	// op: fbits
14944	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
14945	Value \|= (op & UINT64_C(`1`)) << `5`;
14946	Value \|= (op & UINT64_C(`30`)) >> `1`;
14947	// op: dst
14948	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14949	Value \|= (op & UINT64_C(`16`)) << `18`;
14950	Value \|= (op & UINT64_C(`15`)) << `12`;
14951	Value = VFPThumb2PostEncoder(MI, Value, STI);
14952	break;
14953	}
14954	case ARM::ADCrr:
14955	case ARM::ADDrr:
14956	case ARM::ANDrr:
14957	case ARM::BICrr:
14958	case ARM::EORrr:
14959	case ARM::ORRrr:
14960	case ARM::RSBrr:
14961	case ARM::RSCrr:
14962	case ARM::SBCrr:
14963	case ARM::SUBrr: {
14964	// op: p
14965	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
14966	op &= UINT64_C(`15`);
14967	op <<= `28`;
14968	Value \|= op;
14969	// op: s
14970	op = getCCOutOpValue(MI, `5`, Fixups, STI);
14971	op &= UINT64_C(`1`);
14972	op <<= `20`;
14973	Value \|= op;
14974	// op: Rd
14975	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
14976	op &= UINT64_C(`15`);
14977	op <<= `12`;
14978	Value \|= op;
14979	// op: Rn
14980	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
14981	op &= UINT64_C(`15`);
14982	op <<= `16`;
14983	Value \|= op;
14984	// op: Rm
14985	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
14986	op &= UINT64_C(`15`);
14987	Value \|= op;
14988	break;
14989	}
14990	case ARM::ADCri:
14991	case ARM::ADDri:
14992	case ARM::ANDri:
14993	case ARM::BICri:
14994	case ARM::EORri:
14995	case ARM::ORRri:
14996	case ARM::RSBri:
14997	case ARM::RSCri:
14998	case ARM::SBCri:
14999	case ARM::SUBri: {
15000	// op: p
15001	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
15002	op &= UINT64_C(`15`);
15003	op <<= `28`;
15004	Value \|= op;
15005	// op: s
15006	op = getCCOutOpValue(MI, `5`, Fixups, STI);
15007	op &= UINT64_C(`1`);
15008	op <<= `20`;
15009	Value \|= op;
15010	// op: Rd
15011	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
15012	op &= UINT64_C(`15`);
15013	op <<= `12`;
15014	Value \|= op;
15015	// op: Rn
15016	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
15017	op &= UINT64_C(`15`);
15018	op <<= `16`;
15019	Value \|= op;
15020	// op: imm
15021	op = getModImmOpValue(MI, `2`, Fixups, STI);
15022	op &= UINT64_C(`4095`);
15023	Value \|= op;
15024	break;
15025	}
15026	case ARM::MVNsi: {
15027	// op: p
15028	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
15029	op &= UINT64_C(`15`);
15030	op <<= `28`;
15031	Value \|= op;
15032	// op: s
15033	op = getCCOutOpValue(MI, `5`, Fixups, STI);
15034	op &= UINT64_C(`1`);
15035	op <<= `20`;
15036	Value \|= op;
15037	// op: Rd
15038	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
15039	op &= UINT64_C(`15`);
15040	op <<= `12`;
15041	Value \|= op;
15042	// op: shift
15043	op = getSORegImmOpValue(MI, `1`, Fixups, STI);
15044	Value \|= (op & UINT64_C(`4064`));
15045	Value \|= (op & UINT64_C(`15`));
15046	break;
15047	}
15048	case ARM::MOVsi: {
15049	// op: p
15050	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
15051	op &= UINT64_C(`15`);
15052	op <<= `28`;
15053	Value \|= op;
15054	// op: s
15055	op = getCCOutOpValue(MI, `5`, Fixups, STI);
15056	op &= UINT64_C(`1`);
15057	op <<= `20`;
15058	Value \|= op;
15059	// op: Rd
15060	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
15061	op &= UINT64_C(`15`);
15062	op <<= `12`;
15063	Value \|= op;
15064	// op: src
15065	op = getSORegImmOpValue(MI, `1`, Fixups, STI);
15066	Value \|= (op & UINT64_C(`4064`));
15067	Value \|= (op & UINT64_C(`15`));
15068	break;
15069	}
15070	case ARM::MUL: {
15071	// op: p
15072	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
15073	op &= UINT64_C(`15`);
15074	op <<= `28`;
15075	Value \|= op;
15076	// op: s
15077	op = getCCOutOpValue(MI, `5`, Fixups, STI);
15078	op &= UINT64_C(`1`);
15079	op <<= `20`;
15080	Value \|= op;
15081	// op: Rd
15082	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
15083	op &= UINT64_C(`15`);
15084	op <<= `16`;
15085	Value \|= op;
15086	// op: Rm
15087	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
15088	op &= UINT64_C(`15`);
15089	op <<= `8`;
15090	Value \|= op;
15091	// op: Rn
15092	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
15093	op &= UINT64_C(`15`);
15094	Value \|= op;
15095	break;
15096	}
15097	case ARM::VFMAD:
15098	case ARM::VFMSD:
15099	case ARM::VFNMAD:
15100	case ARM::VFNMSD:
15101	case ARM::VMLAD:
15102	case ARM::VMLSD:
15103	case ARM::VNMLAD:
15104	case ARM::VNMLSD: {
15105	// op: p
15106	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
15107	op &= UINT64_C(`15`);
15108	op <<= `28`;
15109	Value \|= op;
15110	// op: Dd
15111	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
15112	Value \|= (op & UINT64_C(`16`)) << `18`;
15113	Value \|= (op & UINT64_C(`15`)) << `12`;
15114	// op: Dn
15115	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
15116	Value \|= (op & UINT64_C(`15`)) << `16`;
15117	Value \|= (op & UINT64_C(`16`)) << `3`;
15118	// op: Dm
15119	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
15120	Value \|= (op & UINT64_C(`16`)) << `1`;
15121	Value \|= (op & UINT64_C(`15`));
15122	Value = VFPThumb2PostEncoder(MI, Value, STI);
15123	break;
15124	}
15125	case ARM::SXTAB:
15126	case ARM::SXTAB16:
15127	case ARM::SXTAH:
15128	case ARM::UXTAB:
15129	case ARM::UXTAB16:
15130	case ARM::UXTAH: {
15131	// op: p
15132	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
15133	op &= UINT64_C(`15`);
15134	op <<= `28`;
15135	Value \|= op;
15136	// op: Rd
15137	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
15138	op &= UINT64_C(`15`);
15139	op <<= `12`;
15140	Value \|= op;
15141	// op: Rm
15142	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
15143	op &= UINT64_C(`15`);
15144	Value \|= op;
15145	// op: Rn
15146	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
15147	op &= UINT64_C(`15`);
15148	op <<= `16`;
15149	Value \|= op;
15150	// op: rot
15151	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
15152	op &= UINT64_C(`3`);
15153	op <<= `10`;
15154	Value \|= op;
15155	break;
15156	}
15157	case ARM::SBFX:
15158	case ARM::UBFX: {
15159	// op: p
15160	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
15161	op &= UINT64_C(`15`);
15162	op <<= `28`;
15163	Value \|= op;
15164	// op: Rd
15165	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
15166	op &= UINT64_C(`15`);
15167	op <<= `12`;
15168	Value \|= op;
15169	// op: Rn
15170	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
15171	op &= UINT64_C(`15`);
15172	Value \|= op;
15173	// op: lsb
15174	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
15175	op &= UINT64_C(`31`);
15176	op <<= `7`;
15177	Value \|= op;
15178	// op: width
15179	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
15180	op &= UINT64_C(`31`);
15181	op <<= `16`;
15182	Value \|= op;
15183	break;
15184	}
15185	case ARM::PKHBT:
15186	case ARM::PKHTB: {
15187	// op: p
15188	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
15189	op &= UINT64_C(`15`);
15190	op <<= `28`;
15191	Value \|= op;
15192	// op: Rd
15193	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
15194	op &= UINT64_C(`15`);
15195	op <<= `12`;
15196	Value \|= op;
15197	// op: Rn
15198	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
15199	op &= UINT64_C(`15`);
15200	op <<= `16`;
15201	Value \|= op;
15202	// op: Rm
15203	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
15204	op &= UINT64_C(`15`);
15205	Value \|= op;
15206	// op: sh
15207	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
15208	op &= UINT64_C(`31`);
15209	op <<= `7`;
15210	Value \|= op;
15211	break;
15212	}
15213	case ARM::BFI: {
15214	// op: p
15215	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
15216	op &= UINT64_C(`15`);
15217	op <<= `28`;
15218	Value \|= op;
15219	// op: Rd
15220	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
15221	op &= UINT64_C(`15`);
15222	op <<= `12`;
15223	Value \|= op;
15224	// op: Rn
15225	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
15226	op &= UINT64_C(`15`);
15227	Value \|= op;
15228	// op: imm
15229	op = getBitfieldInvertedMaskOpValue(MI, `3`, Fixups, STI);
15230	Value \|= (op & UINT64_C(`992`)) << `11`;
15231	Value \|= (op & UINT64_C(`31`)) << `7`;
15232	break;
15233	}
15234	case ARM::SSAT:
15235	case ARM::USAT: {
15236	// op: p
15237	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
15238	op &= UINT64_C(`15`);
15239	op <<= `28`;
15240	Value \|= op;
15241	// op: Rd
15242	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
15243	op &= UINT64_C(`15`);
15244	op <<= `12`;
15245	Value \|= op;
15246	// op: sat_imm
15247	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
15248	op &= UINT64_C(`31`);
15249	op <<= `16`;
15250	Value \|= op;
15251	// op: Rn
15252	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
15253	op &= UINT64_C(`15`);
15254	Value \|= op;
15255	// op: sh
15256	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
15257	Value \|= (op & UINT64_C(`31`)) << `7`;
15258	Value \|= (op & UINT64_C(`32`)) << `1`;
15259	break;
15260	}
15261	case ARM::MLS: {
15262	// op: p
15263	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
15264	op &= UINT64_C(`15`);
15265	op <<= `28`;
15266	Value \|= op;
15267	// op: Rd
15268	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
15269	op &= UINT64_C(`15`);
15270	op <<= `16`;
15271	Value \|= op;
15272	// op: Rm
15273	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
15274	op &= UINT64_C(`15`);
15275	op <<= `8`;
15276	Value \|= op;
15277	// op: Rn
15278	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
15279	op &= UINT64_C(`15`);
15280	Value \|= op;
15281	// op: Ra
15282	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
15283	op &= UINT64_C(`15`);
15284	op <<= `12`;
15285	Value \|= op;
15286	break;
15287	}
15288	case ARM::SMMLA:
15289	case ARM::SMMLAR:
15290	case ARM::SMMLS:
15291	case ARM::SMMLSR:
15292	case ARM::USADA8: {
15293	// op: p
15294	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
15295	op &= UINT64_C(`15`);
15296	op <<= `28`;
15297	Value \|= op;
15298	// op: Rd
15299	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
15300	op &= UINT64_C(`15`);
15301	op <<= `16`;
15302	Value \|= op;
15303	// op: Rn
15304	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
15305	op &= UINT64_C(`15`);
15306	Value \|= op;
15307	// op: Rm
15308	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
15309	op &= UINT64_C(`15`);
15310	op <<= `8`;
15311	Value \|= op;
15312	// op: Ra
15313	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
15314	op &= UINT64_C(`15`);
15315	op <<= `12`;
15316	Value \|= op;
15317	break;
15318	}
15319	case ARM::CMNzrsr:
15320	case ARM::CMPrsr:
15321	case ARM::TEQrsr:
15322	case ARM::TSTrsr: {
15323	// op: p
15324	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
15325	op &= UINT64_C(`15`);
15326	op <<= `28`;
15327	Value \|= op;
15328	// op: Rn
15329	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
15330	op &= UINT64_C(`15`);
15331	op <<= `16`;
15332	Value \|= op;
15333	// op: shift
15334	op = getSORegRegOpValue(MI, `1`, Fixups, STI);
15335	Value \|= (op & UINT64_C(`3840`));
15336	Value \|= (op & UINT64_C(`96`));
15337	Value \|= (op & UINT64_C(`15`));
15338	break;
15339	}
15340	case ARM::SMLAD:
15341	case ARM::SMLADX:
15342	case ARM::SMLSD:
15343	case ARM::SMLSDX: {
15344	// op: p
15345	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
15346	op &= UINT64_C(`15`);
15347	op <<= `28`;
15348	Value \|= op;
15349	// op: Rn
15350	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
15351	op &= UINT64_C(`15`);
15352	Value \|= op;
15353	// op: Rm
15354	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
15355	op &= UINT64_C(`15`);
15356	op <<= `8`;
15357	Value \|= op;
15358	// op: Ra
15359	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
15360	op &= UINT64_C(`15`);
15361	op <<= `12`;
15362	Value \|= op;
15363	// op: Rd
15364	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
15365	op &= UINT64_C(`15`);
15366	op <<= `16`;
15367	Value \|= op;
15368	break;
15369	}
15370	case ARM::SMLABB:
15371	case ARM::SMLABT:
15372	case ARM::SMLATB:
15373	case ARM::SMLATT:
15374	case ARM::SMLAWB:
15375	case ARM::SMLAWT: {
15376	// op: p
15377	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
15378	op &= UINT64_C(`15`);
15379	op <<= `28`;
15380	Value \|= op;
15381	// op: Rn
15382	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
15383	op &= UINT64_C(`15`);
15384	Value \|= op;
15385	// op: Rm
15386	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
15387	op &= UINT64_C(`15`);
15388	op <<= `8`;
15389	Value \|= op;
15390	// op: Rd
15391	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
15392	op &= UINT64_C(`15`);
15393	op <<= `16`;
15394	Value \|= op;
15395	// op: Ra
15396	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
15397	op &= UINT64_C(`15`);
15398	op <<= `12`;
15399	Value \|= op;
15400	break;
15401	}
15402	case ARM::LDRB_PRE_IMM:
15403	case ARM::LDR_PRE_IMM: {
15404	// op: p
15405	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
15406	op &= UINT64_C(`15`);
15407	op <<= `28`;
15408	Value \|= op;
15409	// op: Rt
15410	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
15411	op &= UINT64_C(`15`);
15412	op <<= `12`;
15413	Value \|= op;
15414	// op: addr
15415	op = getAddrModeImm12OpValue(MI, `2`, Fixups, STI);
15416	Value \|= (op & UINT64_C(`4096`)) << `11`;
15417	Value \|= (op & UINT64_C(`122880`)) << `3`;
15418	Value \|= (op & UINT64_C(`4095`));
15419	break;
15420	}
15421	case ARM::LDRBrs:
15422	case ARM::LDRrs:
15423	case ARM::STRBrs:
15424	case ARM::STRrs: {
15425	// op: p
15426	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
15427	op &= UINT64_C(`15`);
15428	op <<= `28`;
15429	Value \|= op;
15430	// op: Rt
15431	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
15432	op &= UINT64_C(`15`);
15433	op <<= `12`;
15434	Value \|= op;
15435	// op: shift
15436	op = getLdStSORegOpValue(MI, `1`, Fixups, STI);
15437	Value \|= (op & UINT64_C(`4096`)) << `11`;
15438	Value \|= (op & UINT64_C(`122880`)) << `3`;
15439	Value \|= (op & UINT64_C(`4064`));
15440	Value \|= (op & UINT64_C(`15`));
15441	break;
15442	}
15443	case ARM::STRB_PRE_IMM:
15444	case ARM::STR_PRE_IMM: {
15445	// op: p
15446	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
15447	op &= UINT64_C(`15`);
15448	op <<= `28`;
15449	Value \|= op;
15450	// op: Rt
15451	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
15452	op &= UINT64_C(`15`);
15453	op <<= `12`;
15454	Value \|= op;
15455	// op: addr
15456	op = getAddrModeImm12OpValue(MI, `2`, Fixups, STI);
15457	Value \|= (op & UINT64_C(`4096`)) << `11`;
15458	Value \|= (op & UINT64_C(`122880`)) << `3`;
15459	Value \|= (op & UINT64_C(`4095`));
15460	break;
15461	}
15462	case ARM::VFMAH:
15463	case ARM::VFMAS:
15464	case ARM::VFMSH:
15465	case ARM::VFMSS:
15466	case ARM::VFNMAH:
15467	case ARM::VFNMAS:
15468	case ARM::VFNMSH:
15469	case ARM::VFNMSS:
15470	case ARM::VMLAH:
15471	case ARM::VMLAS:
15472	case ARM::VMLSH:
15473	case ARM::VMLSS:
15474	case ARM::VNMLAH:
15475	case ARM::VNMLAS:
15476	case ARM::VNMLSH:
15477	case ARM::VNMLSS: {
15478	// op: p
15479	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
15480	op &= UINT64_C(`15`);
15481	op <<= `28`;
15482	Value \|= op;
15483	// op: Sd
15484	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
15485	Value \|= (op & UINT64_C(`1`)) << `22`;
15486	Value \|= (op & UINT64_C(`30`)) << `11`;
15487	// op: Sn
15488	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
15489	Value \|= (op & UINT64_C(`30`)) << `15`;
15490	Value \|= (op & UINT64_C(`1`)) << `7`;
15491	// op: Sm
15492	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
15493	Value \|= (op & UINT64_C(`1`)) << `5`;
15494	Value \|= (op & UINT64_C(`30`)) >> `1`;
15495	Value = VFPThumb2PostEncoder(MI, Value, STI);
15496	break;
15497	}
15498	case ARM::LDRH:
15499	case ARM::LDRSB:
15500	case ARM::LDRSH:
15501	case ARM::STRH: {
15502	// op: p
15503	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
15504	op &= UINT64_C(`15`);
15505	op <<= `28`;
15506	Value \|= op;
15507	// op: addr
15508	op = getAddrMode3OpValue(MI, `1`, Fixups, STI);
15509	Value \|= (op & UINT64_C(`256`)) << `15`;
15510	Value \|= (op & UINT64_C(`8192`)) << `9`;
15511	Value \|= (op & UINT64_C(`7680`)) << `7`;
15512	Value \|= (op & UINT64_C(`240`)) << `4`;
15513	Value \|= (op & UINT64_C(`15`));
15514	// op: Rt
15515	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
15516	op &= UINT64_C(`15`);
15517	op <<= `12`;
15518	Value \|= op;
15519	break;
15520	}
15521	case ARM::LDCL_OFFSET:
15522	case ARM::LDCL_PRE:
15523	case ARM::LDC_OFFSET:
15524	case ARM::LDC_PRE:
15525	case ARM::STCL_OFFSET:
15526	case ARM::STCL_PRE:
15527	case ARM::STC_OFFSET:
15528	case ARM::STC_PRE: {
15529	// op: p
15530	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
15531	op &= UINT64_C(`15`);
15532	op <<= `28`;
15533	Value \|= op;
15534	// op: addr
15535	op = getAddrMode5OpValue(MI, `2`, Fixups, STI);
15536	Value \|= (op & UINT64_C(`256`)) << `15`;
15537	Value \|= (op & UINT64_C(`7680`)) << `7`;
15538	Value \|= (op & UINT64_C(`255`));
15539	// op: cop
15540	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
15541	op &= UINT64_C(`15`);
15542	op <<= `8`;
15543	Value \|= op;
15544	// op: CRd
15545	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
15546	op &= UINT64_C(`15`);
15547	op <<= `12`;
15548	Value \|= op;
15549	break;
15550	}
15551	case ARM::LDRHTi:
15552	case ARM::LDRSBTi:
15553	case ARM::LDRSHTi: {
15554	// op: p
15555	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
15556	op &= UINT64_C(`15`);
15557	op <<= `28`;
15558	Value \|= op;
15559	// op: addr
15560	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
15561	op &= UINT64_C(`15`);
15562	op <<= `16`;
15563	Value \|= op;
15564	// op: Rt
15565	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
15566	op &= UINT64_C(`15`);
15567	op <<= `12`;
15568	Value \|= op;
15569	// op: offset
15570	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
15571	Value \|= (op & UINT64_C(`256`)) << `15`;
15572	Value \|= (op & UINT64_C(`240`)) << `4`;
15573	Value \|= (op & UINT64_C(`15`));
15574	break;
15575	}
15576	case ARM::STRHTi: {
15577	// op: p
15578	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
15579	op &= UINT64_C(`15`);
15580	op <<= `28`;
15581	Value \|= op;
15582	// op: addr
15583	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
15584	op &= UINT64_C(`15`);
15585	op <<= `16`;
15586	Value \|= op;
15587	// op: Rt
15588	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
15589	op &= UINT64_C(`15`);
15590	op <<= `12`;
15591	Value \|= op;
15592	// op: offset
15593	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
15594	Value \|= (op & UINT64_C(`256`)) << `15`;
15595	Value \|= (op & UINT64_C(`240`)) << `4`;
15596	Value \|= (op & UINT64_C(`15`));
15597	break;
15598	}
15599	case ARM::VLDR_P0_pre:
15600	case ARM::VSTR_P0_pre: {
15601	// op: p
15602	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
15603	op &= UINT64_C(`15`);
15604	op <<= `28`;
15605	Value \|= op;
15606	// op: addr
15607	op = getT2AddrModeImm7s4OpValue(MI, `2`, Fixups, STI);
15608	Value \|= (op & UINT64_C(`128`)) << `16`;
15609	Value \|= (op & UINT64_C(`3840`)) << `8`;
15610	Value \|= (op & UINT64_C(`127`));
15611	Value = VFPThumb2PostEncoder(MI, Value, STI);
15612	break;
15613	}
15614	case ARM::VLDR_P0_post:
15615	case ARM::VSTR_P0_post: {
15616	// op: p
15617	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
15618	op &= UINT64_C(`15`);
15619	op <<= `28`;
15620	Value \|= op;
15621	// op: addr
15622	op = getT2ScaledImmOpValue<`7`,`2`>(MI, `3`, Fixups, STI);
15623	Value \|= (op & UINT64_C(`128`)) << `16`;
15624	Value \|= (op & UINT64_C(`127`));
15625	// op: Rn
15626	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
15627	op &= UINT64_C(`15`);
15628	op <<= `16`;
15629	Value \|= op;
15630	Value = VFPThumb2PostEncoder(MI, Value, STI);
15631	break;
15632	}
15633	case ARM::VMOVSRR: {
15634	// op: p
15635	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
15636	op &= UINT64_C(`15`);
15637	op <<= `28`;
15638	Value \|= op;
15639	// op: dst1
15640	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
15641	Value \|= (op & UINT64_C(`1`)) << `5`;
15642	Value \|= (op & UINT64_C(`30`)) >> `1`;
15643	// op: src1
15644	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
15645	op &= UINT64_C(`15`);
15646	op <<= `12`;
15647	Value \|= op;
15648	// op: src2
15649	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
15650	op &= UINT64_C(`15`);
15651	op <<= `16`;
15652	Value \|= op;
15653	Value = VFPThumb2PostEncoder(MI, Value, STI);
15654	break;
15655	}
15656	case ARM::LDCL_POST:
15657	case ARM::LDC_POST:
15658	case ARM::STCL_POST:
15659	case ARM::STC_POST: {
15660	// op: p
15661	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
15662	op &= UINT64_C(`15`);
15663	op <<= `28`;
15664	Value \|= op;
15665	// op: offset
15666	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
15667	Value \|= (op & UINT64_C(`256`)) << `15`;
15668	Value \|= (op & UINT64_C(`255`));
15669	// op: addr
15670	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
15671	op &= UINT64_C(`15`);
15672	op <<= `16`;
15673	Value \|= op;
15674	// op: cop
15675	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
15676	op &= UINT64_C(`15`);
15677	op <<= `8`;
15678	Value \|= op;
15679	// op: CRd
15680	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
15681	op &= UINT64_C(`15`);
15682	op <<= `12`;
15683	Value \|= op;
15684	break;
15685	}
15686	case ARM::LDCL_OPTION:
15687	case ARM::LDC_OPTION:
15688	case ARM::STCL_OPTION:
15689	case ARM::STC_OPTION: {
15690	// op: p
15691	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
15692	op &= UINT64_C(`15`);
15693	op <<= `28`;
15694	Value \|= op;
15695	// op: option
15696	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
15697	op &= UINT64_C(`255`);
15698	Value \|= op;
15699	// op: addr
15700	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
15701	op &= UINT64_C(`15`);
15702	op <<= `16`;
15703	Value \|= op;
15704	// op: cop
15705	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
15706	op &= UINT64_C(`15`);
15707	op <<= `8`;
15708	Value \|= op;
15709	// op: CRd
15710	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
15711	op &= UINT64_C(`15`);
15712	op <<= `12`;
15713	Value \|= op;
15714	break;
15715	}
15716	case ARM::ADCrsi:
15717	case ARM::ADDrsi:
15718	case ARM::ANDrsi:
15719	case ARM::BICrsi:
15720	case ARM::EORrsi:
15721	case ARM::ORRrsi:
15722	case ARM::RSBrsi:
15723	case ARM::RSCrsi:
15724	case ARM::SBCrsi:
15725	case ARM::SUBrsi: {
15726	// op: p
15727	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
15728	op &= UINT64_C(`15`);
15729	op <<= `28`;
15730	Value \|= op;
15731	// op: s
15732	op = getCCOutOpValue(MI, `6`, Fixups, STI);
15733	op &= UINT64_C(`1`);
15734	op <<= `20`;
15735	Value \|= op;
15736	// op: Rd
15737	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
15738	op &= UINT64_C(`15`);
15739	op <<= `12`;
15740	Value \|= op;
15741	// op: Rn
15742	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
15743	op &= UINT64_C(`15`);
15744	op <<= `16`;
15745	Value \|= op;
15746	// op: shift
15747	op = getSORegImmOpValue(MI, `2`, Fixups, STI);
15748	Value \|= (op & UINT64_C(`4064`));
15749	Value \|= (op & UINT64_C(`15`));
15750	break;
15751	}
15752	case ARM::MVNsr: {
15753	// op: p
15754	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
15755	op &= UINT64_C(`15`);
15756	op <<= `28`;
15757	Value \|= op;
15758	// op: s
15759	op = getCCOutOpValue(MI, `6`, Fixups, STI);
15760	op &= UINT64_C(`1`);
15761	op <<= `20`;
15762	Value \|= op;
15763	// op: Rd
15764	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
15765	op &= UINT64_C(`15`);
15766	op <<= `12`;
15767	Value \|= op;
15768	// op: shift
15769	op = getSORegRegOpValue(MI, `1`, Fixups, STI);
15770	Value \|= (op & UINT64_C(`3840`));
15771	Value \|= (op & UINT64_C(`96`));
15772	Value \|= (op & UINT64_C(`15`));
15773	break;
15774	}
15775	case ARM::MOVsr: {
15776	// op: p
15777	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
15778	op &= UINT64_C(`15`);
15779	op <<= `28`;
15780	Value \|= op;
15781	// op: s
15782	op = getCCOutOpValue(MI, `6`, Fixups, STI);
15783	op &= UINT64_C(`1`);
15784	op <<= `20`;
15785	Value \|= op;
15786	// op: Rd
15787	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
15788	op &= UINT64_C(`15`);
15789	op <<= `12`;
15790	Value \|= op;
15791	// op: src
15792	op = getSORegRegOpValue(MI, `1`, Fixups, STI);
15793	Value \|= (op & UINT64_C(`3840`));
15794	Value \|= (op & UINT64_C(`96`));
15795	Value \|= (op & UINT64_C(`15`));
15796	break;
15797	}
15798	case ARM::MLA: {
15799	// op: p
15800	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
15801	op &= UINT64_C(`15`);
15802	op <<= `28`;
15803	Value \|= op;
15804	// op: s
15805	op = getCCOutOpValue(MI, `6`, Fixups, STI);
15806	op &= UINT64_C(`1`);
15807	op <<= `20`;
15808	Value \|= op;
15809	// op: Rd
15810	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
15811	op &= UINT64_C(`15`);
15812	op <<= `16`;
15813	Value \|= op;
15814	// op: Rm
15815	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
15816	op &= UINT64_C(`15`);
15817	op <<= `8`;
15818	Value \|= op;
15819	// op: Rn
15820	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
15821	op &= UINT64_C(`15`);
15822	Value \|= op;
15823	// op: Ra
15824	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
15825	op &= UINT64_C(`15`);
15826	op <<= `12`;
15827	Value \|= op;
15828	break;
15829	}
15830	case ARM::SMULL:
15831	case ARM::UMULL: {
15832	// op: p
15833	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
15834	op &= UINT64_C(`15`);
15835	op <<= `28`;
15836	Value \|= op;
15837	// op: s
15838	op = getCCOutOpValue(MI, `6`, Fixups, STI);
15839	op &= UINT64_C(`1`);
15840	op <<= `20`;
15841	Value \|= op;
15842	// op: RdLo
15843	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
15844	op &= UINT64_C(`15`);
15845	op <<= `12`;
15846	Value \|= op;
15847	// op: RdHi
15848	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
15849	op &= UINT64_C(`15`);
15850	op <<= `16`;
15851	Value \|= op;
15852	// op: Rm
15853	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
15854	op &= UINT64_C(`15`);
15855	op <<= `8`;
15856	Value \|= op;
15857	// op: Rn
15858	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
15859	op &= UINT64_C(`15`);
15860	Value \|= op;
15861	break;
15862	}
15863	case ARM::VMOVRRS: {
15864	// op: p
15865	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
15866	op &= UINT64_C(`15`);
15867	op <<= `28`;
15868	Value \|= op;
15869	// op: src1
15870	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
15871	Value \|= (op & UINT64_C(`1`)) << `5`;
15872	Value \|= (op & UINT64_C(`30`)) >> `1`;
15873	// op: Rt
15874	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
15875	op &= UINT64_C(`15`);
15876	op <<= `12`;
15877	Value \|= op;
15878	// op: Rt2
15879	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
15880	op &= UINT64_C(`15`);
15881	op <<= `16`;
15882	Value \|= op;
15883	Value = VFPThumb2PostEncoder(MI, Value, STI);
15884	break;
15885	}
15886	case ARM::MRRC: {
15887	// op: p
15888	op = getMachineOpValue(MI, MI.getOperand(`5`), Fixups, STI);
15889	op &= UINT64_C(`15`);
15890	op <<= `28`;
15891	Value \|= op;
15892	// op: Rt
15893	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
15894	op &= UINT64_C(`15`);
15895	op <<= `12`;
15896	Value \|= op;
15897	// op: Rt2
15898	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
15899	op &= UINT64_C(`15`);
15900	op <<= `16`;
15901	Value \|= op;
15902	// op: cop
15903	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
15904	op &= UINT64_C(`15`);
15905	op <<= `8`;
15906	Value \|= op;
15907	// op: opc1
15908	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
15909	op &= UINT64_C(`15`);
15910	op <<= `4`;
15911	Value \|= op;
15912	// op: CRm
15913	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
15914	op &= UINT64_C(`15`);
15915	Value \|= op;
15916	break;
15917	}
15918	case ARM::LDRH_PRE:
15919	case ARM::LDRSB_PRE:
15920	case ARM::LDRSH_PRE: {
15921	// op: p
15922	op = getMachineOpValue(MI, MI.getOperand(`5`), Fixups, STI);
15923	op &= UINT64_C(`15`);
15924	op <<= `28`;
15925	Value \|= op;
15926	// op: Rt
15927	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
15928	op &= UINT64_C(`15`);
15929	op <<= `12`;
15930	Value \|= op;
15931	// op: addr
15932	op = getAddrMode3OpValue(MI, `2`, Fixups, STI);
15933	Value \|= (op & UINT64_C(`256`)) << `15`;
15934	Value \|= (op & UINT64_C(`8192`)) << `9`;
15935	Value \|= (op & UINT64_C(`7680`)) << `7`;
15936	Value \|= (op & UINT64_C(`240`)) << `4`;
15937	Value \|= (op & UINT64_C(`15`));
15938	break;
15939	}
15940	case ARM::LDRB_PRE_REG:
15941	case ARM::LDR_PRE_REG: {
15942	// op: p
15943	op = getMachineOpValue(MI, MI.getOperand(`5`), Fixups, STI);
15944	op &= UINT64_C(`15`);
15945	op <<= `28`;
15946	Value \|= op;
15947	// op: Rt
15948	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
15949	op &= UINT64_C(`15`);
15950	op <<= `12`;
15951	Value \|= op;
15952	// op: addr
15953	op = getLdStSORegOpValue(MI, `2`, Fixups, STI);
15954	Value \|= (op & UINT64_C(`4096`)) << `11`;
15955	Value \|= (op & UINT64_C(`122880`)) << `3`;
15956	Value \|= (op & UINT64_C(`4064`));
15957	Value \|= (op & UINT64_C(`15`));
15958	break;
15959	}
15960	case ARM::LDRBT_POST_REG:
15961	case ARM::LDRB_POST_REG:
15962	case ARM::LDRT_POST_REG:
15963	case ARM::LDR_POST_REG: {
15964	// op: p
15965	op = getMachineOpValue(MI, MI.getOperand(`5`), Fixups, STI);
15966	op &= UINT64_C(`15`);
15967	op <<= `28`;
15968	Value \|= op;
15969	// op: Rt
15970	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
15971	op &= UINT64_C(`15`);
15972	op <<= `12`;
15973	Value \|= op;
15974	// op: offset
15975	op = getAddrMode2OffsetOpValue(MI, `3`, Fixups, STI);
15976	Value \|= (op & UINT64_C(`4096`)) << `11`;
15977	Value \|= (op & UINT64_C(`4064`));
15978	Value \|= (op & UINT64_C(`15`));
15979	// op: addr
15980	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
15981	op &= UINT64_C(`15`);
15982	op <<= `16`;
15983	Value \|= op;
15984	break;
15985	}
15986	case ARM::LDRBT_POST_IMM:
15987	case ARM::LDRB_POST_IMM:
15988	case ARM::LDRT_POST_IMM:
15989	case ARM::LDR_POST_IMM: {
15990	// op: p
15991	op = getMachineOpValue(MI, MI.getOperand(`5`), Fixups, STI);
15992	op &= UINT64_C(`15`);
15993	op <<= `28`;
15994	Value \|= op;
15995	// op: Rt
15996	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
15997	op &= UINT64_C(`15`);
15998	op <<= `12`;
15999	Value \|= op;
16000	// op: offset
16001	op = getAddrMode2OffsetOpValue(MI, `3`, Fixups, STI);
16002	Value \|= (op & UINT64_C(`4096`)) << `11`;
16003	Value \|= (op & UINT64_C(`4095`));
16004	// op: addr
16005	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
16006	op &= UINT64_C(`15`);
16007	op <<= `16`;
16008	Value \|= op;
16009	break;
16010	}
16011	case ARM::LDRH_POST:
16012	case ARM::LDRSB_POST:
16013	case ARM::LDRSH_POST: {
16014	// op: p
16015	op = getMachineOpValue(MI, MI.getOperand(`5`), Fixups, STI);
16016	op &= UINT64_C(`15`);
16017	op <<= `28`;
16018	Value \|= op;
16019	// op: Rt
16020	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
16021	op &= UINT64_C(`15`);
16022	op <<= `12`;
16023	Value \|= op;
16024	// op: offset
16025	op = getAddrMode3OffsetOpValue(MI, `3`, Fixups, STI);
16026	Value \|= (op & UINT64_C(`256`)) << `15`;
16027	Value \|= (op & UINT64_C(`512`)) << `13`;
16028	Value \|= (op & UINT64_C(`240`)) << `4`;
16029	Value \|= (op & UINT64_C(`15`));
16030	// op: addr
16031	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
16032	op &= UINT64_C(`15`);
16033	op <<= `16`;
16034	Value \|= op;
16035	break;
16036	}
16037	case ARM::STRH_PRE: {
16038	// op: p
16039	op = getMachineOpValue(MI, MI.getOperand(`5`), Fixups, STI);
16040	op &= UINT64_C(`15`);
16041	op <<= `28`;
16042	Value \|= op;
16043	// op: Rt
16044	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
16045	op &= UINT64_C(`15`);
16046	op <<= `12`;
16047	Value \|= op;
16048	// op: addr
16049	op = getAddrMode3OpValue(MI, `2`, Fixups, STI);
16050	Value \|= (op & UINT64_C(`256`)) << `15`;
16051	Value \|= (op & UINT64_C(`8192`)) << `9`;
16052	Value \|= (op & UINT64_C(`7680`)) << `7`;
16053	Value \|= (op & UINT64_C(`240`)) << `4`;
16054	Value \|= (op & UINT64_C(`15`));
16055	break;
16056	}
16057	case ARM::STRB_PRE_REG:
16058	case ARM::STR_PRE_REG: {
16059	// op: p
16060	op = getMachineOpValue(MI, MI.getOperand(`5`), Fixups, STI);
16061	op &= UINT64_C(`15`);
16062	op <<= `28`;
16063	Value \|= op;
16064	// op: Rt
16065	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
16066	op &= UINT64_C(`15`);
16067	op <<= `12`;
16068	Value \|= op;
16069	// op: addr
16070	op = getLdStSORegOpValue(MI, `2`, Fixups, STI);
16071	Value \|= (op & UINT64_C(`4096`)) << `11`;
16072	Value \|= (op & UINT64_C(`122880`)) << `3`;
16073	Value \|= (op & UINT64_C(`4064`));
16074	Value \|= (op & UINT64_C(`15`));
16075	break;
16076	}
16077	case ARM::STRBT_POST_REG:
16078	case ARM::STRB_POST_REG:
16079	case ARM::STRT_POST_REG:
16080	case ARM::STR_POST_REG: {
16081	// op: p
16082	op = getMachineOpValue(MI, MI.getOperand(`5`), Fixups, STI);
16083	op &= UINT64_C(`15`);
16084	op <<= `28`;
16085	Value \|= op;
16086	// op: Rt
16087	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
16088	op &= UINT64_C(`15`);
16089	op <<= `12`;
16090	Value \|= op;
16091	// op: offset
16092	op = getAddrMode2OffsetOpValue(MI, `3`, Fixups, STI);
16093	Value \|= (op & UINT64_C(`4096`)) << `11`;
16094	Value \|= (op & UINT64_C(`4064`));
16095	Value \|= (op & UINT64_C(`15`));
16096	// op: addr
16097	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
16098	op &= UINT64_C(`15`);
16099	op <<= `16`;
16100	Value \|= op;
16101	break;
16102	}
16103	case ARM::STRBT_POST_IMM:
16104	case ARM::STRB_POST_IMM:
16105	case ARM::STRT_POST_IMM:
16106	case ARM::STR_POST_IMM: {
16107	// op: p
16108	op = getMachineOpValue(MI, MI.getOperand(`5`), Fixups, STI);
16109	op &= UINT64_C(`15`);
16110	op <<= `28`;
16111	Value \|= op;
16112	// op: Rt
16113	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
16114	op &= UINT64_C(`15`);
16115	op <<= `12`;
16116	Value \|= op;
16117	// op: offset
16118	op = getAddrMode2OffsetOpValue(MI, `3`, Fixups, STI);
16119	Value \|= (op & UINT64_C(`4096`)) << `11`;
16120	Value \|= (op & UINT64_C(`4095`));
16121	// op: addr
16122	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
16123	op &= UINT64_C(`15`);
16124	op <<= `16`;
16125	Value \|= op;
16126	break;
16127	}
16128	case ARM::STRH_POST: {
16129	// op: p
16130	op = getMachineOpValue(MI, MI.getOperand(`5`), Fixups, STI);
16131	op &= UINT64_C(`15`);
16132	op <<= `28`;
16133	Value \|= op;
16134	// op: Rt
16135	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
16136	op &= UINT64_C(`15`);
16137	op <<= `12`;
16138	Value \|= op;
16139	// op: offset
16140	op = getAddrMode3OffsetOpValue(MI, `3`, Fixups, STI);
16141	Value \|= (op & UINT64_C(`256`)) << `15`;
16142	Value \|= (op & UINT64_C(`512`)) << `13`;
16143	Value \|= (op & UINT64_C(`240`)) << `4`;
16144	Value \|= (op & UINT64_C(`15`));
16145	// op: addr
16146	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
16147	op &= UINT64_C(`15`);
16148	op <<= `16`;
16149	Value \|= op;
16150	break;
16151	}
16152	case ARM::MCRR: {
16153	// op: p
16154	op = getMachineOpValue(MI, MI.getOperand(`5`), Fixups, STI);
16155	op &= UINT64_C(`15`);
16156	op <<= `28`;
16157	Value \|= op;
16158	// op: Rt
16159	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
16160	op &= UINT64_C(`15`);
16161	op <<= `12`;
16162	Value \|= op;
16163	// op: Rt2
16164	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
16165	op &= UINT64_C(`15`);
16166	op <<= `16`;
16167	Value \|= op;
16168	// op: cop
16169	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
16170	op &= UINT64_C(`15`);
16171	op <<= `8`;
16172	Value \|= op;
16173	// op: opc1
16174	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
16175	op &= UINT64_C(`15`);
16176	op <<= `4`;
16177	Value \|= op;
16178	// op: CRm
16179	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
16180	op &= UINT64_C(`15`);
16181	Value \|= op;
16182	break;
16183	}
16184	case ARM::LDRD:
16185	case ARM::STRD: {
16186	// op: p
16187	op = getMachineOpValue(MI, MI.getOperand(`5`), Fixups, STI);
16188	op &= UINT64_C(`15`);
16189	op <<= `28`;
16190	Value \|= op;
16191	// op: addr
16192	op = getAddrMode3OpValue(MI, `2`, Fixups, STI);
16193	Value \|= (op & UINT64_C(`256`)) << `15`;
16194	Value \|= (op & UINT64_C(`8192`)) << `9`;
16195	Value \|= (op & UINT64_C(`7680`)) << `7`;
16196	Value \|= (op & UINT64_C(`240`)) << `4`;
16197	Value \|= (op & UINT64_C(`15`));
16198	// op: Rt
16199	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
16200	op &= UINT64_C(`15`);
16201	op <<= `12`;
16202	Value \|= op;
16203	break;
16204	}
16205	case ARM::LDRHTr:
16206	case ARM::LDRSBTr:
16207	case ARM::LDRSHTr: {
16208	// op: p
16209	op = getMachineOpValue(MI, MI.getOperand(`5`), Fixups, STI);
16210	op &= UINT64_C(`15`);
16211	op <<= `28`;
16212	Value \|= op;
16213	// op: addr
16214	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
16215	op &= UINT64_C(`15`);
16216	op <<= `16`;
16217	Value \|= op;
16218	// op: Rt
16219	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
16220	op &= UINT64_C(`15`);
16221	op <<= `12`;
16222	Value \|= op;
16223	// op: Rm
16224	op = getPostIdxRegOpValue(MI, `3`, Fixups, STI);
16225	Value \|= (op & UINT64_C(`16`)) << `19`;
16226	Value \|= (op & UINT64_C(`15`));
16227	break;
16228	}
16229	case ARM::STRHTr: {
16230	// op: p
16231	op = getMachineOpValue(MI, MI.getOperand(`5`), Fixups, STI);
16232	op &= UINT64_C(`15`);
16233	op <<= `28`;
16234	Value \|= op;
16235	// op: addr
16236	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
16237	op &= UINT64_C(`15`);
16238	op <<= `16`;
16239	Value \|= op;
16240	// op: Rt
16241	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
16242	op &= UINT64_C(`15`);
16243	op <<= `12`;
16244	Value \|= op;
16245	// op: Rm
16246	op = getPostIdxRegOpValue(MI, `3`, Fixups, STI);
16247	Value \|= (op & UINT64_C(`16`)) << `19`;
16248	Value \|= (op & UINT64_C(`15`));
16249	break;
16250	}
16251	case ARM::ADCrsr:
16252	case ARM::ADDrsr:
16253	case ARM::ANDrsr:
16254	case ARM::BICrsr:
16255	case ARM::EORrsr:
16256	case ARM::ORRrsr:
16257	case ARM::RSBrsr:
16258	case ARM::RSCrsr:
16259	case ARM::SBCrsr:
16260	case ARM::SUBrsr: {
16261	// op: p
16262	op = getMachineOpValue(MI, MI.getOperand(`5`), Fixups, STI);
16263	op &= UINT64_C(`15`);
16264	op <<= `28`;
16265	Value \|= op;
16266	// op: s
16267	op = getCCOutOpValue(MI, `7`, Fixups, STI);
16268	op &= UINT64_C(`1`);
16269	op <<= `20`;
16270	Value \|= op;
16271	// op: Rd
16272	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
16273	op &= UINT64_C(`15`);
16274	op <<= `12`;
16275	Value \|= op;
16276	// op: Rn
16277	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
16278	op &= UINT64_C(`15`);
16279	op <<= `16`;
16280	Value \|= op;
16281	// op: shift
16282	op = getSORegRegOpValue(MI, `2`, Fixups, STI);
16283	Value \|= (op & UINT64_C(`3840`));
16284	Value \|= (op & UINT64_C(`96`));
16285	Value \|= (op & UINT64_C(`15`));
16286	break;
16287	}
16288	case ARM::UMAAL: {
16289	// op: p
16290	op = getMachineOpValue(MI, MI.getOperand(`6`), Fixups, STI);
16291	op &= UINT64_C(`15`);
16292	op <<= `28`;
16293	Value \|= op;
16294	// op: RdLo
16295	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
16296	op &= UINT64_C(`15`);
16297	op <<= `12`;
16298	Value \|= op;
16299	// op: RdHi
16300	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
16301	op &= UINT64_C(`15`);
16302	op <<= `16`;
16303	Value \|= op;
16304	// op: Rm
16305	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
16306	op &= UINT64_C(`15`);
16307	op <<= `8`;
16308	Value \|= op;
16309	// op: Rn
16310	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
16311	op &= UINT64_C(`15`);
16312	Value \|= op;
16313	break;
16314	}
16315	case ARM::SMLALBB:
16316	case ARM::SMLALBT:
16317	case ARM::SMLALD:
16318	case ARM::SMLALDX:
16319	case ARM::SMLALTB:
16320	case ARM::SMLALTT:
16321	case ARM::SMLSLD:
16322	case ARM::SMLSLDX: {
16323	// op: p
16324	op = getMachineOpValue(MI, MI.getOperand(`6`), Fixups, STI);
16325	op &= UINT64_C(`15`);
16326	op <<= `28`;
16327	Value \|= op;
16328	// op: Rn
16329	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
16330	op &= UINT64_C(`15`);
16331	Value \|= op;
16332	// op: Rm
16333	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
16334	op &= UINT64_C(`15`);
16335	op <<= `8`;
16336	Value \|= op;
16337	// op: RdLo
16338	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
16339	op &= UINT64_C(`15`);
16340	op <<= `12`;
16341	Value \|= op;
16342	// op: RdHi
16343	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
16344	op &= UINT64_C(`15`);
16345	op <<= `16`;
16346	Value \|= op;
16347	break;
16348	}
16349	case ARM::LDRD_PRE: {
16350	// op: p
16351	op = getMachineOpValue(MI, MI.getOperand(`6`), Fixups, STI);
16352	op &= UINT64_C(`15`);
16353	op <<= `28`;
16354	Value \|= op;
16355	// op: Rt
16356	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
16357	op &= UINT64_C(`15`);
16358	op <<= `12`;
16359	Value \|= op;
16360	// op: addr
16361	op = getAddrMode3OpValue(MI, `3`, Fixups, STI);
16362	Value \|= (op & UINT64_C(`256`)) << `15`;
16363	Value \|= (op & UINT64_C(`8192`)) << `9`;
16364	Value \|= (op & UINT64_C(`7680`)) << `7`;
16365	Value \|= (op & UINT64_C(`240`)) << `4`;
16366	Value \|= (op & UINT64_C(`15`));
16367	break;
16368	}
16369	case ARM::MRC: {
16370	// op: p
16371	op = getMachineOpValue(MI, MI.getOperand(`6`), Fixups, STI);
16372	op &= UINT64_C(`15`);
16373	op <<= `28`;
16374	Value \|= op;
16375	// op: Rt
16376	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
16377	op &= UINT64_C(`15`);
16378	op <<= `12`;
16379	Value \|= op;
16380	// op: cop
16381	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
16382	op &= UINT64_C(`15`);
16383	op <<= `8`;
16384	Value \|= op;
16385	// op: opc1
16386	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
16387	op &= UINT64_C(`7`);
16388	op <<= `21`;
16389	Value \|= op;
16390	// op: opc2
16391	op = getMachineOpValue(MI, MI.getOperand(`5`), Fixups, STI);
16392	op &= UINT64_C(`7`);
16393	op <<= `5`;
16394	Value \|= op;
16395	// op: CRm
16396	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
16397	op &= UINT64_C(`15`);
16398	Value \|= op;
16399	// op: CRn
16400	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
16401	op &= UINT64_C(`15`);
16402	op <<= `16`;
16403	Value \|= op;
16404	break;
16405	}
16406	case ARM::LDRD_POST: {
16407	// op: p
16408	op = getMachineOpValue(MI, MI.getOperand(`6`), Fixups, STI);
16409	op &= UINT64_C(`15`);
16410	op <<= `28`;
16411	Value \|= op;
16412	// op: Rt
16413	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
16414	op &= UINT64_C(`15`);
16415	op <<= `12`;
16416	Value \|= op;
16417	// op: offset
16418	op = getAddrMode3OffsetOpValue(MI, `4`, Fixups, STI);
16419	Value \|= (op & UINT64_C(`256`)) << `15`;
16420	Value \|= (op & UINT64_C(`512`)) << `13`;
16421	Value \|= (op & UINT64_C(`240`)) << `4`;
16422	Value \|= (op & UINT64_C(`15`));
16423	// op: addr
16424	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
16425	op &= UINT64_C(`15`);
16426	op <<= `16`;
16427	Value \|= op;
16428	break;
16429	}
16430	case ARM::STRD_PRE: {
16431	// op: p
16432	op = getMachineOpValue(MI, MI.getOperand(`6`), Fixups, STI);
16433	op &= UINT64_C(`15`);
16434	op <<= `28`;
16435	Value \|= op;
16436	// op: Rt
16437	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
16438	op &= UINT64_C(`15`);
16439	op <<= `12`;
16440	Value \|= op;
16441	// op: addr
16442	op = getAddrMode3OpValue(MI, `3`, Fixups, STI);
16443	Value \|= (op & UINT64_C(`256`)) << `15`;
16444	Value \|= (op & UINT64_C(`8192`)) << `9`;
16445	Value \|= (op & UINT64_C(`7680`)) << `7`;
16446	Value \|= (op & UINT64_C(`240`)) << `4`;
16447	Value \|= (op & UINT64_C(`15`));
16448	break;
16449	}
16450	case ARM::STRD_POST: {
16451	// op: p
16452	op = getMachineOpValue(MI, MI.getOperand(`6`), Fixups, STI);
16453	op &= UINT64_C(`15`);
16454	op <<= `28`;
16455	Value \|= op;
16456	// op: Rt
16457	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
16458	op &= UINT64_C(`15`);
16459	op <<= `12`;
16460	Value \|= op;
16461	// op: offset
16462	op = getAddrMode3OffsetOpValue(MI, `4`, Fixups, STI);
16463	Value \|= (op & UINT64_C(`256`)) << `15`;
16464	Value \|= (op & UINT64_C(`512`)) << `13`;
16465	Value \|= (op & UINT64_C(`240`)) << `4`;
16466	Value \|= (op & UINT64_C(`15`));
16467	// op: addr
16468	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
16469	op &= UINT64_C(`15`);
16470	op <<= `16`;
16471	Value \|= op;
16472	break;
16473	}
16474	case ARM::MCR: {
16475	// op: p
16476	op = getMachineOpValue(MI, MI.getOperand(`6`), Fixups, STI);
16477	op &= UINT64_C(`15`);
16478	op <<= `28`;
16479	Value \|= op;
16480	// op: Rt
16481	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
16482	op &= UINT64_C(`15`);
16483	op <<= `12`;
16484	Value \|= op;
16485	// op: cop
16486	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
16487	op &= UINT64_C(`15`);
16488	op <<= `8`;
16489	Value \|= op;
16490	// op: opc1
16491	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
16492	op &= UINT64_C(`7`);
16493	op <<= `21`;
16494	Value \|= op;
16495	// op: opc2
16496	op = getMachineOpValue(MI, MI.getOperand(`5`), Fixups, STI);
16497	op &= UINT64_C(`7`);
16498	op <<= `5`;
16499	Value \|= op;
16500	// op: CRm
16501	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
16502	op &= UINT64_C(`15`);
16503	Value \|= op;
16504	// op: CRn
16505	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
16506	op &= UINT64_C(`15`);
16507	op <<= `16`;
16508	Value \|= op;
16509	break;
16510	}
16511	case ARM::CDP: {
16512	// op: p
16513	op = getMachineOpValue(MI, MI.getOperand(`6`), Fixups, STI);
16514	op &= UINT64_C(`15`);
16515	op <<= `28`;
16516	Value \|= op;
16517	// op: opc1
16518	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
16519	op &= UINT64_C(`15`);
16520	op <<= `20`;
16521	Value \|= op;
16522	// op: CRn
16523	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
16524	op &= UINT64_C(`15`);
16525	op <<= `16`;
16526	Value \|= op;
16527	// op: CRd
16528	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
16529	op &= UINT64_C(`15`);
16530	op <<= `12`;
16531	Value \|= op;
16532	// op: cop
16533	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
16534	op &= UINT64_C(`15`);
16535	op <<= `8`;
16536	Value \|= op;
16537	// op: opc2
16538	op = getMachineOpValue(MI, MI.getOperand(`5`), Fixups, STI);
16539	op &= UINT64_C(`7`);
16540	op <<= `5`;
16541	Value \|= op;
16542	// op: CRm
16543	op = getMachineOpValue(MI, MI.getOperand(`4`), Fixups, STI);
16544	op &= UINT64_C(`15`);
16545	Value \|= op;
16546	break;
16547	}
16548	case ARM::SMLAL:
16549	case ARM::UMLAL: {
16550	// op: p
16551	op = getMachineOpValue(MI, MI.getOperand(`6`), Fixups, STI);
16552	op &= UINT64_C(`15`);
16553	op <<= `28`;
16554	Value \|= op;
16555	// op: s
16556	op = getCCOutOpValue(MI, `8`, Fixups, STI);
16557	op &= UINT64_C(`1`);
16558	op <<= `20`;
16559	Value \|= op;
16560	// op: RdLo
16561	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
16562	op &= UINT64_C(`15`);
16563	op <<= `12`;
16564	Value \|= op;
16565	// op: RdHi
16566	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
16567	op &= UINT64_C(`15`);
16568	op <<= `16`;
16569	Value \|= op;
16570	// op: Rm
16571	op = getMachineOpValue(MI, MI.getOperand(`3`), Fixups, STI);
16572	op &= UINT64_C(`15`);
16573	op <<= `8`;
16574	Value \|= op;
16575	// op: Rn
16576	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
16577	op &= UINT64_C(`15`);
16578	Value \|= op;
16579	break;
16580	}
16581	case ARM::tPUSH: {
16582	// op: regs
16583	op = getRegisterListOpValue(MI, `2`, Fixups, STI);
16584	Value \|= (op & UINT64_C(`16384`)) >> `6`;
16585	Value \|= (op & UINT64_C(`255`));
16586	break;
16587	}
16588	case ARM::VSCCLRMS: {
16589	// op: regs
16590	op = getRegisterListOpValue(MI, `2`, Fixups, STI);
16591	Value \|= (op & UINT64_C(`256`)) << `14`;
16592	Value \|= (op & UINT64_C(`7680`)) << `3`;
16593	Value \|= (op & UINT64_C(`255`));
16594	Value = VFPThumb2PostEncoder(MI, Value, STI);
16595	break;
16596	}
16597	case ARM::tPOP: {
16598	// op: regs
16599	op = getRegisterListOpValue(MI, `2`, Fixups, STI);
16600	Value \|= (op & UINT64_C(`32768`)) >> `7`;
16601	Value \|= (op & UINT64_C(`255`));
16602	break;
16603	}
16604	case ARM::VSCCLRMD: {
16605	// op: regs
16606	op = getRegisterListOpValue(MI, `2`, Fixups, STI);
16607	Value \|= (op & UINT64_C(`4096`)) << `10`;
16608	Value \|= (op & UINT64_C(`3840`)) << `4`;
16609	Value \|= (op & UINT64_C(`254`));
16610	Value = VFPThumb2PostEncoder(MI, Value, STI);
16611	break;
16612	}
16613	case ARM::t2CLRM: {
16614	// op: regs
16615	op = getRegisterListOpValue(MI, `2`, Fixups, STI);
16616	Value \|= (op & UINT64_C(`49152`));
16617	Value \|= (op & UINT64_C(`8191`));
16618	break;
16619	}
16620	case ARM::t2MOVr:
16621	case ARM::t2MVNr:
16622	case ARM::t2RRX: {
16623	// op: s
16624	op = getCCOutOpValue(MI, `4`, Fixups, STI);
16625	op &= UINT64_C(`1`);
16626	op <<= `20`;
16627	Value \|= op;
16628	// op: Rd
16629	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
16630	op &= UINT64_C(`15`);
16631	op <<= `8`;
16632	Value \|= op;
16633	// op: Rm
16634	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
16635	op &= UINT64_C(`15`);
16636	Value \|= op;
16637	break;
16638	}
16639	case ARM::t2MOVi:
16640	case ARM::t2MVNi: {
16641	// op: s
16642	op = getCCOutOpValue(MI, `4`, Fixups, STI);
16643	op &= UINT64_C(`1`);
16644	op <<= `20`;
16645	Value \|= op;
16646	// op: Rd
16647	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
16648	op &= UINT64_C(`15`);
16649	op <<= `8`;
16650	Value \|= op;
16651	// op: imm
16652	op = getT2SOImmOpValue(MI, `1`, Fixups, STI);
16653	Value \|= (op & UINT64_C(`2048`)) << `15`;
16654	Value \|= (op & UINT64_C(`1792`)) << `4`;
16655	Value \|= (op & UINT64_C(`255`));
16656	break;
16657	}
16658	case ARM::t2ASRri:
16659	case ARM::t2LSLri:
16660	case ARM::t2LSRri:
16661	case ARM::t2RORri: {
16662	// op: s
16663	op = getCCOutOpValue(MI, `5`, Fixups, STI);
16664	op &= UINT64_C(`1`);
16665	op <<= `20`;
16666	Value \|= op;
16667	// op: Rd
16668	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
16669	op &= UINT64_C(`15`);
16670	op <<= `8`;
16671	Value \|= op;
16672	// op: Rm
16673	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
16674	op &= UINT64_C(`15`);
16675	Value \|= op;
16676	// op: imm
16677	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
16678	Value \|= (op & UINT64_C(`28`)) << `10`;
16679	Value \|= (op & UINT64_C(`3`)) << `6`;
16680	break;
16681	}
16682	case ARM::t2ADCrr:
16683	case ARM::t2ADDrr:
16684	case ARM::t2ANDrr:
16685	case ARM::t2ASRrr:
16686	case ARM::t2BICrr:
16687	case ARM::t2EORrr:
16688	case ARM::t2LSLrr:
16689	case ARM::t2LSRrr:
16690	case ARM::t2ORNrr:
16691	case ARM::t2ORRrr:
16692	case ARM::t2RORrr:
16693	case ARM::t2RSBrr:
16694	case ARM::t2SBCrr:
16695	case ARM::t2SUBrr: {
16696	// op: s
16697	op = getCCOutOpValue(MI, `5`, Fixups, STI);
16698	op &= UINT64_C(`1`);
16699	op <<= `20`;
16700	Value \|= op;
16701	// op: Rd
16702	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
16703	op &= UINT64_C(`15`);
16704	op <<= `8`;
16705	Value \|= op;
16706	// op: Rn
16707	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
16708	op &= UINT64_C(`15`);
16709	op <<= `16`;
16710	Value \|= op;
16711	// op: Rm
16712	op = getMachineOpValue(MI, MI.getOperand(`2`), Fixups, STI);
16713	op &= UINT64_C(`15`);
16714	Value \|= op;
16715	break;
16716	}
16717	case ARM::t2ADCri:
16718	case ARM::t2ADDri:
16719	case ARM::t2ANDri:
16720	case ARM::t2BICri:
16721	case ARM::t2EORri:
16722	case ARM::t2ORNri:
16723	case ARM::t2ORRri:
16724	case ARM::t2RSBri:
16725	case ARM::t2SBCri:
16726	case ARM::t2SUBri: {
16727	// op: s
16728	op = getCCOutOpValue(MI, `5`, Fixups, STI);
16729	op &= UINT64_C(`1`);
16730	op <<= `20`;
16731	Value \|= op;
16732	// op: Rd
16733	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
16734	op &= UINT64_C(`15`);
16735	op <<= `8`;
16736	Value \|= op;
16737	// op: Rn
16738	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
16739	op &= UINT64_C(`15`);
16740	op <<= `16`;
16741	Value \|= op;
16742	// op: imm
16743	op = getT2SOImmOpValue(MI, `2`, Fixups, STI);
16744	Value \|= (op & UINT64_C(`2048`)) << `15`;
16745	Value \|= (op & UINT64_C(`1792`)) << `4`;
16746	Value \|= (op & UINT64_C(`255`));
16747	break;
16748	}
16749	case ARM::t2MVNs: {
16750	// op: s
16751	op = getCCOutOpValue(MI, `5`, Fixups, STI);
16752	op &= UINT64_C(`1`);
16753	op <<= `20`;
16754	Value \|= op;
16755	// op: Rd
16756	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
16757	op &= UINT64_C(`15`);
16758	op <<= `8`;
16759	Value \|= op;
16760	// op: ShiftedRm
16761	op = getT2SORegOpValue(MI, `1`, Fixups, STI);
16762	Value \|= (op & UINT64_C(`3584`)) << `3`;
16763	Value \|= (op & UINT64_C(`480`)) >> `1`;
16764	Value \|= (op & UINT64_C(`15`));
16765	break;
16766	}
16767	case ARM::t2ADDspImm:
16768	case ARM::t2SUBspImm: {
16769	// op: s
16770	op = getCCOutOpValue(MI, `5`, Fixups, STI);
16771	op &= UINT64_C(`1`);
16772	op <<= `20`;
16773	Value \|= op;
16774	// op: imm
16775	op = getT2SOImmOpValue(MI, `2`, Fixups, STI);
16776	Value \|= (op & UINT64_C(`2048`)) << `15`;
16777	Value \|= (op & UINT64_C(`1792`)) << `4`;
16778	Value \|= (op & UINT64_C(`255`));
16779	break;
16780	}
16781	case ARM::t2ADCrs:
16782	case ARM::t2ADDrs:
16783	case ARM::t2ANDrs:
16784	case ARM::t2BICrs:
16785	case ARM::t2EORrs:
16786	case ARM::t2ORNrs:
16787	case ARM::t2ORRrs:
16788	case ARM::t2RSBrs:
16789	case ARM::t2SBCrs:
16790	case ARM::t2SUBrs: {
16791	// op: s
16792	op = getCCOutOpValue(MI, `6`, Fixups, STI);
16793	op &= UINT64_C(`1`);
16794	op <<= `20`;
16795	Value \|= op;
16796	// op: Rd
16797	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
16798	op &= UINT64_C(`15`);
16799	op <<= `8`;
16800	Value \|= op;
16801	// op: Rn
16802	op = getMachineOpValue(MI, MI.getOperand(`1`), Fixups, STI);
16803	op &= UINT64_C(`15`);
16804	op <<= `16`;
16805	Value \|= op;
16806	// op: ShiftedRm
16807	op = getT2SORegOpValue(MI, `2`, Fixups, STI);
16808	Value \|= (op & UINT64_C(`3584`)) << `3`;
16809	Value \|= (op & UINT64_C(`480`)) >> `1`;
16810	Value \|= (op & UINT64_C(`15`));
16811	break;
16812	}
16813	case ARM::PLDWrs:
16814	case ARM::PLDrs:
16815	case ARM::PLIrs: {
16816	// op: shift
16817	op = getLdStSORegOpValue(MI, `0`, Fixups, STI);
16818	Value \|= (op & UINT64_C(`4096`)) << `11`;
16819	Value \|= (op & UINT64_C(`122880`)) << `3`;
16820	Value \|= (op & UINT64_C(`4064`));
16821	Value \|= (op & UINT64_C(`15`));
16822	break;
16823	}
16824	case ARM::BLXi: {
16825	// op: target
16826	op = getARMBLXTargetOpValue(MI, `0`, Fixups, STI);
16827	Value \|= (op & UINT64_C(`1`)) << `24`;
16828	Value \|= (op & UINT64_C(`33554430`)) >> `1`;
16829	break;
16830	}
16831	case ARM::tB: {
16832	// op: target
16833	op = getThumbBRTargetOpValue(MI, `0`, Fixups, STI);
16834	op &= UINT64_C(`2047`);
16835	Value \|= op;
16836	break;
16837	}
16838	case ARM::t2B: {
16839	// op: target
16840	op = getThumbBranchTargetOpValue(MI, `0`, Fixups, STI);
16841	Value \|= (op & UINT64_C(`8388608`)) << `3`;
16842	Value \|= (op & UINT64_C(`2095104`)) << `5`;
16843	Value \|= (op & UINT64_C(`4194304`)) >> `9`;
16844	Value \|= (op & UINT64_C(`2097152`)) >> `10`;
16845	Value \|= (op & UINT64_C(`2047`));
16846	break;
16847	}
16848	case ARM::tCBNZ:
16849	case ARM::tCBZ: {
16850	// op: target
16851	op = getThumbCBTargetOpValue(MI, `1`, Fixups, STI);
16852	Value \|= (op & UINT64_C(`32`)) << `4`;
16853	Value \|= (op & UINT64_C(`31`)) << `3`;
16854	// op: Rn
16855	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
16856	op &= UINT64_C(`7`);
16857	Value \|= op;
16858	break;
16859	}
16860	case ARM::BKPT:
16861	case ARM::HLT: {
16862	// op: val
16863	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
16864	Value \|= (op & UINT64_C(`65520`)) << `4`;
16865	Value \|= (op & UINT64_C(`15`));
16866	break;
16867	}
16868	case ARM::tBKPT: {
16869	// op: val
16870	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
16871	op &= UINT64_C(`255`);
16872	Value \|= op;
16873	break;
16874	}
16875	case ARM::tHLT: {
16876	// op: val
16877	op = getMachineOpValue(MI, MI.getOperand(`0`), Fixups, STI);
16878	op &= UINT64_C(`63`);
16879	Value \|= op;
16880	break;
16881	}
16882	default:
16883	std::string msg;
16884	raw_string_ostream Msg(msg);
16885	Msg << "Not supported instr: " << MI;
16886	report_fatal_error(Msg.str());
16887	}
16888	return Value;
16889	}
16890
16891	#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
16892	#undef ENABLE_INSTR_PREDICATE_VERIFIER
16893	#include <sstream>
16894
16895	// Bits for subtarget features that participate in instruction matching.
16896	enum SubtargetFeatureBits : uint8_t {
16897	Feature_HasV4TBit = `33`,
16898	Feature_HasV5TBit = `34`,
16899	Feature_HasV5TEBit = `35`,
16900	Feature_HasV6Bit = `36`,
16901	Feature_HasV6MBit = `38`,
16902	Feature_HasV8MBaselineBit = `43`,
16903	Feature_HasV8MMainlineBit = `44`,
16904	Feature_HasV8_1MMainlineBit = `45`,
16905	Feature_HasMVEIntBit = `25`,
16906	Feature_HasMVEFloatBit = `24`,
16907	Feature_HasCDEBit = `4`,
16908	Feature_HasFPRegsBit = `17`,
16909	Feature_HasFPRegs16Bit = `18`,
16910	Feature_HasNoFPRegs16Bit = `28`,
16911	Feature_HasFPRegs64Bit = `19`,
16912	Feature_HasFPRegsV8_1MBit = `20`,
16913	Feature_HasV6T2Bit = `39`,
16914	Feature_HasV6KBit = `37`,
16915	Feature_HasV7Bit = `40`,
16916	Feature_HasV8Bit = `42`,
16917	Feature_PreV8Bit = `62`,
16918	Feature_HasV8_1aBit = `46`,
16919	Feature_HasV8_2aBit = `47`,
16920	Feature_HasV8_3aBit = `48`,
16921	Feature_HasV8_4aBit = `49`,
16922	Feature_HasV8_5aBit = `50`,
16923	Feature_HasV8_6aBit = `51`,
16924	Feature_HasV8_7aBit = `52`,
16925	Feature_HasVFP2Bit = `53`,
16926	Feature_HasVFP3Bit = `54`,
16927	Feature_HasVFP4Bit = `55`,
16928	Feature_HasDPVFPBit = `9`,
16929	Feature_HasFPARMv8Bit = `16`,
16930	Feature_HasNEONBit = `27`,
16931	Feature_HasSHA2Bit = `31`,
16932	Feature_HasAESBit = `1`,
16933	Feature_HasCryptoBit = `6`,
16934	Feature_HasDotProdBit = `13`,
16935	Feature_HasCRCBit = `5`,
16936	Feature_HasRASBit = `29`,
16937	Feature_HasLOBBit = `22`,
16938	Feature_HasFP16Bit = `14`,
16939	Feature_HasFullFP16Bit = `21`,
16940	Feature_HasFP16FMLBit = `15`,
16941	Feature_HasBF16Bit = `3`,
16942	Feature_HasMatMulInt8Bit = `26`,
16943	Feature_HasDivideInThumbBit = `12`,
16944	Feature_HasDivideInARMBit = `11`,
16945	Feature_HasDSPBit = `10`,
16946	Feature_HasDBBit = `7`,
16947	Feature_HasDFBBit = `8`,
16948	Feature_HasV7ClrexBit = `41`,
16949	Feature_HasAcquireReleaseBit = `2`,
16950	Feature_HasMPBit = `23`,
16951	Feature_HasVirtualizationBit = `56`,
16952	Feature_HasTrustZoneBit = `32`,
16953	Feature_Has8MSecExtBit = `0`,
16954	Feature_IsThumbBit = `60`,
16955	Feature_IsThumb2Bit = `61`,
16956	Feature_IsMClassBit = `58`,
16957	Feature_IsNotMClassBit = `59`,
16958	Feature_IsARMBit = `57`,
16959	Feature_UseNaClTrapBit = `63`,
16960	Feature_UseNegativeImmediatesBit = `64`,
16961	Feature_HasSBBit = `30`,
16962	};
16963
16964	#ifndef NDEBUG
16965	static const char *SubtargetFeatureNames[] = {
16966	"Feature_Has8MSecExt",
16967	"Feature_HasAES",
16968	"Feature_HasAcquireRelease",
16969	"Feature_HasBF16",
16970	"Feature_HasCDE",
16971	"Feature_HasCRC",
16972	"Feature_HasCrypto",
16973	"Feature_HasDB",
16974	"Feature_HasDFB",
16975	"Feature_HasDPVFP",
16976	"Feature_HasDSP",
16977	"Feature_HasDivideInARM",
16978	"Feature_HasDivideInThumb",
16979	"Feature_HasDotProd",
16980	"Feature_HasFP16",
16981	"Feature_HasFP16FML",
16982	"Feature_HasFPARMv8",
16983	"Feature_HasFPRegs",
16984	"Feature_HasFPRegs16",
16985	"Feature_HasFPRegs64",
16986	"Feature_HasFPRegsV8_1M",
16987	"Feature_HasFullFP16",
16988	"Feature_HasLOB",
16989	"Feature_HasMP",
16990	"Feature_HasMVEFloat",
16991	"Feature_HasMVEInt",
16992	"Feature_HasMatMulInt8",
16993	"Feature_HasNEON",
16994	"Feature_HasNoFPRegs16",
16995	"Feature_HasRAS",
16996	"Feature_HasSB",
16997	"Feature_HasSHA2",
16998	"Feature_HasTrustZone",
16999	"Feature_HasV4T",
17000	"Feature_HasV5T",
17001	"Feature_HasV5TE",
17002	"Feature_HasV6",
17003	"Feature_HasV6K",
17004	"Feature_HasV6M",
17005	"Feature_HasV6T2",
17006	"Feature_HasV7",
17007	"Feature_HasV7Clrex",
17008	"Feature_HasV8",
17009	"Feature_HasV8MBaseline",
17010	"Feature_HasV8MMainline",
17011	"Feature_HasV8_1MMainline",
17012	"Feature_HasV8_1a",
17013	"Feature_HasV8_2a",
17014	"Feature_HasV8_3a",
17015	"Feature_HasV8_4a",
17016	"Feature_HasV8_5a",
17017	"Feature_HasV8_6a",
17018	"Feature_HasV8_7a",
17019	"Feature_HasVFP2",
17020	"Feature_HasVFP3",
17021	"Feature_HasVFP4",
17022	"Feature_HasVirtualization",
17023	"Feature_IsARM",
17024	"Feature_IsMClass",
17025	"Feature_IsNotMClass",
17026	"Feature_IsThumb",
17027	"Feature_IsThumb2",
17028	"Feature_PreV8",
17029	"Feature_UseNaClTrap",
17030	"Feature_UseNegativeImmediates",
17031	nullptr
17032	};
17033
17034	#endif // NDEBUG
17035	FeatureBitset ARMMCCodeEmitter::
17036	computeAvailableFeatures(const FeatureBitset &FB) const {
17037	FeatureBitset Features;
17038	if (FB[ARM::HasV4TOps])
17039	Features.set(Feature_HasV4TBit);
17040	if (FB[ARM::HasV5TOps])
17041	Features.set(Feature_HasV5TBit);
17042	if (FB[ARM::HasV5TEOps])
17043	Features.set(Feature_HasV5TEBit);
17044	if (FB[ARM::HasV6Ops])
17045	Features.set(Feature_HasV6Bit);
17046	if (FB[ARM::HasV6MOps])
17047	Features.set(Feature_HasV6MBit);
17048	if (FB[ARM::HasV8MBaselineOps])
17049	Features.set(Feature_HasV8MBaselineBit);
17050	if (FB[ARM::HasV8MMainlineOps])
17051	Features.set(Feature_HasV8MMainlineBit);
17052	if (FB[ARM::HasV8_1MMainlineOps])
17053	Features.set(Feature_HasV8_1MMainlineBit);
17054	if (FB[ARM::HasMVEIntegerOps])
17055	Features.set(Feature_HasMVEIntBit);
17056	if (FB[ARM::HasMVEFloatOps])
17057	Features.set(Feature_HasMVEFloatBit);
17058	if (FB[ARM::HasCDEOps])
17059	Features.set(Feature_HasCDEBit);
17060	if (FB[ARM::FeatureFPRegs])
17061	Features.set(Feature_HasFPRegsBit);
17062	if (FB[ARM::FeatureFPRegs16])
17063	Features.set(Feature_HasFPRegs16Bit);
17064	if (!FB[ARM::FeatureFPRegs16])
17065	Features.set(Feature_HasNoFPRegs16Bit);
17066	if (FB[ARM::FeatureFPRegs64])
17067	Features.set(Feature_HasFPRegs64Bit);
17068	if (FB[ARM::FeatureFPRegs] && FB[ARM::HasV8_1MMainlineOps])
17069	Features.set(Feature_HasFPRegsV8_1MBit);
17070	if (FB[ARM::HasV6T2Ops])
17071	Features.set(Feature_HasV6T2Bit);
17072	if (FB[ARM::HasV6KOps])
17073	Features.set(Feature_HasV6KBit);
17074	if (FB[ARM::HasV7Ops])
17075	Features.set(Feature_HasV7Bit);
17076	if (FB[ARM::HasV8Ops])
17077	Features.set(Feature_HasV8Bit);
17078	if (!FB[ARM::HasV8Ops])
17079	Features.set(Feature_PreV8Bit);
17080	if (FB[ARM::HasV8_1aOps])
17081	Features.set(Feature_HasV8_1aBit);
17082	if (FB[ARM::HasV8_2aOps])
17083	Features.set(Feature_HasV8_2aBit);
17084	if (FB[ARM::HasV8_3aOps])
17085	Features.set(Feature_HasV8_3aBit);
17086	if (FB[ARM::HasV8_4aOps])
17087	Features.set(Feature_HasV8_4aBit);
17088	if (FB[ARM::HasV8_5aOps])
17089	Features.set(Feature_HasV8_5aBit);
17090	if (FB[ARM::HasV8_6aOps])
17091	Features.set(Feature_HasV8_6aBit);
17092	if (FB[ARM::HasV8_7aOps])
17093	Features.set(Feature_HasV8_7aBit);
17094	if (FB[ARM::FeatureVFP2_SP])
17095	Features.set(Feature_HasVFP2Bit);
17096	if (FB[ARM::FeatureVFP3_D16_SP])
17097	Features.set(Feature_HasVFP3Bit);
17098	if (FB[ARM::FeatureVFP4_D16_SP])
17099	Features.set(Feature_HasVFP4Bit);
17100	if (FB[ARM::FeatureFP64])
17101	Features.set(Feature_HasDPVFPBit);
17102	if (FB[ARM::FeatureFPARMv8_D16_SP])
17103	Features.set(Feature_HasFPARMv8Bit);
17104	if (FB[ARM::FeatureNEON])
17105	Features.set(Feature_HasNEONBit);
17106	if (FB[ARM::FeatureSHA2])
17107	Features.set(Feature_HasSHA2Bit);
17108	if (FB[ARM::FeatureAES])
17109	Features.set(Feature_HasAESBit);
17110	if (FB[ARM::FeatureCrypto])
17111	Features.set(Feature_HasCryptoBit);
17112	if (FB[ARM::FeatureDotProd])
17113	Features.set(Feature_HasDotProdBit);
17114	if (FB[ARM::FeatureCRC])
17115	Features.set(Feature_HasCRCBit);
17116	if (FB[ARM::FeatureRAS])
17117	Features.set(Feature_HasRASBit);
17118	if (FB[ARM::FeatureLOB])
17119	Features.set(Feature_HasLOBBit);
17120	if (FB[ARM::FeatureFP16])
17121	Features.set(Feature_HasFP16Bit);
17122	if (FB[ARM::FeatureFullFP16])
17123	Features.set(Feature_HasFullFP16Bit);
17124	if (FB[ARM::FeatureFP16FML])
17125	Features.set(Feature_HasFP16FMLBit);
17126	if (FB[ARM::FeatureBF16])
17127	Features.set(Feature_HasBF16Bit);
17128	if (FB[ARM::FeatureMatMulInt8])
17129	Features.set(Feature_HasMatMulInt8Bit);
17130	if (FB[ARM::FeatureHWDivThumb])
17131	Features.set(Feature_HasDivideInThumbBit);
17132	if (FB[ARM::FeatureHWDivARM])
17133	Features.set(Feature_HasDivideInARMBit);
17134	if (FB[ARM::FeatureDSP])
17135	Features.set(Feature_HasDSPBit);
17136	if (FB[ARM::FeatureDB])
17137	Features.set(Feature_HasDBBit);
17138	if (FB[ARM::FeatureDFB])
17139	Features.set(Feature_HasDFBBit);
17140	if (FB[ARM::FeatureV7Clrex])
17141	Features.set(Feature_HasV7ClrexBit);
17142	if (FB[ARM::FeatureAcquireRelease])
17143	Features.set(Feature_HasAcquireReleaseBit);
17144	if (FB[ARM::FeatureMP])
17145	Features.set(Feature_HasMPBit);
17146	if (FB[ARM::FeatureVirtualization])
17147	Features.set(Feature_HasVirtualizationBit);
17148	if (FB[ARM::FeatureTrustZone])
17149	Features.set(Feature_HasTrustZoneBit);
17150	if (FB[ARM::Feature8MSecExt])
17151	Features.set(Feature_Has8MSecExtBit);
17152	if (FB[ARM::ModeThumb])
17153	Features.set(Feature_IsThumbBit);
17154	if (FB[ARM::ModeThumb] && FB[ARM::FeatureThumb2])
17155	Features.set(Feature_IsThumb2Bit);
17156	if (FB[ARM::FeatureMClass])
17157	Features.set(Feature_IsMClassBit);
17158	if (!FB[ARM::FeatureMClass])
17159	Features.set(Feature_IsNotMClassBit);
17160	if (!FB[ARM::ModeThumb])
17161	Features.set(Feature_IsARMBit);
17162	if (FB[ARM::FeatureNaClTrap])
17163	Features.set(Feature_UseNaClTrapBit);
17164	if (!FB[ARM::FeatureNoNegativeImmediates])
17165	Features.set(Feature_UseNegativeImmediatesBit);
17166	if (FB[ARM::FeatureSB])
17167	Features.set(Feature_HasSBBit);
17168	return Features;
17169	}
17170
17171	#ifndef NDEBUG
17172	// Feature bitsets.
17173	enum : uint8_t {
17174	CEFBS_None,
17175	CEFBS_Has8MSecExt,
17176	CEFBS_HasBF16,
17177	CEFBS_HasCDE,
17178	CEFBS_HasDotProd,
17179	CEFBS_HasFP16,
17180	CEFBS_HasFPARMv8,
17181	CEFBS_HasFPRegs,
17182	CEFBS_HasFPRegs16,
17183	CEFBS_HasFPRegs64,
17184	CEFBS_HasFPRegsV8_1M,
17185	CEFBS_HasFullFP16,
17186	CEFBS_HasMVEFloat,
17187	CEFBS_HasMVEInt,
17188	CEFBS_HasMatMulInt8,
17189	CEFBS_HasNEON,
17190	CEFBS_HasV8_1MMainline,
17191	CEFBS_HasVFP2,
17192	CEFBS_HasVFP3,
17193	CEFBS_HasVFP4,
17194	CEFBS_IsARM,
17195	CEFBS_IsThumb,
17196	CEFBS_IsThumb2,
17197	CEFBS_HasBF16_HasNEON,
17198	CEFBS_HasCDE_HasFPRegs,
17199	CEFBS_HasCDE_HasMVEInt,
17200	CEFBS_HasDSP_IsThumb2,
17201	CEFBS_HasFPARMv8_HasDPVFP,
17202	CEFBS_HasFPARMv8_HasV8_3a,
17203	CEFBS_HasFPRegs_HasV8_1MMainline,
17204	CEFBS_HasNEON_HasFP16,
17205	CEFBS_HasNEON_HasFP16FML,
17206	CEFBS_HasNEON_HasFullFP16,
17207	CEFBS_HasNEON_HasV8_1a,
17208	CEFBS_HasNEON_HasV8_3a,
17209	CEFBS_HasNEON_HasVFP4,
17210	CEFBS_HasV8_HasCrypto,
17211	CEFBS_HasV8_HasNEON,
17212	CEFBS_HasV8MMainline_Has8MSecExt,
17213	CEFBS_HasV8_1MMainline_Has8MSecExt,
17214	CEFBS_HasV8_1MMainline_HasFPRegs,
17215	CEFBS_HasV8_1MMainline_HasMVEInt,
17216	CEFBS_HasVFP2_HasDPVFP,
17217	CEFBS_HasVFP3_HasDPVFP,
17218	CEFBS_HasVFP4_HasDPVFP,
17219	CEFBS_IsARM_HasAcquireRelease,
17220	CEFBS_IsARM_HasDB,
17221	CEFBS_IsARM_HasDivideInARM,
17222	CEFBS_IsARM_HasSB,
17223	CEFBS_IsARM_HasTrustZone,
17224	CEFBS_IsARM_HasV4T,
17225	CEFBS_IsARM_HasV5T,
17226	CEFBS_IsARM_HasV5TE,
17227	CEFBS_IsARM_HasV6,
17228	CEFBS_IsARM_HasV6K,
17229	CEFBS_IsARM_HasV6T2,
17230	CEFBS_IsARM_HasV7,
17231	CEFBS_IsARM_HasV8,
17232	CEFBS_IsARM_HasV8_4a,
17233	CEFBS_IsARM_HasVFP2,
17234	CEFBS_IsARM_HasVirtualization,
17235	CEFBS_IsARM_PreV8,
17236	CEFBS_IsARM_UseNaClTrap,
17237	CEFBS_IsThumb_Has8MSecExt,
17238	CEFBS_IsThumb_HasAcquireRelease,
17239	CEFBS_IsThumb_HasDB,
17240	CEFBS_IsThumb_HasV5T,
17241	CEFBS_IsThumb_HasV6,
17242	CEFBS_IsThumb_HasV6M,
17243	CEFBS_IsThumb_HasV7Clrex,
17244	CEFBS_IsThumb_HasV8,
17245	CEFBS_IsThumb_HasV8MBaseline,
17246	CEFBS_IsThumb_HasV8_4a,
17247	CEFBS_IsThumb_HasVirtualization,
17248	CEFBS_IsThumb_IsMClass,
17249	CEFBS_IsThumb_IsNotMClass,
17250	CEFBS_IsThumb2_HasDSP,
17251	CEFBS_IsThumb2_HasSB,
17252	CEFBS_IsThumb2_HasTrustZone,
17253	CEFBS_IsThumb2_HasV7,
17254	CEFBS_IsThumb2_HasV8,
17255	CEFBS_IsThumb2_HasVFP2,
17256	CEFBS_IsThumb2_HasVirtualization,
17257	CEFBS_IsThumb2_IsNotMClass,
17258	CEFBS_IsThumb2_PreV8,
17259	CEFBS_PreV8_IsThumb2,
17260	CEFBS_HasDivideInThumb_IsThumb_HasV8MBaseline,
17261	CEFBS_HasNEON_HasV8_3a_HasFullFP16,
17262	CEFBS_HasV8_HasNEON_HasFullFP16,
17263	CEFBS_IsARM_HasAcquireRelease_HasV7Clrex,
17264	CEFBS_IsARM_HasV7_HasMP,
17265	CEFBS_IsARM_HasV8_HasCRC,
17266	CEFBS_IsARM_HasV8_HasV8_1a,
17267	CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex,
17268	CEFBS_IsThumb_HasV5T_IsNotMClass,
17269	CEFBS_IsThumb2_HasV7_HasMP,
17270	CEFBS_IsThumb2_HasV8_HasCRC,
17271	CEFBS_IsThumb2_HasV8_HasV8_1a,
17272	CEFBS_IsThumb2_HasV8_1MMainline_HasLOB,
17273	CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex_IsNotMClass,
17274	};
17275
17276	static constexpr FeatureBitset FeatureBitsets[] = {
17277	{}, // CEFBS_None
17278	{Feature_Has8MSecExtBit, },
17279	{Feature_HasBF16Bit, },
17280	{Feature_HasCDEBit, },
17281	{Feature_HasDotProdBit, },
17282	{Feature_HasFP16Bit, },
17283	{Feature_HasFPARMv8Bit, },
17284	{Feature_HasFPRegsBit, },
17285	{Feature_HasFPRegs16Bit, },
17286	{Feature_HasFPRegs64Bit, },
17287	{Feature_HasFPRegsV8_1MBit, },
17288	{Feature_HasFullFP16Bit, },
17289	{Feature_HasMVEFloatBit, },
17290	{Feature_HasMVEIntBit, },
17291	{Feature_HasMatMulInt8Bit, },
17292	{Feature_HasNEONBit, },
17293	{Feature_HasV8_1MMainlineBit, },
17294	{Feature_HasVFP2Bit, },
17295	{Feature_HasVFP3Bit, },
17296	{Feature_HasVFP4Bit, },
17297	{Feature_IsARMBit, },
17298	{Feature_IsThumbBit, },
17299	{Feature_IsThumb2Bit, },
17300	{Feature_HasBF16Bit, Feature_HasNEONBit, },
17301	{Feature_HasCDEBit, Feature_HasFPRegsBit, },
17302	{Feature_HasCDEBit, Feature_HasMVEIntBit, },
17303	{Feature_HasDSPBit, Feature_IsThumb2Bit, },
17304	{Feature_HasFPARMv8Bit, Feature_HasDPVFPBit, },
17305	{Feature_HasFPARMv8Bit, Feature_HasV8_3aBit, },
17306	{Feature_HasFPRegsBit, Feature_HasV8_1MMainlineBit, },
17307	{Feature_HasNEONBit, Feature_HasFP16Bit, },
17308	{Feature_HasNEONBit, Feature_HasFP16FMLBit, },
17309	{Feature_HasNEONBit, Feature_HasFullFP16Bit, },
17310	{Feature_HasNEONBit, Feature_HasV8_1aBit, },
17311	{Feature_HasNEONBit, Feature_HasV8_3aBit, },
17312	{Feature_HasNEONBit, Feature_HasVFP4Bit, },
17313	{Feature_HasV8Bit, Feature_HasCryptoBit, },
17314	{Feature_HasV8Bit, Feature_HasNEONBit, },
17315	{Feature_HasV8MMainlineBit, Feature_Has8MSecExtBit, },
17316	{Feature_HasV8_1MMainlineBit, Feature_Has8MSecExtBit, },
17317	{Feature_HasV8_1MMainlineBit, Feature_HasFPRegsBit, },
17318	{Feature_HasV8_1MMainlineBit, Feature_HasMVEIntBit, },
17319	{Feature_HasVFP2Bit, Feature_HasDPVFPBit, },
17320	{Feature_HasVFP3Bit, Feature_HasDPVFPBit, },
17321	{Feature_HasVFP4Bit, Feature_HasDPVFPBit, },
17322	{Feature_IsARMBit, Feature_HasAcquireReleaseBit, },
17323	{Feature_IsARMBit, Feature_HasDBBit, },
17324	{Feature_IsARMBit, Feature_HasDivideInARMBit, },
17325	{Feature_IsARMBit, Feature_HasSBBit, },
17326	{Feature_IsARMBit, Feature_HasTrustZoneBit, },
17327	{Feature_IsARMBit, Feature_HasV4TBit, },
17328	{Feature_IsARMBit, Feature_HasV5TBit, },
17329	{Feature_IsARMBit, Feature_HasV5TEBit, },
17330	{Feature_IsARMBit, Feature_HasV6Bit, },
17331	{Feature_IsARMBit, Feature_HasV6KBit, },
17332	{Feature_IsARMBit, Feature_HasV6T2Bit, },
17333	{Feature_IsARMBit, Feature_HasV7Bit, },
17334	{Feature_IsARMBit, Feature_HasV8Bit, },
17335	{Feature_IsARMBit, Feature_HasV8_4aBit, },
17336	{Feature_IsARMBit, Feature_HasVFP2Bit, },
17337	{Feature_IsARMBit, Feature_HasVirtualizationBit, },
17338	{Feature_IsARMBit, Feature_PreV8Bit, },
17339	{Feature_IsARMBit, Feature_UseNaClTrapBit, },
17340	{Feature_IsThumbBit, Feature_Has8MSecExtBit, },
17341	{Feature_IsThumbBit, Feature_HasAcquireReleaseBit, },
17342	{Feature_IsThumbBit, Feature_HasDBBit, },
17343	{Feature_IsThumbBit, Feature_HasV5TBit, },
17344	{Feature_IsThumbBit, Feature_HasV6Bit, },
17345	{Feature_IsThumbBit, Feature_HasV6MBit, },
17346	{Feature_IsThumbBit, Feature_HasV7ClrexBit, },
17347	{Feature_IsThumbBit, Feature_HasV8Bit, },
17348	{Feature_IsThumbBit, Feature_HasV8MBaselineBit, },
17349	{Feature_IsThumbBit, Feature_HasV8_4aBit, },
17350	{Feature_IsThumbBit, Feature_HasVirtualizationBit, },
17351	{Feature_IsThumbBit, Feature_IsMClassBit, },
17352	{Feature_IsThumbBit, Feature_IsNotMClassBit, },
17353	{Feature_IsThumb2Bit, Feature_HasDSPBit, },
17354	{Feature_IsThumb2Bit, Feature_HasSBBit, },
17355	{Feature_IsThumb2Bit, Feature_HasTrustZoneBit, },
17356	{Feature_IsThumb2Bit, Feature_HasV7Bit, },
17357	{Feature_IsThumb2Bit, Feature_HasV8Bit, },
17358	{Feature_IsThumb2Bit, Feature_HasVFP2Bit, },
17359	{Feature_IsThumb2Bit, Feature_HasVirtualizationBit, },
17360	{Feature_IsThumb2Bit, Feature_IsNotMClassBit, },
17361	{Feature_IsThumb2Bit, Feature_PreV8Bit, },
17362	{Feature_PreV8Bit, Feature_IsThumb2Bit, },
17363	{Feature_HasDivideInThumbBit, Feature_IsThumbBit, Feature_HasV8MBaselineBit, },
17364	{Feature_HasNEONBit, Feature_HasV8_3aBit, Feature_HasFullFP16Bit, },
17365	{Feature_HasV8Bit, Feature_HasNEONBit, Feature_HasFullFP16Bit, },
17366	{Feature_IsARMBit, Feature_HasAcquireReleaseBit, Feature_HasV7ClrexBit, },
17367	{Feature_IsARMBit, Feature_HasV7Bit, Feature_HasMPBit, },
17368	{Feature_IsARMBit, Feature_HasV8Bit, Feature_HasCRCBit, },
17369	{Feature_IsARMBit, Feature_HasV8Bit, Feature_HasV8_1aBit, },
17370	{Feature_IsThumbBit, Feature_HasAcquireReleaseBit, Feature_HasV7ClrexBit, },
17371	{Feature_IsThumbBit, Feature_HasV5TBit, Feature_IsNotMClassBit, },
17372	{Feature_IsThumb2Bit, Feature_HasV7Bit, Feature_HasMPBit, },
17373	{Feature_IsThumb2Bit, Feature_HasV8Bit, Feature_HasCRCBit, },
17374	{Feature_IsThumb2Bit, Feature_HasV8Bit, Feature_HasV8_1aBit, },
17375	{Feature_IsThumb2Bit, Feature_HasV8_1MMainlineBit, Feature_HasLOBBit, },
17376	{Feature_IsThumbBit, Feature_HasAcquireReleaseBit, Feature_HasV7ClrexBit, Feature_IsNotMClassBit, },
17377	};
17378	#endif // NDEBUG
17379
17380	void ARMMCCodeEmitter::verifyInstructionPredicates(
17381	const MCInst &Inst, const FeatureBitset &AvailableFeatures) const {
17382	#ifndef NDEBUG
17383	static uint8_t RequiredFeaturesRefs[] = {
17384	CEFBS_None, // PHI = 0
17385	CEFBS_None, // INLINEASM = 1
17386	CEFBS_None, // INLINEASM_BR = 2
17387	CEFBS_None, // CFI_INSTRUCTION = 3
17388	CEFBS_None, // EH_LABEL = 4
17389	CEFBS_None, // GC_LABEL = 5
17390	CEFBS_None, // ANNOTATION_LABEL = 6
17391	CEFBS_None, // KILL = 7
17392	CEFBS_None, // EXTRACT_SUBREG = 8
17393	CEFBS_None, // INSERT_SUBREG = 9
17394	CEFBS_None, // IMPLICIT_DEF = 10
17395	CEFBS_None, // SUBREG_TO_REG = 11
17396	CEFBS_None, // COPY_TO_REGCLASS = 12
17397	CEFBS_None, // DBG_VALUE = 13
17398	CEFBS_None, // DBG_INSTR_REF = 14
17399	CEFBS_None, // DBG_LABEL = 15
17400	CEFBS_None, // REG_SEQUENCE = 16
17401	CEFBS_None, // COPY = 17
17402	CEFBS_None, // BUNDLE = 18
17403	CEFBS_None, // LIFETIME_START = 19
17404	CEFBS_None, // LIFETIME_END = 20
17405	CEFBS_None, // PSEUDO_PROBE = 21
17406	CEFBS_None, // STACKMAP = 22
17407	CEFBS_None, // FENTRY_CALL = 23
17408	CEFBS_None, // PATCHPOINT = 24
17409	CEFBS_None, // LOAD_STACK_GUARD = 25
17410	CEFBS_None, // PREALLOCATED_SETUP = 26
17411	CEFBS_None, // PREALLOCATED_ARG = 27
17412	CEFBS_None, // STATEPOINT = 28
17413	CEFBS_None, // LOCAL_ESCAPE = 29
17414	CEFBS_None, // FAULTING_OP = 30
17415	CEFBS_None, // PATCHABLE_OP = 31
17416	CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 32
17417	CEFBS_None, // PATCHABLE_RET = 33
17418	CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 34
17419	CEFBS_None, // PATCHABLE_TAIL_CALL = 35
17420	CEFBS_None, // PATCHABLE_EVENT_CALL = 36
17421	CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 37
17422	CEFBS_None, // ICALL_BRANCH_FUNNEL = 38
17423	CEFBS_None, // G_ADD = 39
17424	CEFBS_None, // G_SUB = 40
17425	CEFBS_None, // G_MUL = 41
17426	CEFBS_None, // G_SDIV = 42
17427	CEFBS_None, // G_UDIV = 43
17428	CEFBS_None, // G_SREM = 44
17429	CEFBS_None, // G_UREM = 45
17430	CEFBS_None, // G_AND = 46
17431	CEFBS_None, // G_OR = 47
17432	CEFBS_None, // G_XOR = 48
17433	CEFBS_None, // G_IMPLICIT_DEF = 49
17434	CEFBS_None, // G_PHI = 50
17435	CEFBS_None, // G_FRAME_INDEX = 51
17436	CEFBS_None, // G_GLOBAL_VALUE = 52
17437	CEFBS_None, // G_EXTRACT = 53
17438	CEFBS_None, // G_UNMERGE_VALUES = 54
17439	CEFBS_None, // G_INSERT = 55
17440	CEFBS_None, // G_MERGE_VALUES = 56
17441	CEFBS_None, // G_BUILD_VECTOR = 57
17442	CEFBS_None, // G_BUILD_VECTOR_TRUNC = 58
17443	CEFBS_None, // G_CONCAT_VECTORS = 59
17444	CEFBS_None, // G_PTRTOINT = 60
17445	CEFBS_None, // G_INTTOPTR = 61
17446	CEFBS_None, // G_BITCAST = 62
17447	CEFBS_None, // G_FREEZE = 63
17448	CEFBS_None, // G_INTRINSIC_TRUNC = 64
17449	CEFBS_None, // G_INTRINSIC_ROUND = 65
17450	CEFBS_None, // G_INTRINSIC_LRINT = 66
17451	CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 67
17452	CEFBS_None, // G_READCYCLECOUNTER = 68
17453	CEFBS_None, // G_LOAD = 69
17454	CEFBS_None, // G_SEXTLOAD = 70
17455	CEFBS_None, // G_ZEXTLOAD = 71
17456	CEFBS_None, // G_INDEXED_LOAD = 72
17457	CEFBS_None, // G_INDEXED_SEXTLOAD = 73
17458	CEFBS_None, // G_INDEXED_ZEXTLOAD = 74
17459	CEFBS_None, // G_STORE = 75
17460	CEFBS_None, // G_INDEXED_STORE = 76
17461	CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 77
17462	CEFBS_None, // G_ATOMIC_CMPXCHG = 78
17463	CEFBS_None, // G_ATOMICRMW_XCHG = 79
17464	CEFBS_None, // G_ATOMICRMW_ADD = 80
17465	CEFBS_None, // G_ATOMICRMW_SUB = 81
17466	CEFBS_None, // G_ATOMICRMW_AND = 82
17467	CEFBS_None, // G_ATOMICRMW_NAND = 83
17468	CEFBS_None, // G_ATOMICRMW_OR = 84
17469	CEFBS_None, // G_ATOMICRMW_XOR = 85
17470	CEFBS_None, // G_ATOMICRMW_MAX = 86
17471	CEFBS_None, // G_ATOMICRMW_MIN = 87
17472	CEFBS_None, // G_ATOMICRMW_UMAX = 88
17473	CEFBS_None, // G_ATOMICRMW_UMIN = 89
17474	CEFBS_None, // G_ATOMICRMW_FADD = 90
17475	CEFBS_None, // G_ATOMICRMW_FSUB = 91
17476	CEFBS_None, // G_FENCE = 92
17477	CEFBS_None, // G_BRCOND = 93
17478	CEFBS_None, // G_BRINDIRECT = 94
17479	CEFBS_None, // G_INTRINSIC = 95
17480	CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 96
17481	CEFBS_None, // G_ANYEXT = 97
17482	CEFBS_None, // G_TRUNC = 98
17483	CEFBS_None, // G_CONSTANT = 99
17484	CEFBS_None, // G_FCONSTANT = 100
17485	CEFBS_None, // G_VASTART = 101
17486	CEFBS_None, // G_VAARG = 102
17487	CEFBS_None, // G_SEXT = 103
17488	CEFBS_None, // G_SEXT_INREG = 104
17489	CEFBS_None, // G_ZEXT = 105
17490	CEFBS_None, // G_SHL = 106
17491	CEFBS_None, // G_LSHR = 107
17492	CEFBS_None, // G_ASHR = 108
17493	CEFBS_None, // G_FSHL = 109
17494	CEFBS_None, // G_FSHR = 110
17495	CEFBS_None, // G_ICMP = 111
17496	CEFBS_None, // G_FCMP = 112
17497	CEFBS_None, // G_SELECT = 113
17498	CEFBS_None, // G_UADDO = 114
17499	CEFBS_None, // G_UADDE = 115
17500	CEFBS_None, // G_USUBO = 116
17501	CEFBS_None, // G_USUBE = 117
17502	CEFBS_None, // G_SADDO = 118
17503	CEFBS_None, // G_SADDE = 119
17504	CEFBS_None, // G_SSUBO = 120
17505	CEFBS_None, // G_SSUBE = 121
17506	CEFBS_None, // G_UMULO = 122
17507	CEFBS_None, // G_SMULO = 123
17508	CEFBS_None, // G_UMULH = 124
17509	CEFBS_None, // G_SMULH = 125
17510	CEFBS_None, // G_UADDSAT = 126
17511	CEFBS_None, // G_SADDSAT = 127
17512	CEFBS_None, // G_USUBSAT = 128
17513	CEFBS_None, // G_SSUBSAT = 129
17514	CEFBS_None, // G_USHLSAT = 130
17515	CEFBS_None, // G_SSHLSAT = 131
17516	CEFBS_None, // G_SMULFIX = 132
17517	CEFBS_None, // G_UMULFIX = 133
17518	CEFBS_None, // G_SMULFIXSAT = 134
17519	CEFBS_None, // G_UMULFIXSAT = 135
17520	CEFBS_None, // G_SDIVFIX = 136
17521	CEFBS_None, // G_UDIVFIX = 137
17522	CEFBS_None, // G_SDIVFIXSAT = 138
17523	CEFBS_None, // G_UDIVFIXSAT = 139
17524	CEFBS_None, // G_FADD = 140
17525	CEFBS_None, // G_FSUB = 141
17526	CEFBS_None, // G_FMUL = 142
17527	CEFBS_None, // G_FMA = 143
17528	CEFBS_None, // G_FMAD = 144
17529	CEFBS_None, // G_FDIV = 145
17530	CEFBS_None, // G_FREM = 146
17531	CEFBS_None, // G_FPOW = 147
17532	CEFBS_None, // G_FPOWI = 148
17533	CEFBS_None, // G_FEXP = 149
17534	CEFBS_None, // G_FEXP2 = 150
17535	CEFBS_None, // G_FLOG = 151
17536	CEFBS_None, // G_FLOG2 = 152
17537	CEFBS_None, // G_FLOG10 = 153
17538	CEFBS_None, // G_FNEG = 154
17539	CEFBS_None, // G_FPEXT = 155
17540	CEFBS_None, // G_FPTRUNC = 156
17541	CEFBS_None, // G_FPTOSI = 157
17542	CEFBS_None, // G_FPTOUI = 158
17543	CEFBS_None, // G_SITOFP = 159
17544	CEFBS_None, // G_UITOFP = 160
17545	CEFBS_None, // G_FABS = 161
17546	CEFBS_None, // G_FCOPYSIGN = 162
17547	CEFBS_None, // G_FCANONICALIZE = 163
17548	CEFBS_None, // G_FMINNUM = 164
17549	CEFBS_None, // G_FMAXNUM = 165
17550	CEFBS_None, // G_FMINNUM_IEEE = 166
17551	CEFBS_None, // G_FMAXNUM_IEEE = 167
17552	CEFBS_None, // G_FMINIMUM = 168
17553	CEFBS_None, // G_FMAXIMUM = 169
17554	CEFBS_None, // G_PTR_ADD = 170
17555	CEFBS_None, // G_PTRMASK = 171
17556	CEFBS_None, // G_SMIN = 172
17557	CEFBS_None, // G_SMAX = 173
17558	CEFBS_None, // G_UMIN = 174
17559	CEFBS_None, // G_UMAX = 175
17560	CEFBS_None, // G_ABS = 176
17561	CEFBS_None, // G_BR = 177
17562	CEFBS_None, // G_BRJT = 178
17563	CEFBS_None, // G_INSERT_VECTOR_ELT = 179
17564	CEFBS_None, // G_EXTRACT_VECTOR_ELT = 180
17565	CEFBS_None, // G_SHUFFLE_VECTOR = 181
17566	CEFBS_None, // G_CTTZ = 182
17567	CEFBS_None, // G_CTTZ_ZERO_UNDEF = 183
17568	CEFBS_None, // G_CTLZ = 184
17569	CEFBS_None, // G_CTLZ_ZERO_UNDEF = 185
17570	CEFBS_None, // G_CTPOP = 186
17571	CEFBS_None, // G_BSWAP = 187
17572	CEFBS_None, // G_BITREVERSE = 188
17573	CEFBS_None, // G_FCEIL = 189
17574	CEFBS_None, // G_FCOS = 190
17575	CEFBS_None, // G_FSIN = 191
17576	CEFBS_None, // G_FSQRT = 192
17577	CEFBS_None, // G_FFLOOR = 193
17578	CEFBS_None, // G_FRINT = 194
17579	CEFBS_None, // G_FNEARBYINT = 195
17580	CEFBS_None, // G_ADDRSPACE_CAST = 196
17581	CEFBS_None, // G_BLOCK_ADDR = 197
17582	CEFBS_None, // G_JUMP_TABLE = 198
17583	CEFBS_None, // G_DYN_STACKALLOC = 199
17584	CEFBS_None, // G_STRICT_FADD = 200
17585	CEFBS_None, // G_STRICT_FSUB = 201
17586	CEFBS_None, // G_STRICT_FMUL = 202
17587	CEFBS_None, // G_STRICT_FDIV = 203
17588	CEFBS_None, // G_STRICT_FREM = 204
17589	CEFBS_None, // G_STRICT_FMA = 205
17590	CEFBS_None, // G_STRICT_FSQRT = 206
17591	CEFBS_None, // G_READ_REGISTER = 207
17592	CEFBS_None, // G_WRITE_REGISTER = 208
17593	CEFBS_None, // G_MEMCPY = 209
17594	CEFBS_None, // G_MEMMOVE = 210
17595	CEFBS_None, // G_MEMSET = 211
17596	CEFBS_None, // G_VECREDUCE_SEQ_FADD = 212
17597	CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 213
17598	CEFBS_None, // G_VECREDUCE_FADD = 214
17599	CEFBS_None, // G_VECREDUCE_FMUL = 215
17600	CEFBS_None, // G_VECREDUCE_FMAX = 216
17601	CEFBS_None, // G_VECREDUCE_FMIN = 217
17602	CEFBS_None, // G_VECREDUCE_ADD = 218
17603	CEFBS_None, // G_VECREDUCE_MUL = 219
17604	CEFBS_None, // G_VECREDUCE_AND = 220
17605	CEFBS_None, // G_VECREDUCE_OR = 221
17606	CEFBS_None, // G_VECREDUCE_XOR = 222
17607	CEFBS_None, // G_VECREDUCE_SMAX = 223
17608	CEFBS_None, // G_VECREDUCE_SMIN = 224
17609	CEFBS_None, // G_VECREDUCE_UMAX = 225
17610	CEFBS_None, // G_VECREDUCE_UMIN = 226
17611	CEFBS_IsARM, // ABS = 227
17612	CEFBS_IsARM, // ADDSri = 228
17613	CEFBS_IsARM, // ADDSrr = 229
17614	CEFBS_IsARM, // ADDSrsi = 230
17615	CEFBS_IsARM, // ADDSrsr = 231
17616	CEFBS_None, // ADJCALLSTACKDOWN = 232
17617	CEFBS_None, // ADJCALLSTACKUP = 233
17618	CEFBS_IsARM, // ASRi = 234
17619	CEFBS_IsARM, // ASRr = 235
17620	CEFBS_IsARM, // B = 236
17621	CEFBS_None, // BCCZi64 = 237
17622	CEFBS_None, // BCCi64 = 238
17623	CEFBS_IsARM_HasV5T, // BLX_noip = 239
17624	CEFBS_IsARM_HasV5T, // BLX_pred_noip = 240
17625	CEFBS_IsARM, // BL_PUSHLR = 241
17626	CEFBS_IsARM, // BMOVPCB_CALL = 242
17627	CEFBS_IsARM, // BMOVPCRX_CALL = 243
17628	CEFBS_IsARM, // BR_JTadd = 244
17629	CEFBS_IsARM, // BR_JTm_i12 = 245
17630	CEFBS_IsARM, // BR_JTm_rs = 246
17631	CEFBS_IsARM, // BR_JTr = 247
17632	CEFBS_IsARM_HasV4T, // BX_CALL = 248
17633	CEFBS_None, // CMP_SWAP_16 = 249
17634	CEFBS_None, // CMP_SWAP_32 = 250
17635	CEFBS_None, // CMP_SWAP_64 = 251
17636	CEFBS_None, // CMP_SWAP_8 = 252
17637	CEFBS_None, // CONSTPOOL_ENTRY = 253
17638	CEFBS_None, // COPY_STRUCT_BYVAL_I32 = 254
17639	CEFBS_None, // CompilerBarrier = 255
17640	CEFBS_IsARM, // ITasm = 256
17641	CEFBS_None, // Int_eh_sjlj_dispatchsetup = 257
17642	CEFBS_IsARM, // Int_eh_sjlj_longjmp = 258
17643	CEFBS_IsARM_HasVFP2, // Int_eh_sjlj_setjmp = 259
17644	CEFBS_IsARM, // Int_eh_sjlj_setjmp_nofp = 260
17645	CEFBS_None, // Int_eh_sjlj_setup_dispatch = 261
17646	CEFBS_None, // JUMPTABLE_ADDRS = 262
17647	CEFBS_None, // JUMPTABLE_INSTS = 263
17648	CEFBS_None, // JUMPTABLE_TBB = 264
17649	CEFBS_None, // JUMPTABLE_TBH = 265
17650	CEFBS_IsARM, // LDMIA_RET = 266
17651	CEFBS_IsARM, // LDRBT_POST = 267
17652	CEFBS_IsARM, // LDRConstPool = 268
17653	CEFBS_IsARM, // LDRHTii = 269
17654	CEFBS_IsARM, // LDRLIT_ga_abs = 270
17655	CEFBS_IsARM, // LDRLIT_ga_pcrel = 271
17656	CEFBS_IsARM, // LDRLIT_ga_pcrel_ldr = 272
17657	CEFBS_IsARM, // LDRSBTii = 273
17658	CEFBS_IsARM, // LDRSHTii = 274
17659	CEFBS_IsARM, // LDRT_POST = 275
17660	CEFBS_IsARM, // LEApcrel = 276
17661	CEFBS_IsARM, // LEApcrelJT = 277
17662	CEFBS_IsARM_HasV5TE, // LOADDUAL = 278
17663	CEFBS_IsARM, // LSLi = 279
17664	CEFBS_IsARM, // LSLr = 280
17665	CEFBS_IsARM, // LSRi = 281
17666	CEFBS_IsARM, // LSRr = 282
17667	CEFBS_None, // MEMCPY = 283
17668	CEFBS_IsARM, // MLAv5 = 284
17669	CEFBS_IsARM, // MOVCCi = 285
17670	CEFBS_IsARM_HasV6T2, // MOVCCi16 = 286
17671	CEFBS_IsARM_HasV6T2, // MOVCCi32imm = 287
17672	CEFBS_IsARM, // MOVCCr = 288
17673	CEFBS_IsARM, // MOVCCsi = 289
17674	CEFBS_IsARM, // MOVCCsr = 290
17675	CEFBS_IsARM, // MOVPCRX = 291
17676	CEFBS_None, // MOVTi16_ga_pcrel = 292
17677	CEFBS_IsARM, // MOV_ga_pcrel = 293
17678	CEFBS_IsARM, // MOV_ga_pcrel_ldr = 294
17679	CEFBS_None, // MOVi16_ga_pcrel = 295
17680	CEFBS_IsARM, // MOVi32imm = 296
17681	CEFBS_IsARM, // MOVsra_flag = 297
17682	CEFBS_IsARM, // MOVsrl_flag = 298
17683	CEFBS_IsARM, // MULv5 = 299
17684	CEFBS_IsARM, // MVNCCi = 300
17685	CEFBS_IsARM, // PICADD = 301
17686	CEFBS_IsARM, // PICLDR = 302
17687	CEFBS_IsARM, // PICLDRB = 303
17688	CEFBS_IsARM, // PICLDRH = 304
17689	CEFBS_IsARM, // PICLDRSB = 305
17690	CEFBS_IsARM, // PICLDRSH = 306
17691	CEFBS_IsARM, // PICSTR = 307
17692	CEFBS_IsARM, // PICSTRB = 308
17693	CEFBS_IsARM, // PICSTRH = 309
17694	CEFBS_IsARM, // RORi = 310
17695	CEFBS_IsARM, // RORr = 311
17696	CEFBS_IsARM, // RRX = 312
17697	CEFBS_IsARM, // RRXi = 313
17698	CEFBS_IsARM, // RSBSri = 314
17699	CEFBS_IsARM, // RSBSrsi = 315
17700	CEFBS_IsARM, // RSBSrsr = 316
17701	CEFBS_IsARM, // SMLALv5 = 317
17702	CEFBS_IsARM, // SMULLv5 = 318
17703	CEFBS_None, // SPACE = 319
17704	CEFBS_IsARM_HasV5TE, // STOREDUAL = 320
17705	CEFBS_IsARM, // STRBT_POST = 321
17706	CEFBS_IsARM, // STRBi_preidx = 322
17707	CEFBS_IsARM, // STRBr_preidx = 323
17708	CEFBS_IsARM, // STRH_preidx = 324
17709	CEFBS_IsARM, // STRT_POST = 325
17710	CEFBS_IsARM, // STRi_preidx = 326
17711	CEFBS_IsARM, // STRr_preidx = 327
17712	CEFBS_IsARM, // SUBS_PC_LR = 328
17713	CEFBS_IsARM, // SUBSri = 329
17714	CEFBS_IsARM, // SUBSrr = 330
17715	CEFBS_IsARM, // SUBSrsi = 331
17716	CEFBS_IsARM, // SUBSrsr = 332
17717	CEFBS_None, // SpeculationBarrierISBDSBEndBB = 333
17718	CEFBS_None, // SpeculationBarrierSBEndBB = 334
17719	CEFBS_IsARM, // TAILJMPd = 335
17720	CEFBS_IsARM_HasV4T, // TAILJMPr = 336
17721	CEFBS_IsARM, // TAILJMPr4 = 337
17722	CEFBS_None, // TCRETURNdi = 338
17723	CEFBS_None, // TCRETURNri = 339
17724	CEFBS_IsARM, // TPsoft = 340
17725	CEFBS_IsARM, // UMLALv5 = 341
17726	CEFBS_IsARM, // UMULLv5 = 342
17727	CEFBS_HasNEON, // VLD1LNdAsm_16 = 343
17728	CEFBS_HasNEON, // VLD1LNdAsm_32 = 344
17729	CEFBS_HasNEON, // VLD1LNdAsm_8 = 345
17730	CEFBS_HasNEON, // VLD1LNdWB_fixed_Asm_16 = 346
17731	CEFBS_HasNEON, // VLD1LNdWB_fixed_Asm_32 = 347
17732	CEFBS_HasNEON, // VLD1LNdWB_fixed_Asm_8 = 348
17733	CEFBS_HasNEON, // VLD1LNdWB_register_Asm_16 = 349
17734	CEFBS_HasNEON, // VLD1LNdWB_register_Asm_32 = 350
17735	CEFBS_HasNEON, // VLD1LNdWB_register_Asm_8 = 351
17736	CEFBS_HasNEON, // VLD2LNdAsm_16 = 352
17737	CEFBS_HasNEON, // VLD2LNdAsm_32 = 353
17738	CEFBS_HasNEON, // VLD2LNdAsm_8 = 354
17739	CEFBS_HasNEON, // VLD2LNdWB_fixed_Asm_16 = 355
17740	CEFBS_HasNEON, // VLD2LNdWB_fixed_Asm_32 = 356
17741	CEFBS_HasNEON, // VLD2LNdWB_fixed_Asm_8 = 357
17742	CEFBS_HasNEON, // VLD2LNdWB_register_Asm_16 = 358
17743	CEFBS_HasNEON, // VLD2LNdWB_register_Asm_32 = 359
17744	CEFBS_HasNEON, // VLD2LNdWB_register_Asm_8 = 360
17745	CEFBS_HasNEON, // VLD2LNqAsm_16 = 361
17746	CEFBS_HasNEON, // VLD2LNqAsm_32 = 362
17747	CEFBS_HasNEON, // VLD2LNqWB_fixed_Asm_16 = 363
17748	CEFBS_HasNEON, // VLD2LNqWB_fixed_Asm_32 = 364
17749	CEFBS_HasNEON, // VLD2LNqWB_register_Asm_16 = 365
17750	CEFBS_HasNEON, // VLD2LNqWB_register_Asm_32 = 366
17751	CEFBS_HasNEON, // VLD3DUPdAsm_16 = 367
17752	CEFBS_HasNEON, // VLD3DUPdAsm_32 = 368
17753	CEFBS_HasNEON, // VLD3DUPdAsm_8 = 369
17754	CEFBS_HasNEON, // VLD3DUPdWB_fixed_Asm_16 = 370
17755	CEFBS_HasNEON, // VLD3DUPdWB_fixed_Asm_32 = 371
17756	CEFBS_HasNEON, // VLD3DUPdWB_fixed_Asm_8 = 372
17757	CEFBS_HasNEON, // VLD3DUPdWB_register_Asm_16 = 373
17758	CEFBS_HasNEON, // VLD3DUPdWB_register_Asm_32 = 374
17759	CEFBS_HasNEON, // VLD3DUPdWB_register_Asm_8 = 375
17760	CEFBS_HasNEON, // VLD3DUPqAsm_16 = 376
17761	CEFBS_HasNEON, // VLD3DUPqAsm_32 = 377
17762	CEFBS_HasNEON, // VLD3DUPqAsm_8 = 378
17763	CEFBS_HasNEON, // VLD3DUPqWB_fixed_Asm_16 = 379
17764	CEFBS_HasNEON, // VLD3DUPqWB_fixed_Asm_32 = 380
17765	CEFBS_HasNEON, // VLD3DUPqWB_fixed_Asm_8 = 381
17766	CEFBS_HasNEON, // VLD3DUPqWB_register_Asm_16 = 382
17767	CEFBS_HasNEON, // VLD3DUPqWB_register_Asm_32 = 383
17768	CEFBS_HasNEON, // VLD3DUPqWB_register_Asm_8 = 384
17769	CEFBS_HasNEON, // VLD3LNdAsm_16 = 385
17770	CEFBS_HasNEON, // VLD3LNdAsm_32 = 386
17771	CEFBS_HasNEON, // VLD3LNdAsm_8 = 387
17772	CEFBS_HasNEON, // VLD3LNdWB_fixed_Asm_16 = 388
17773	CEFBS_HasNEON, // VLD3LNdWB_fixed_Asm_32 = 389
17774	CEFBS_HasNEON, // VLD3LNdWB_fixed_Asm_8 = 390
17775	CEFBS_HasNEON, // VLD3LNdWB_register_Asm_16 = 391
17776	CEFBS_HasNEON, // VLD3LNdWB_register_Asm_32 = 392
17777	CEFBS_HasNEON, // VLD3LNdWB_register_Asm_8 = 393
17778	CEFBS_HasNEON, // VLD3LNqAsm_16 = 394
17779	CEFBS_HasNEON, // VLD3LNqAsm_32 = 395
17780	CEFBS_HasNEON, // VLD3LNqWB_fixed_Asm_16 = 396
17781	CEFBS_HasNEON, // VLD3LNqWB_fixed_Asm_32 = 397
17782	CEFBS_HasNEON, // VLD3LNqWB_register_Asm_16 = 398
17783	CEFBS_HasNEON, // VLD3LNqWB_register_Asm_32 = 399
17784	CEFBS_HasNEON, // VLD3dAsm_16 = 400
17785	CEFBS_HasNEON, // VLD3dAsm_32 = 401
17786	CEFBS_HasNEON, // VLD3dAsm_8 = 402
17787	CEFBS_HasNEON, // VLD3dWB_fixed_Asm_16 = 403
17788	CEFBS_HasNEON, // VLD3dWB_fixed_Asm_32 = 404
17789	CEFBS_HasNEON, // VLD3dWB_fixed_Asm_8 = 405
17790	CEFBS_HasNEON, // VLD3dWB_register_Asm_16 = 406
17791	CEFBS_HasNEON, // VLD3dWB_register_Asm_32 = 407
17792	CEFBS_HasNEON, // VLD3dWB_register_Asm_8 = 408
17793	CEFBS_HasNEON, // VLD3qAsm_16 = 409
17794	CEFBS_HasNEON, // VLD3qAsm_32 = 410
17795	CEFBS_HasNEON, // VLD3qAsm_8 = 411
17796	CEFBS_HasNEON, // VLD3qWB_fixed_Asm_16 = 412
17797	CEFBS_HasNEON, // VLD3qWB_fixed_Asm_32 = 413
17798	CEFBS_HasNEON, // VLD3qWB_fixed_Asm_8 = 414
17799	CEFBS_HasNEON, // VLD3qWB_register_Asm_16 = 415
17800	CEFBS_HasNEON, // VLD3qWB_register_Asm_32 = 416
17801	CEFBS_HasNEON, // VLD3qWB_register_Asm_8 = 417
17802	CEFBS_HasNEON, // VLD4DUPdAsm_16 = 418
17803	CEFBS_HasNEON, // VLD4DUPdAsm_32 = 419
17804	CEFBS_HasNEON, // VLD4DUPdAsm_8 = 420
17805	CEFBS_HasNEON, // VLD4DUPdWB_fixed_Asm_16 = 421
17806	CEFBS_HasNEON, // VLD4DUPdWB_fixed_Asm_32 = 422
17807	CEFBS_HasNEON, // VLD4DUPdWB_fixed_Asm_8 = 423
17808	CEFBS_HasNEON, // VLD4DUPdWB_register_Asm_16 = 424
17809	CEFBS_HasNEON, // VLD4DUPdWB_register_Asm_32 = 425
17810	CEFBS_HasNEON, // VLD4DUPdWB_register_Asm_8 = 426
17811	CEFBS_HasNEON, // VLD4DUPqAsm_16 = 427
17812	CEFBS_HasNEON, // VLD4DUPqAsm_32 = 428
17813	CEFBS_HasNEON, // VLD4DUPqAsm_8 = 429
17814	CEFBS_HasNEON, // VLD4DUPqWB_fixed_Asm_16 = 430
17815	CEFBS_HasNEON, // VLD4DUPqWB_fixed_Asm_32 = 431
17816	CEFBS_HasNEON, // VLD4DUPqWB_fixed_Asm_8 = 432
17817	CEFBS_HasNEON, // VLD4DUPqWB_register_Asm_16 = 433
17818	CEFBS_HasNEON, // VLD4DUPqWB_register_Asm_32 = 434
17819	CEFBS_HasNEON, // VLD4DUPqWB_register_Asm_8 = 435
17820	CEFBS_HasNEON, // VLD4LNdAsm_16 = 436
17821	CEFBS_HasNEON, // VLD4LNdAsm_32 = 437
17822	CEFBS_HasNEON, // VLD4LNdAsm_8 = 438
17823	CEFBS_HasNEON, // VLD4LNdWB_fixed_Asm_16 = 439
17824	CEFBS_HasNEON, // VLD4LNdWB_fixed_Asm_32 = 440
17825	CEFBS_HasNEON, // VLD4LNdWB_fixed_Asm_8 = 441
17826	CEFBS_HasNEON, // VLD4LNdWB_register_Asm_16 = 442
17827	CEFBS_HasNEON, // VLD4LNdWB_register_Asm_32 = 443
17828	CEFBS_HasNEON, // VLD4LNdWB_register_Asm_8 = 444
17829	CEFBS_HasNEON, // VLD4LNqAsm_16 = 445
17830	CEFBS_HasNEON, // VLD4LNqAsm_32 = 446
17831	CEFBS_HasNEON, // VLD4LNqWB_fixed_Asm_16 = 447
17832	CEFBS_HasNEON, // VLD4LNqWB_fixed_Asm_32 = 448
17833	CEFBS_HasNEON, // VLD4LNqWB_register_Asm_16 = 449
17834	CEFBS_HasNEON, // VLD4LNqWB_register_Asm_32 = 450
17835	CEFBS_HasNEON, // VLD4dAsm_16 = 451
17836	CEFBS_HasNEON, // VLD4dAsm_32 = 452
17837	CEFBS_HasNEON, // VLD4dAsm_8 = 453
17838	CEFBS_HasNEON, // VLD4dWB_fixed_Asm_16 = 454
17839	CEFBS_HasNEON, // VLD4dWB_fixed_Asm_32 = 455
17840	CEFBS_HasNEON, // VLD4dWB_fixed_Asm_8 = 456
17841	CEFBS_HasNEON, // VLD4dWB_register_Asm_16 = 457
17842	CEFBS_HasNEON, // VLD4dWB_register_Asm_32 = 458
17843	CEFBS_HasNEON, // VLD4dWB_register_Asm_8 = 459
17844	CEFBS_HasNEON, // VLD4qAsm_16 = 460
17845	CEFBS_HasNEON, // VLD4qAsm_32 = 461
17846	CEFBS_HasNEON, // VLD4qAsm_8 = 462
17847	CEFBS_HasNEON, // VLD4qWB_fixed_Asm_16 = 463
17848	CEFBS_HasNEON, // VLD4qWB_fixed_Asm_32 = 464
17849	CEFBS_HasNEON, // VLD4qWB_fixed_Asm_8 = 465
17850	CEFBS_HasNEON, // VLD4qWB_register_Asm_16 = 466
17851	CEFBS_HasNEON, // VLD4qWB_register_Asm_32 = 467
17852	CEFBS_HasNEON, // VLD4qWB_register_Asm_8 = 468
17853	CEFBS_None, // VMOVD0 = 469
17854	CEFBS_HasFPRegs64, // VMOVDcc = 470
17855	CEFBS_HasFPRegs, // VMOVHcc = 471
17856	CEFBS_None, // VMOVQ0 = 472
17857	CEFBS_HasFPRegs, // VMOVScc = 473
17858	CEFBS_HasNEON, // VST1LNdAsm_16 = 474
17859	CEFBS_HasNEON, // VST1LNdAsm_32 = 475
17860	CEFBS_HasNEON, // VST1LNdAsm_8 = 476
17861	CEFBS_HasNEON, // VST1LNdWB_fixed_Asm_16 = 477
17862	CEFBS_HasNEON, // VST1LNdWB_fixed_Asm_32 = 478
17863	CEFBS_HasNEON, // VST1LNdWB_fixed_Asm_8 = 479
17864	CEFBS_HasNEON, // VST1LNdWB_register_Asm_16 = 480
17865	CEFBS_HasNEON, // VST1LNdWB_register_Asm_32 = 481
17866	CEFBS_HasNEON, // VST1LNdWB_register_Asm_8 = 482
17867	CEFBS_HasNEON, // VST2LNdAsm_16 = 483
17868	CEFBS_HasNEON, // VST2LNdAsm_32 = 484
17869	CEFBS_HasNEON, // VST2LNdAsm_8 = 485
17870	CEFBS_HasNEON, // VST2LNdWB_fixed_Asm_16 = 486
17871	CEFBS_HasNEON, // VST2LNdWB_fixed_Asm_32 = 487
17872	CEFBS_HasNEON, // VST2LNdWB_fixed_Asm_8 = 488
17873	CEFBS_HasNEON, // VST2LNdWB_register_Asm_16 = 489
17874	CEFBS_HasNEON, // VST2LNdWB_register_Asm_32 = 490
17875	CEFBS_HasNEON, // VST2LNdWB_register_Asm_8 = 491
17876	CEFBS_HasNEON, // VST2LNqAsm_16 = 492
17877	CEFBS_HasNEON, // VST2LNqAsm_32 = 493
17878	CEFBS_HasNEON, // VST2LNqWB_fixed_Asm_16 = 494
17879	CEFBS_HasNEON, // VST2LNqWB_fixed_Asm_32 = 495
17880	CEFBS_HasNEON, // VST2LNqWB_register_Asm_16 = 496
17881	CEFBS_HasNEON, // VST2LNqWB_register_Asm_32 = 497
17882	CEFBS_HasNEON, // VST3LNdAsm_16 = 498
17883	CEFBS_HasNEON, // VST3LNdAsm_32 = 499
17884	CEFBS_HasNEON, // VST3LNdAsm_8 = 500
17885	CEFBS_HasNEON, // VST3LNdWB_fixed_Asm_16 = 501
17886	CEFBS_HasNEON, // VST3LNdWB_fixed_Asm_32 = 502
17887	CEFBS_HasNEON, // VST3LNdWB_fixed_Asm_8 = 503
17888	CEFBS_HasNEON, // VST3LNdWB_register_Asm_16 = 504
17889	CEFBS_HasNEON, // VST3LNdWB_register_Asm_32 = 505
17890	CEFBS_HasNEON, // VST3LNdWB_register_Asm_8 = 506
17891	CEFBS_HasNEON, // VST3LNqAsm_16 = 507
17892	CEFBS_HasNEON, // VST3LNqAsm_32 = 508
17893	CEFBS_HasNEON, // VST3LNqWB_fixed_Asm_16 = 509
17894	CEFBS_HasNEON, // VST3LNqWB_fixed_Asm_32 = 510
17895	CEFBS_HasNEON, // VST3LNqWB_register_Asm_16 = 511
17896	CEFBS_HasNEON, // VST3LNqWB_register_Asm_32 = 512
17897	CEFBS_HasNEON, // VST3dAsm_16 = 513
17898	CEFBS_HasNEON, // VST3dAsm_32 = 514
17899	CEFBS_HasNEON, // VST3dAsm_8 = 515
17900	CEFBS_HasNEON, // VST3dWB_fixed_Asm_16 = 516
17901	CEFBS_HasNEON, // VST3dWB_fixed_Asm_32 = 517
17902	CEFBS_HasNEON, // VST3dWB_fixed_Asm_8 = 518
17903	CEFBS_HasNEON, // VST3dWB_register_Asm_16 = 519
17904	CEFBS_HasNEON, // VST3dWB_register_Asm_32 = 520
17905	CEFBS_HasNEON, // VST3dWB_register_Asm_8 = 521
17906	CEFBS_HasNEON, // VST3qAsm_16 = 522
17907	CEFBS_HasNEON, // VST3qAsm_32 = 523
17908	CEFBS_HasNEON, // VST3qAsm_8 = 524
17909	CEFBS_HasNEON, // VST3qWB_fixed_Asm_16 = 525
17910	CEFBS_HasNEON, // VST3qWB_fixed_Asm_32 = 526
17911	CEFBS_HasNEON, // VST3qWB_fixed_Asm_8 = 527
17912	CEFBS_HasNEON, // VST3qWB_register_Asm_16 = 528
17913	CEFBS_HasNEON, // VST3qWB_register_Asm_32 = 529
17914	CEFBS_HasNEON, // VST3qWB_register_Asm_8 = 530
17915	CEFBS_HasNEON, // VST4LNdAsm_16 = 531
17916	CEFBS_HasNEON, // VST4LNdAsm_32 = 532
17917	CEFBS_HasNEON, // VST4LNdAsm_8 = 533
17918	CEFBS_HasNEON, // VST4LNdWB_fixed_Asm_16 = 534
17919	CEFBS_HasNEON, // VST4LNdWB_fixed_Asm_32 = 535
17920	CEFBS_HasNEON, // VST4LNdWB_fixed_Asm_8 = 536
17921	CEFBS_HasNEON, // VST4LNdWB_register_Asm_16 = 537
17922	CEFBS_HasNEON, // VST4LNdWB_register_Asm_32 = 538
17923	CEFBS_HasNEON, // VST4LNdWB_register_Asm_8 = 539
17924	CEFBS_HasNEON, // VST4LNqAsm_16 = 540
17925	CEFBS_HasNEON, // VST4LNqAsm_32 = 541
17926	CEFBS_HasNEON, // VST4LNqWB_fixed_Asm_16 = 542
17927	CEFBS_HasNEON, // VST4LNqWB_fixed_Asm_32 = 543
17928	CEFBS_HasNEON, // VST4LNqWB_register_Asm_16 = 544
17929	CEFBS_HasNEON, // VST4LNqWB_register_Asm_32 = 545
17930	CEFBS_HasNEON, // VST4dAsm_16 = 546
17931	CEFBS_HasNEON, // VST4dAsm_32 = 547
17932	CEFBS_HasNEON, // VST4dAsm_8 = 548
17933	CEFBS_HasNEON, // VST4dWB_fixed_Asm_16 = 549
17934	CEFBS_HasNEON, // VST4dWB_fixed_Asm_32 = 550
17935	CEFBS_HasNEON, // VST4dWB_fixed_Asm_8 = 551
17936	CEFBS_HasNEON, // VST4dWB_register_Asm_16 = 552
17937	CEFBS_HasNEON, // VST4dWB_register_Asm_32 = 553
17938	CEFBS_HasNEON, // VST4dWB_register_Asm_8 = 554
17939	CEFBS_HasNEON, // VST4qAsm_16 = 555
17940	CEFBS_HasNEON, // VST4qAsm_32 = 556
17941	CEFBS_HasNEON, // VST4qAsm_8 = 557
17942	CEFBS_HasNEON, // VST4qWB_fixed_Asm_16 = 558
17943	CEFBS_HasNEON, // VST4qWB_fixed_Asm_32 = 559
17944	CEFBS_HasNEON, // VST4qWB_fixed_Asm_8 = 560
17945	CEFBS_HasNEON, // VST4qWB_register_Asm_16 = 561
17946	CEFBS_HasNEON, // VST4qWB_register_Asm_32 = 562
17947	CEFBS_HasNEON, // VST4qWB_register_Asm_8 = 563
17948	CEFBS_None, // WIN__CHKSTK = 564
17949	CEFBS_None, // WIN__DBZCHK = 565
17950	CEFBS_IsThumb2, // t2ABS = 566
17951	CEFBS_IsThumb2, // t2ADDSri = 567
17952	CEFBS_IsThumb2, // t2ADDSrr = 568
17953	CEFBS_IsThumb2, // t2ADDSrs = 569
17954	CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2BF_LabelPseudo = 570
17955	CEFBS_IsThumb_HasV8MBaseline, // t2BR_JT = 571
17956	CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2DoLoopStart = 572
17957	CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2DoLoopStartTP = 573
17958	CEFBS_IsThumb2, // t2LDMIA_RET = 574
17959	CEFBS_IsThumb2, // t2LDRBpcrel = 575
17960	CEFBS_IsThumb2, // t2LDRConstPool = 576
17961	CEFBS_IsThumb2, // t2LDRHpcrel = 577
17962	CEFBS_IsThumb2, // t2LDRSBpcrel = 578
17963	CEFBS_IsThumb2, // t2LDRSHpcrel = 579
17964	CEFBS_IsThumb2, // t2LDRpci_pic = 580
17965	CEFBS_IsThumb2, // t2LDRpcrel = 581
17966	CEFBS_IsThumb2, // t2LEApcrel = 582
17967	CEFBS_IsThumb2, // t2LEApcrelJT = 583
17968	CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2LoopDec = 584
17969	CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2LoopEnd = 585
17970	CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2LoopEndDec = 586
17971	CEFBS_IsThumb2, // t2MOVCCasr = 587
17972	CEFBS_IsThumb2, // t2MOVCCi = 588
17973	CEFBS_IsThumb2, // t2MOVCCi16 = 589
17974	CEFBS_IsThumb2, // t2MOVCCi32imm = 590
17975	CEFBS_IsThumb2, // t2MOVCClsl = 591
17976	CEFBS_IsThumb2, // t2MOVCClsr = 592
17977	CEFBS_IsThumb2, // t2MOVCCr = 593
17978	CEFBS_IsThumb2, // t2MOVCCror = 594
17979	CEFBS_IsThumb2, // t2MOVSsi = 595
17980	CEFBS_IsThumb2, // t2MOVSsr = 596
17981	CEFBS_IsThumb_HasV8MBaseline, // t2MOVTi16_ga_pcrel = 597
17982	CEFBS_IsThumb_HasV8MBaseline, // t2MOV_ga_pcrel = 598
17983	CEFBS_None, // t2MOVi16_ga_pcrel = 599
17984	CEFBS_IsThumb, // t2MOVi32imm = 600
17985	CEFBS_IsThumb2, // t2MOVsi = 601
17986	CEFBS_IsThumb2, // t2MOVsr = 602
17987	CEFBS_IsThumb2, // t2MVNCCi = 603
17988	CEFBS_IsThumb2, // t2RSBSri = 604
17989	CEFBS_IsThumb2, // t2RSBSrs = 605
17990	CEFBS_IsThumb2, // t2STRB_preidx = 606
17991	CEFBS_IsThumb2, // t2STRH_preidx = 607
17992	CEFBS_IsThumb2, // t2STR_preidx = 608
17993	CEFBS_IsThumb2, // t2SUBSri = 609
17994	CEFBS_IsThumb2, // t2SUBSrr = 610
17995	CEFBS_IsThumb2, // t2SUBSrs = 611
17996	CEFBS_None, // t2SpeculationBarrierISBDSBEndBB = 612
17997	CEFBS_None, // t2SpeculationBarrierSBEndBB = 613
17998	CEFBS_IsThumb2, // t2TBB_JT = 614
17999	CEFBS_IsThumb2, // t2TBH_JT = 615
18000	CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2WhileLoopStart = 616
18001	CEFBS_None, // tADCS = 617
18002	CEFBS_None, // tADDSi3 = 618
18003	CEFBS_None, // tADDSi8 = 619
18004	CEFBS_None, // tADDSrr = 620
18005	CEFBS_IsThumb, // tADDframe = 621
18006	CEFBS_IsThumb, // tADJCALLSTACKDOWN = 622
18007	CEFBS_IsThumb, // tADJCALLSTACKUP = 623
18008	CEFBS_IsThumb_Has8MSecExt, // tBLXNS_CALL = 624
18009	CEFBS_IsThumb_HasV5T, // tBLXr_noip = 625
18010	CEFBS_IsThumb, // tBL_PUSHLR = 626
18011	CEFBS_IsThumb, // tBRIND = 627
18012	CEFBS_IsThumb, // tBR_JTr = 628
18013	CEFBS_IsThumb, // tBXNS_RET = 629
18014	CEFBS_IsThumb, // tBX_CALL = 630
18015	CEFBS_IsThumb, // tBX_RET = 631
18016	CEFBS_IsThumb, // tBX_RET_vararg = 632
18017	CEFBS_IsThumb, // tBfar = 633
18018	CEFBS_IsThumb, // tLDMIA_UPD = 634
18019	CEFBS_IsThumb, // tLDRConstPool = 635
18020	CEFBS_IsThumb, // tLDRLIT_ga_abs = 636
18021	CEFBS_IsThumb, // tLDRLIT_ga_pcrel = 637
18022	CEFBS_IsThumb, // tLDR_postidx = 638
18023	CEFBS_IsThumb, // tLDRpci_pic = 639
18024	CEFBS_IsThumb, // tLEApcrel = 640
18025	CEFBS_IsThumb, // tLEApcrelJT = 641
18026	CEFBS_None, // tLSLSri = 642
18027	CEFBS_None, // tMOVCCr_pseudo = 643
18028	CEFBS_IsThumb, // tPOP_RET = 644
18029	CEFBS_None, // tRSBS = 645
18030	CEFBS_None, // tSBCS = 646
18031	CEFBS_None, // tSUBSi3 = 647
18032	CEFBS_None, // tSUBSi8 = 648
18033	CEFBS_None, // tSUBSrr = 649
18034	CEFBS_IsThumb2, // tTAILJMPd = 650
18035	CEFBS_IsThumb, // tTAILJMPdND = 651
18036	CEFBS_IsThumb, // tTAILJMPr = 652
18037	CEFBS_IsThumb, // tTBB_JT = 653
18038	CEFBS_IsThumb, // tTBH_JT = 654
18039	CEFBS_IsThumb, // tTPsoft = 655
18040	CEFBS_IsARM, // ADCri = 656
18041	CEFBS_IsARM, // ADCrr = 657
18042	CEFBS_IsARM, // ADCrsi = 658
18043	CEFBS_IsARM, // ADCrsr = 659
18044	CEFBS_IsARM, // ADDri = 660
18045	CEFBS_IsARM, // ADDrr = 661
18046	CEFBS_IsARM, // ADDrsi = 662
18047	CEFBS_IsARM, // ADDrsr = 663
18048	CEFBS_IsARM, // ADR = 664
18049	CEFBS_HasV8_HasCrypto, // AESD = 665
18050	CEFBS_HasV8_HasCrypto, // AESE = 666
18051	CEFBS_HasV8_HasCrypto, // AESIMC = 667
18052	CEFBS_HasV8_HasCrypto, // AESMC = 668
18053	CEFBS_IsARM, // ANDri = 669
18054	CEFBS_IsARM, // ANDrr = 670
18055	CEFBS_IsARM, // ANDrsi = 671
18056	CEFBS_IsARM, // ANDrsr = 672
18057	CEFBS_HasBF16_HasNEON, // BF16VDOTI_VDOTD = 673
18058	CEFBS_HasBF16_HasNEON, // BF16VDOTI_VDOTQ = 674
18059	CEFBS_HasBF16_HasNEON, // BF16VDOTS_VDOTD = 675
18060	CEFBS_HasBF16_HasNEON, // BF16VDOTS_VDOTQ = 676
18061	CEFBS_HasBF16_HasNEON, // BF16_VCVT = 677
18062	CEFBS_HasBF16, // BF16_VCVTB = 678
18063	CEFBS_HasBF16, // BF16_VCVTT = 679
18064	CEFBS_IsARM_HasV6T2, // BFC = 680
18065	CEFBS_IsARM_HasV6T2, // BFI = 681
18066	CEFBS_IsARM, // BICri = 682
18067	CEFBS_IsARM, // BICrr = 683
18068	CEFBS_IsARM, // BICrsi = 684
18069	CEFBS_IsARM, // BICrsr = 685
18070	CEFBS_IsARM, // BKPT = 686
18071	CEFBS_IsARM, // BL = 687
18072	CEFBS_IsARM_HasV5T, // BLX = 688
18073	CEFBS_IsARM_HasV5T, // BLX_pred = 689
18074	CEFBS_IsARM_HasV5T, // BLXi = 690
18075	CEFBS_IsARM, // BL_pred = 691
18076	CEFBS_IsARM_HasV4T, // BX = 692
18077	CEFBS_IsARM, // BXJ = 693
18078	CEFBS_IsARM_HasV4T, // BX_RET = 694
18079	CEFBS_IsARM_HasV4T, // BX_pred = 695
18080	CEFBS_IsARM, // Bcc = 696
18081	CEFBS_HasCDE, // CDE_CX1 = 697
18082	CEFBS_HasCDE, // CDE_CX1A = 698
18083	CEFBS_HasCDE, // CDE_CX1D = 699
18084	CEFBS_HasCDE, // CDE_CX1DA = 700
18085	CEFBS_HasCDE, // CDE_CX2 = 701
18086	CEFBS_HasCDE, // CDE_CX2A = 702
18087	CEFBS_HasCDE, // CDE_CX2D = 703
18088	CEFBS_HasCDE, // CDE_CX2DA = 704
18089	CEFBS_HasCDE, // CDE_CX3 = 705
18090	CEFBS_HasCDE, // CDE_CX3A = 706
18091	CEFBS_HasCDE, // CDE_CX3D = 707
18092	CEFBS_HasCDE, // CDE_CX3DA = 708
18093	CEFBS_HasCDE_HasFPRegs, // CDE_VCX1A_fpdp = 709
18094	CEFBS_HasCDE_HasFPRegs, // CDE_VCX1A_fpsp = 710
18095	CEFBS_HasCDE_HasMVEInt, // CDE_VCX1A_vec = 711
18096	CEFBS_HasCDE_HasFPRegs, // CDE_VCX1_fpdp = 712
18097	CEFBS_HasCDE_HasFPRegs, // CDE_VCX1_fpsp = 713
18098	CEFBS_HasCDE_HasMVEInt, // CDE_VCX1_vec = 714
18099	CEFBS_HasCDE_HasFPRegs, // CDE_VCX2A_fpdp = 715
18100	CEFBS_HasCDE_HasFPRegs, // CDE_VCX2A_fpsp = 716
18101	CEFBS_HasCDE_HasMVEInt, // CDE_VCX2A_vec = 717
18102	CEFBS_HasCDE_HasFPRegs, // CDE_VCX2_fpdp = 718
18103	CEFBS_HasCDE_HasFPRegs, // CDE_VCX2_fpsp = 719
18104	CEFBS_HasCDE_HasMVEInt, // CDE_VCX2_vec = 720
18105	CEFBS_HasCDE_HasFPRegs, // CDE_VCX3A_fpdp = 721
18106	CEFBS_HasCDE_HasFPRegs, // CDE_VCX3A_fpsp = 722
18107	CEFBS_HasCDE_HasMVEInt, // CDE_VCX3A_vec = 723
18108	CEFBS_HasCDE_HasFPRegs, // CDE_VCX3_fpdp = 724
18109	CEFBS_HasCDE_HasFPRegs, // CDE_VCX3_fpsp = 725
18110	CEFBS_HasCDE_HasMVEInt, // CDE_VCX3_vec = 726
18111	CEFBS_IsARM_PreV8, // CDP = 727
18112	CEFBS_IsARM_PreV8, // CDP2 = 728
18113	CEFBS_IsARM_HasV6K, // CLREX = 729
18114	CEFBS_IsARM_HasV5T, // CLZ = 730
18115	CEFBS_IsARM, // CMNri = 731
18116	CEFBS_IsARM, // CMNzrr = 732
18117	CEFBS_IsARM, // CMNzrsi = 733
18118	CEFBS_IsARM, // CMNzrsr = 734
18119	CEFBS_IsARM, // CMPri = 735
18120	CEFBS_IsARM, // CMPrr = 736
18121	CEFBS_IsARM, // CMPrsi = 737
18122	CEFBS_IsARM, // CMPrsr = 738
18123	CEFBS_IsARM, // CPS1p = 739
18124	CEFBS_IsARM, // CPS2p = 740
18125	CEFBS_IsARM, // CPS3p = 741
18126	CEFBS_IsARM_HasV8_HasCRC, // CRC32B = 742
18127	CEFBS_IsARM_HasV8_HasCRC, // CRC32CB = 743
18128	CEFBS_IsARM_HasV8_HasCRC, // CRC32CH = 744
18129	CEFBS_IsARM_HasV8_HasCRC, // CRC32CW = 745
18130	CEFBS_IsARM_HasV8_HasCRC, // CRC32H = 746
18131	CEFBS_IsARM_HasV8_HasCRC, // CRC32W = 747
18132	CEFBS_IsARM_HasV7, // DBG = 748
18133	CEFBS_IsARM_HasDB, // DMB = 749
18134	CEFBS_IsARM_HasDB, // DSB = 750
18135	CEFBS_IsARM, // EORri = 751
18136	CEFBS_IsARM, // EORrr = 752
18137	CEFBS_IsARM, // EORrsi = 753
18138	CEFBS_IsARM, // EORrsr = 754
18139	CEFBS_IsARM_HasVirtualization, // ERET = 755
18140	CEFBS_HasVFP3_HasDPVFP, // FCONSTD = 756
18141	CEFBS_HasFullFP16, // FCONSTH = 757
18142	CEFBS_HasVFP3, // FCONSTS = 758
18143	CEFBS_HasFPRegs, // FLDMXDB_UPD = 759
18144	CEFBS_HasFPRegs, // FLDMXIA = 760
18145	CEFBS_HasFPRegs, // FLDMXIA_UPD = 761
18146	CEFBS_HasFPRegs, // FMSTAT = 762
18147	CEFBS_HasFPRegs, // FSTMXDB_UPD = 763
18148	CEFBS_HasFPRegs, // FSTMXIA = 764
18149	CEFBS_HasFPRegs, // FSTMXIA_UPD = 765
18150	CEFBS_IsARM_HasV6, // HINT = 766
18151	CEFBS_IsARM_HasV8, // HLT = 767
18152	CEFBS_IsARM_HasVirtualization, // HVC = 768
18153	CEFBS_IsARM_HasDB, // ISB = 769
18154	CEFBS_IsARM_HasAcquireRelease, // LDA = 770
18155	CEFBS_IsARM_HasAcquireRelease, // LDAB = 771
18156	CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // LDAEX = 772
18157	CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // LDAEXB = 773
18158	CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // LDAEXD = 774
18159	CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // LDAEXH = 775
18160	CEFBS_IsARM_HasAcquireRelease, // LDAH = 776
18161	CEFBS_IsARM_PreV8, // LDC2L_OFFSET = 777
18162	CEFBS_IsARM_PreV8, // LDC2L_OPTION = 778
18163	CEFBS_IsARM_PreV8, // LDC2L_POST = 779
18164	CEFBS_IsARM_PreV8, // LDC2L_PRE = 780
18165	CEFBS_IsARM_PreV8, // LDC2_OFFSET = 781
18166	CEFBS_IsARM_PreV8, // LDC2_OPTION = 782
18167	CEFBS_IsARM_PreV8, // LDC2_POST = 783
18168	CEFBS_IsARM_PreV8, // LDC2_PRE = 784
18169	CEFBS_IsARM, // LDCL_OFFSET = 785
18170	CEFBS_IsARM, // LDCL_OPTION = 786
18171	CEFBS_IsARM, // LDCL_POST = 787
18172	CEFBS_IsARM, // LDCL_PRE = 788
18173	CEFBS_IsARM, // LDC_OFFSET = 789
18174	CEFBS_IsARM, // LDC_OPTION = 790
18175	CEFBS_IsARM, // LDC_POST = 791
18176	CEFBS_IsARM, // LDC_PRE = 792
18177	CEFBS_IsARM, // LDMDA = 793
18178	CEFBS_IsARM, // LDMDA_UPD = 794
18179	CEFBS_IsARM, // LDMDB = 795
18180	CEFBS_IsARM, // LDMDB_UPD = 796
18181	CEFBS_IsARM, // LDMIA = 797
18182	CEFBS_IsARM, // LDMIA_UPD = 798
18183	CEFBS_IsARM, // LDMIB = 799
18184	CEFBS_IsARM, // LDMIB_UPD = 800
18185	CEFBS_IsARM, // LDRBT_POST_IMM = 801
18186	CEFBS_IsARM, // LDRBT_POST_REG = 802
18187	CEFBS_IsARM, // LDRB_POST_IMM = 803
18188	CEFBS_IsARM, // LDRB_POST_REG = 804
18189	CEFBS_IsARM, // LDRB_PRE_IMM = 805
18190	CEFBS_IsARM, // LDRB_PRE_REG = 806
18191	CEFBS_IsARM, // LDRBi12 = 807
18192	CEFBS_IsARM, // LDRBrs = 808
18193	CEFBS_IsARM_HasV5TE, // LDRD = 809
18194	CEFBS_IsARM, // LDRD_POST = 810
18195	CEFBS_IsARM, // LDRD_PRE = 811
18196	CEFBS_IsARM, // LDREX = 812
18197	CEFBS_IsARM, // LDREXB = 813
18198	CEFBS_IsARM, // LDREXD = 814
18199	CEFBS_IsARM, // LDREXH = 815
18200	CEFBS_IsARM, // LDRH = 816
18201	CEFBS_IsARM, // LDRHTi = 817
18202	CEFBS_IsARM, // LDRHTr = 818
18203	CEFBS_IsARM, // LDRH_POST = 819
18204	CEFBS_IsARM, // LDRH_PRE = 820
18205	CEFBS_IsARM, // LDRSB = 821
18206	CEFBS_IsARM, // LDRSBTi = 822
18207	CEFBS_IsARM, // LDRSBTr = 823
18208	CEFBS_IsARM, // LDRSB_POST = 824
18209	CEFBS_IsARM, // LDRSB_PRE = 825
18210	CEFBS_IsARM, // LDRSH = 826
18211	CEFBS_IsARM, // LDRSHTi = 827
18212	CEFBS_IsARM, // LDRSHTr = 828
18213	CEFBS_IsARM, // LDRSH_POST = 829
18214	CEFBS_IsARM, // LDRSH_PRE = 830
18215	CEFBS_IsARM, // LDRT_POST_IMM = 831
18216	CEFBS_IsARM, // LDRT_POST_REG = 832
18217	CEFBS_IsARM, // LDR_POST_IMM = 833
18218	CEFBS_IsARM, // LDR_POST_REG = 834
18219	CEFBS_IsARM, // LDR_PRE_IMM = 835
18220	CEFBS_IsARM, // LDR_PRE_REG = 836
18221	CEFBS_IsARM, // LDRcp = 837
18222	CEFBS_IsARM, // LDRi12 = 838
18223	CEFBS_IsARM, // LDRrs = 839
18224	CEFBS_IsARM, // MCR = 840
18225	CEFBS_IsARM_PreV8, // MCR2 = 841
18226	CEFBS_IsARM, // MCRR = 842
18227	CEFBS_IsARM_PreV8, // MCRR2 = 843
18228	CEFBS_IsARM_HasV6, // MLA = 844
18229	CEFBS_IsARM_HasV6T2, // MLS = 845
18230	CEFBS_IsARM, // MOVPCLR = 846
18231	CEFBS_IsARM_HasV6T2, // MOVTi16 = 847
18232	CEFBS_IsARM, // MOVi = 848
18233	CEFBS_IsARM_HasV6T2, // MOVi16 = 849
18234	CEFBS_IsARM, // MOVr = 850
18235	CEFBS_IsARM, // MOVr_TC = 851
18236	CEFBS_IsARM, // MOVsi = 852
18237	CEFBS_IsARM, // MOVsr = 853
18238	CEFBS_IsARM, // MRC = 854
18239	CEFBS_IsARM_PreV8, // MRC2 = 855
18240	CEFBS_IsARM, // MRRC = 856
18241	CEFBS_IsARM_PreV8, // MRRC2 = 857
18242	CEFBS_IsARM, // MRS = 858
18243	CEFBS_IsARM_HasVirtualization, // MRSbanked = 859
18244	CEFBS_IsARM, // MRSsys = 860
18245	CEFBS_IsARM, // MSR = 861
18246	CEFBS_IsARM_HasVirtualization, // MSRbanked = 862
18247	CEFBS_IsARM, // MSRi = 863
18248	CEFBS_IsARM_HasV6, // MUL = 864
18249	CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_ASRLi = 865
18250	CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_ASRLr = 866
18251	CEFBS_HasMVEInt, // MVE_DLSTP_16 = 867
18252	CEFBS_HasMVEInt, // MVE_DLSTP_32 = 868
18253	CEFBS_HasMVEInt, // MVE_DLSTP_64 = 869
18254	CEFBS_HasMVEInt, // MVE_DLSTP_8 = 870
18255	CEFBS_HasMVEInt, // MVE_LCTP = 871
18256	CEFBS_HasMVEInt, // MVE_LETP = 872
18257	CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_LSLLi = 873
18258	CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_LSLLr = 874
18259	CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_LSRL = 875
18260	CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_SQRSHR = 876
18261	CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_SQRSHRL = 877
18262	CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_SQSHL = 878
18263	CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_SQSHLL = 879
18264	CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_SRSHR = 880
18265	CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_SRSHRL = 881
18266	CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_UQRSHL = 882
18267	CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_UQRSHLL = 883
18268	CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_UQSHL = 884
18269	CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_UQSHLL = 885
18270	CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_URSHR = 886
18271	CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_URSHRL = 887
18272	CEFBS_HasMVEInt, // MVE_VABAVs16 = 888
18273	CEFBS_HasMVEInt, // MVE_VABAVs32 = 889
18274	CEFBS_HasMVEInt, // MVE_VABAVs8 = 890
18275	CEFBS_HasMVEInt, // MVE_VABAVu16 = 891
18276	CEFBS_HasMVEInt, // MVE_VABAVu32 = 892
18277	CEFBS_HasMVEInt, // MVE_VABAVu8 = 893
18278	CEFBS_HasMVEFloat, // MVE_VABDf16 = 894
18279	CEFBS_HasMVEFloat, // MVE_VABDf32 = 895
18280	CEFBS_HasMVEInt, // MVE_VABDs16 = 896
18281	CEFBS_HasMVEInt, // MVE_VABDs32 = 897
18282	CEFBS_HasMVEInt, // MVE_VABDs8 = 898
18283	CEFBS_HasMVEInt, // MVE_VABDu16 = 899
18284	CEFBS_HasMVEInt, // MVE_VABDu32 = 900
18285	CEFBS_HasMVEInt, // MVE_VABDu8 = 901
18286	CEFBS_HasMVEFloat, // MVE_VABSf16 = 902
18287	CEFBS_HasMVEFloat, // MVE_VABSf32 = 903
18288	CEFBS_HasMVEInt, // MVE_VABSs16 = 904
18289	CEFBS_HasMVEInt, // MVE_VABSs32 = 905
18290	CEFBS_HasMVEInt, // MVE_VABSs8 = 906
18291	CEFBS_HasMVEInt, // MVE_VADC = 907
18292	CEFBS_HasMVEInt, // MVE_VADCI = 908
18293	CEFBS_HasMVEInt, // MVE_VADDLVs32acc = 909
18294	CEFBS_HasMVEInt, // MVE_VADDLVs32no_acc = 910
18295	CEFBS_HasMVEInt, // MVE_VADDLVu32acc = 911
18296	CEFBS_HasMVEInt, // MVE_VADDLVu32no_acc = 912
18297	CEFBS_HasMVEInt, // MVE_VADDVs16acc = 913
18298	CEFBS_HasMVEInt, // MVE_VADDVs16no_acc = 914
18299	CEFBS_HasMVEInt, // MVE_VADDVs32acc = 915
18300	CEFBS_HasMVEInt, // MVE_VADDVs32no_acc = 916
18301	CEFBS_HasMVEInt, // MVE_VADDVs8acc = 917
18302	CEFBS_HasMVEInt, // MVE_VADDVs8no_acc = 918
18303	CEFBS_HasMVEInt, // MVE_VADDVu16acc = 919
18304	CEFBS_HasMVEInt, // MVE_VADDVu16no_acc = 920
18305	CEFBS_HasMVEInt, // MVE_VADDVu32acc = 921
18306	CEFBS_HasMVEInt, // MVE_VADDVu32no_acc = 922
18307	CEFBS_HasMVEInt, // MVE_VADDVu8acc = 923
18308	CEFBS_HasMVEInt, // MVE_VADDVu8no_acc = 924
18309	CEFBS_HasMVEFloat, // MVE_VADD_qr_f16 = 925
18310	CEFBS_HasMVEFloat, // MVE_VADD_qr_f32 = 926
18311	CEFBS_HasMVEInt, // MVE_VADD_qr_i16 = 927
18312	CEFBS_HasMVEInt, // MVE_VADD_qr_i32 = 928
18313	CEFBS_HasMVEInt, // MVE_VADD_qr_i8 = 929
18314	CEFBS_HasMVEFloat, // MVE_VADDf16 = 930
18315	CEFBS_HasMVEFloat, // MVE_VADDf32 = 931
18316	CEFBS_HasMVEInt, // MVE_VADDi16 = 932
18317	CEFBS_HasMVEInt, // MVE_VADDi32 = 933
18318	CEFBS_HasMVEInt, // MVE_VADDi8 = 934
18319	CEFBS_HasMVEInt, // MVE_VAND = 935
18320	CEFBS_HasMVEInt, // MVE_VBIC = 936
18321	CEFBS_HasMVEInt, // MVE_VBICimmi16 = 937
18322	CEFBS_HasMVEInt, // MVE_VBICimmi32 = 938
18323	CEFBS_HasMVEInt, // MVE_VBRSR16 = 939
18324	CEFBS_HasMVEInt, // MVE_VBRSR32 = 940
18325	CEFBS_HasMVEInt, // MVE_VBRSR8 = 941
18326	CEFBS_HasMVEFloat, // MVE_VCADDf16 = 942
18327	CEFBS_HasMVEFloat, // MVE_VCADDf32 = 943
18328	CEFBS_HasMVEInt, // MVE_VCADDi16 = 944
18329	CEFBS_HasMVEInt, // MVE_VCADDi32 = 945
18330	CEFBS_HasMVEInt, // MVE_VCADDi8 = 946
18331	CEFBS_HasMVEInt, // MVE_VCLSs16 = 947
18332	CEFBS_HasMVEInt, // MVE_VCLSs32 = 948
18333	CEFBS_HasMVEInt, // MVE_VCLSs8 = 949
18334	CEFBS_HasMVEInt, // MVE_VCLZs16 = 950
18335	CEFBS_HasMVEInt, // MVE_VCLZs32 = 951
18336	CEFBS_HasMVEInt, // MVE_VCLZs8 = 952
18337	CEFBS_HasMVEFloat, // MVE_VCMLAf16 = 953
18338	CEFBS_HasMVEFloat, // MVE_VCMLAf32 = 954
18339	CEFBS_HasMVEFloat, // MVE_VCMPf16 = 955
18340	CEFBS_HasMVEFloat, // MVE_VCMPf16r = 956
18341	CEFBS_HasMVEFloat, // MVE_VCMPf32 = 957
18342	CEFBS_HasMVEFloat, // MVE_VCMPf32r = 958
18343	CEFBS_HasMVEInt, // MVE_VCMPi16 = 959
18344	CEFBS_HasMVEInt, // MVE_VCMPi16r = 960
18345	CEFBS_HasMVEInt, // MVE_VCMPi32 = 961
18346	CEFBS_HasMVEInt, // MVE_VCMPi32r = 962
18347	CEFBS_HasMVEInt, // MVE_VCMPi8 = 963
18348	CEFBS_HasMVEInt, // MVE_VCMPi8r = 964
18349	CEFBS_HasMVEInt, // MVE_VCMPs16 = 965
18350	CEFBS_HasMVEInt, // MVE_VCMPs16r = 966
18351	CEFBS_HasMVEInt, // MVE_VCMPs32 = 967
18352	CEFBS_HasMVEInt, // MVE_VCMPs32r = 968
18353	CEFBS_HasMVEInt, // MVE_VCMPs8 = 969
18354	CEFBS_HasMVEInt, // MVE_VCMPs8r = 970
18355	CEFBS_HasMVEInt, // MVE_VCMPu16 = 971
18356	CEFBS_HasMVEInt, // MVE_VCMPu16r = 972
18357	CEFBS_HasMVEInt, // MVE_VCMPu32 = 973
18358	CEFBS_HasMVEInt, // MVE_VCMPu32r = 974
18359	CEFBS_HasMVEInt, // MVE_VCMPu8 = 975
18360	CEFBS_HasMVEInt, // MVE_VCMPu8r = 976
18361	CEFBS_HasMVEFloat, // MVE_VCMULf16 = 977
18362	CEFBS_HasMVEFloat, // MVE_VCMULf32 = 978
18363	CEFBS_HasMVEInt, // MVE_VCTP16 = 979
18364	CEFBS_HasMVEInt, // MVE_VCTP32 = 980
18365	CEFBS_HasMVEInt, // MVE_VCTP64 = 981
18366	CEFBS_HasMVEInt, // MVE_VCTP8 = 982
18367	CEFBS_HasMVEFloat, // MVE_VCVTf16f32bh = 983
18368	CEFBS_HasMVEFloat, // MVE_VCVTf16f32th = 984
18369	CEFBS_HasMVEFloat, // MVE_VCVTf16s16_fix = 985
18370	CEFBS_HasMVEFloat, // MVE_VCVTf16s16n = 986
18371	CEFBS_HasMVEFloat, // MVE_VCVTf16u16_fix = 987
18372	CEFBS_HasMVEFloat, // MVE_VCVTf16u16n = 988
18373	CEFBS_HasMVEFloat, // MVE_VCVTf32f16bh = 989
18374	CEFBS_HasMVEFloat, // MVE_VCVTf32f16th = 990
18375	CEFBS_HasMVEFloat, // MVE_VCVTf32s32_fix = 991
18376	CEFBS_HasMVEFloat, // MVE_VCVTf32s32n = 992
18377	CEFBS_HasMVEFloat, // MVE_VCVTf32u32_fix = 993
18378	CEFBS_HasMVEFloat, // MVE_VCVTf32u32n = 994
18379	CEFBS_HasMVEFloat, // MVE_VCVTs16f16_fix = 995
18380	CEFBS_HasMVEFloat, // MVE_VCVTs16f16a = 996
18381	CEFBS_HasMVEFloat, // MVE_VCVTs16f16m = 997
18382	CEFBS_HasMVEFloat, // MVE_VCVTs16f16n = 998
18383	CEFBS_HasMVEFloat, // MVE_VCVTs16f16p = 999
18384	CEFBS_HasMVEFloat, // MVE_VCVTs16f16z = 1000
18385	CEFBS_HasMVEFloat, // MVE_VCVTs32f32_fix = 1001
18386	CEFBS_HasMVEFloat, // MVE_VCVTs32f32a = 1002
18387	CEFBS_HasMVEFloat, // MVE_VCVTs32f32m = 1003
18388	CEFBS_HasMVEFloat, // MVE_VCVTs32f32n = 1004
18389	CEFBS_HasMVEFloat, // MVE_VCVTs32f32p = 1005
18390	CEFBS_HasMVEFloat, // MVE_VCVTs32f32z = 1006
18391	CEFBS_HasMVEFloat, // MVE_VCVTu16f16_fix = 1007
18392	CEFBS_HasMVEFloat, // MVE_VCVTu16f16a = 1008
18393	CEFBS_HasMVEFloat, // MVE_VCVTu16f16m = 1009
18394	CEFBS_HasMVEFloat, // MVE_VCVTu16f16n = 1010
18395	CEFBS_HasMVEFloat, // MVE_VCVTu16f16p = 1011
18396	CEFBS_HasMVEFloat, // MVE_VCVTu16f16z = 1012
18397	CEFBS_HasMVEFloat, // MVE_VCVTu32f32_fix = 1013
18398	CEFBS_HasMVEFloat, // MVE_VCVTu32f32a = 1014
18399	CEFBS_HasMVEFloat, // MVE_VCVTu32f32m = 1015
18400	CEFBS_HasMVEFloat, // MVE_VCVTu32f32n = 1016
18401	CEFBS_HasMVEFloat, // MVE_VCVTu32f32p = 1017
18402	CEFBS_HasMVEFloat, // MVE_VCVTu32f32z = 1018
18403	CEFBS_HasMVEInt, // MVE_VDDUPu16 = 1019
18404	CEFBS_HasMVEInt, // MVE_VDDUPu32 = 1020
18405	CEFBS_HasMVEInt, // MVE_VDDUPu8 = 1021
18406	CEFBS_HasMVEInt, // MVE_VDUP16 = 1022
18407	CEFBS_HasMVEInt, // MVE_VDUP32 = 1023
18408	CEFBS_HasMVEInt, // MVE_VDUP8 = 1024
18409	CEFBS_HasMVEInt, // MVE_VDWDUPu16 = 1025
18410	CEFBS_HasMVEInt, // MVE_VDWDUPu32 = 1026
18411	CEFBS_HasMVEInt, // MVE_VDWDUPu8 = 1027
18412	CEFBS_HasMVEInt, // MVE_VEOR = 1028
18413	CEFBS_HasMVEFloat, // MVE_VFMA_qr_Sf16 = 1029
18414	CEFBS_HasMVEFloat, // MVE_VFMA_qr_Sf32 = 1030
18415	CEFBS_HasMVEFloat, // MVE_VFMA_qr_f16 = 1031
18416	CEFBS_HasMVEFloat, // MVE_VFMA_qr_f32 = 1032
18417	CEFBS_HasMVEFloat, // MVE_VFMAf16 = 1033
18418	CEFBS_HasMVEFloat, // MVE_VFMAf32 = 1034
18419	CEFBS_HasMVEFloat, // MVE_VFMSf16 = 1035
18420	CEFBS_HasMVEFloat, // MVE_VFMSf32 = 1036
18421	CEFBS_HasMVEInt, // MVE_VHADD_qr_s16 = 1037
18422	CEFBS_HasMVEInt, // MVE_VHADD_qr_s32 = 1038
18423	CEFBS_HasMVEInt, // MVE_VHADD_qr_s8 = 1039
18424	CEFBS_HasMVEInt, // MVE_VHADD_qr_u16 = 1040
18425	CEFBS_HasMVEInt, // MVE_VHADD_qr_u32 = 1041
18426	CEFBS_HasMVEInt, // MVE_VHADD_qr_u8 = 1042
18427	CEFBS_HasMVEInt, // MVE_VHADDs16 = 1043
18428	CEFBS_HasMVEInt, // MVE_VHADDs32 = 1044
18429	CEFBS_HasMVEInt, // MVE_VHADDs8 = 1045
18430	CEFBS_HasMVEInt, // MVE_VHADDu16 = 1046
18431	CEFBS_HasMVEInt, // MVE_VHADDu32 = 1047
18432	CEFBS_HasMVEInt, // MVE_VHADDu8 = 1048
18433	CEFBS_HasMVEInt, // MVE_VHCADDs16 = 1049
18434	CEFBS_HasMVEInt, // MVE_VHCADDs32 = 1050
18435	CEFBS_HasMVEInt, // MVE_VHCADDs8 = 1051
18436	CEFBS_HasMVEInt, // MVE_VHSUB_qr_s16 = 1052
18437	CEFBS_HasMVEInt, // MVE_VHSUB_qr_s32 = 1053
18438	CEFBS_HasMVEInt, // MVE_VHSUB_qr_s8 = 1054
18439	CEFBS_HasMVEInt, // MVE_VHSUB_qr_u16 = 1055
18440	CEFBS_HasMVEInt, // MVE_VHSUB_qr_u32 = 1056
18441	CEFBS_HasMVEInt, // MVE_VHSUB_qr_u8 = 1057
18442	CEFBS_HasMVEInt, // MVE_VHSUBs16 = 1058
18443	CEFBS_HasMVEInt, // MVE_VHSUBs32 = 1059
18444	CEFBS_HasMVEInt, // MVE_VHSUBs8 = 1060
18445	CEFBS_HasMVEInt, // MVE_VHSUBu16 = 1061
18446	CEFBS_HasMVEInt, // MVE_VHSUBu32 = 1062
18447	CEFBS_HasMVEInt, // MVE_VHSUBu8 = 1063
18448	CEFBS_HasMVEInt, // MVE_VIDUPu16 = 1064
18449	CEFBS_HasMVEInt, // MVE_VIDUPu32 = 1065
18450	CEFBS_HasMVEInt, // MVE_VIDUPu8 = 1066
18451	CEFBS_HasMVEInt, // MVE_VIWDUPu16 = 1067
18452	CEFBS_HasMVEInt, // MVE_VIWDUPu32 = 1068
18453	CEFBS_HasMVEInt, // MVE_VIWDUPu8 = 1069
18454	CEFBS_HasMVEInt, // MVE_VLD20_16 = 1070
18455	CEFBS_HasMVEInt, // MVE_VLD20_16_wb = 1071
18456	CEFBS_HasMVEInt, // MVE_VLD20_32 = 1072
18457	CEFBS_HasMVEInt, // MVE_VLD20_32_wb = 1073
18458	CEFBS_HasMVEInt, // MVE_VLD20_8 = 1074
18459	CEFBS_HasMVEInt, // MVE_VLD20_8_wb = 1075
18460	CEFBS_HasMVEInt, // MVE_VLD21_16 = 1076
18461	CEFBS_HasMVEInt, // MVE_VLD21_16_wb = 1077
18462	CEFBS_HasMVEInt, // MVE_VLD21_32 = 1078
18463	CEFBS_HasMVEInt, // MVE_VLD21_32_wb = 1079
18464	CEFBS_HasMVEInt, // MVE_VLD21_8 = 1080
18465	CEFBS_HasMVEInt, // MVE_VLD21_8_wb = 1081
18466	CEFBS_HasMVEInt, // MVE_VLD40_16 = 1082
18467	CEFBS_HasMVEInt, // MVE_VLD40_16_wb = 1083
18468	CEFBS_HasMVEInt, // MVE_VLD40_32 = 1084
18469	CEFBS_HasMVEInt, // MVE_VLD40_32_wb = 1085
18470	CEFBS_HasMVEInt, // MVE_VLD40_8 = 1086
18471	CEFBS_HasMVEInt, // MVE_VLD40_8_wb = 1087
18472	CEFBS_HasMVEInt, // MVE_VLD41_16 = 1088
18473	CEFBS_HasMVEInt, // MVE_VLD41_16_wb = 1089
18474	CEFBS_HasMVEInt, // MVE_VLD41_32 = 1090
18475	CEFBS_HasMVEInt, // MVE_VLD41_32_wb = 1091
18476	CEFBS_HasMVEInt, // MVE_VLD41_8 = 1092
18477	CEFBS_HasMVEInt, // MVE_VLD41_8_wb = 1093
18478	CEFBS_HasMVEInt, // MVE_VLD42_16 = 1094
18479	CEFBS_HasMVEInt, // MVE_VLD42_16_wb = 1095
18480	CEFBS_HasMVEInt, // MVE_VLD42_32 = 1096
18481	CEFBS_HasMVEInt, // MVE_VLD42_32_wb = 1097
18482	CEFBS_HasMVEInt, // MVE_VLD42_8 = 1098
18483	CEFBS_HasMVEInt, // MVE_VLD42_8_wb = 1099
18484	CEFBS_HasMVEInt, // MVE_VLD43_16 = 1100
18485	CEFBS_HasMVEInt, // MVE_VLD43_16_wb = 1101
18486	CEFBS_HasMVEInt, // MVE_VLD43_32 = 1102
18487	CEFBS_HasMVEInt, // MVE_VLD43_32_wb = 1103
18488	CEFBS_HasMVEInt, // MVE_VLD43_8 = 1104
18489	CEFBS_HasMVEInt, // MVE_VLD43_8_wb = 1105
18490	CEFBS_HasMVEInt, // MVE_VLDRBS16 = 1106
18491	CEFBS_HasMVEInt, // MVE_VLDRBS16_post = 1107
18492	CEFBS_HasMVEInt, // MVE_VLDRBS16_pre = 1108
18493	CEFBS_HasMVEInt, // MVE_VLDRBS16_rq = 1109
18494	CEFBS_HasMVEInt, // MVE_VLDRBS32 = 1110
18495	CEFBS_HasMVEInt, // MVE_VLDRBS32_post = 1111
18496	CEFBS_HasMVEInt, // MVE_VLDRBS32_pre = 1112
18497	CEFBS_HasMVEInt, // MVE_VLDRBS32_rq = 1113
18498	CEFBS_HasMVEInt, // MVE_VLDRBU16 = 1114
18499	CEFBS_HasMVEInt, // MVE_VLDRBU16_post = 1115
18500	CEFBS_HasMVEInt, // MVE_VLDRBU16_pre = 1116
18501	CEFBS_HasMVEInt, // MVE_VLDRBU16_rq = 1117
18502	CEFBS_HasMVEInt, // MVE_VLDRBU32 = 1118
18503	CEFBS_HasMVEInt, // MVE_VLDRBU32_post = 1119
18504	CEFBS_HasMVEInt, // MVE_VLDRBU32_pre = 1120
18505	CEFBS_HasMVEInt, // MVE_VLDRBU32_rq = 1121
18506	CEFBS_HasMVEInt, // MVE_VLDRBU8 = 1122
18507	CEFBS_HasMVEInt, // MVE_VLDRBU8_post = 1123
18508	CEFBS_HasMVEInt, // MVE_VLDRBU8_pre = 1124
18509	CEFBS_HasMVEInt, // MVE_VLDRBU8_rq = 1125
18510	CEFBS_HasMVEInt, // MVE_VLDRDU64_qi = 1126
18511	CEFBS_HasMVEInt, // MVE_VLDRDU64_qi_pre = 1127
18512	CEFBS_HasMVEInt, // MVE_VLDRDU64_rq = 1128
18513	CEFBS_HasMVEInt, // MVE_VLDRDU64_rq_u = 1129
18514	CEFBS_HasMVEInt, // MVE_VLDRHS32 = 1130
18515	CEFBS_HasMVEInt, // MVE_VLDRHS32_post = 1131
18516	CEFBS_HasMVEInt, // MVE_VLDRHS32_pre = 1132
18517	CEFBS_HasMVEInt, // MVE_VLDRHS32_rq = 1133
18518	CEFBS_HasMVEInt, // MVE_VLDRHS32_rq_u = 1134
18519	CEFBS_HasMVEInt, // MVE_VLDRHU16 = 1135
18520	CEFBS_HasMVEInt, // MVE_VLDRHU16_post = 1136
18521	CEFBS_HasMVEInt, // MVE_VLDRHU16_pre = 1137
18522	CEFBS_HasMVEInt, // MVE_VLDRHU16_rq = 1138
18523	CEFBS_HasMVEInt, // MVE_VLDRHU16_rq_u = 1139
18524	CEFBS_HasMVEInt, // MVE_VLDRHU32 = 1140
18525	CEFBS_HasMVEInt, // MVE_VLDRHU32_post = 1141
18526	CEFBS_HasMVEInt, // MVE_VLDRHU32_pre = 1142
18527	CEFBS_HasMVEInt, // MVE_VLDRHU32_rq = 1143
18528	CEFBS_HasMVEInt, // MVE_VLDRHU32_rq_u = 1144
18529	CEFBS_HasMVEInt, // MVE_VLDRWU32 = 1145
18530	CEFBS_HasMVEInt, // MVE_VLDRWU32_post = 1146
18531	CEFBS_HasMVEInt, // MVE_VLDRWU32_pre = 1147
18532	CEFBS_HasMVEInt, // MVE_VLDRWU32_qi = 1148
18533	CEFBS_HasMVEInt, // MVE_VLDRWU32_qi_pre = 1149
18534	CEFBS_HasMVEInt, // MVE_VLDRWU32_rq = 1150
18535	CEFBS_HasMVEInt, // MVE_VLDRWU32_rq_u = 1151
18536	CEFBS_HasMVEInt, // MVE_VMAXAVs16 = 1152
18537	CEFBS_HasMVEInt, // MVE_VMAXAVs32 = 1153
18538	CEFBS_HasMVEInt, // MVE_VMAXAVs8 = 1154
18539	CEFBS_HasMVEInt, // MVE_VMAXAs16 = 1155
18540	CEFBS_HasMVEInt, // MVE_VMAXAs32 = 1156
18541	CEFBS_HasMVEInt, // MVE_VMAXAs8 = 1157
18542	CEFBS_HasMVEFloat, // MVE_VMAXNMAVf16 = 1158
18543	CEFBS_HasMVEFloat, // MVE_VMAXNMAVf32 = 1159
18544	CEFBS_HasMVEFloat, // MVE_VMAXNMAf16 = 1160
18545	CEFBS_HasMVEFloat, // MVE_VMAXNMAf32 = 1161
18546	CEFBS_HasMVEFloat, // MVE_VMAXNMVf16 = 1162
18547	CEFBS_HasMVEFloat, // MVE_VMAXNMVf32 = 1163
18548	CEFBS_HasMVEFloat, // MVE_VMAXNMf16 = 1164
18549	CEFBS_HasMVEFloat, // MVE_VMAXNMf32 = 1165
18550	CEFBS_HasMVEInt, // MVE_VMAXVs16 = 1166
18551	CEFBS_HasMVEInt, // MVE_VMAXVs32 = 1167
18552	CEFBS_HasMVEInt, // MVE_VMAXVs8 = 1168
18553	CEFBS_HasMVEInt, // MVE_VMAXVu16 = 1169
18554	CEFBS_HasMVEInt, // MVE_VMAXVu32 = 1170
18555	CEFBS_HasMVEInt, // MVE_VMAXVu8 = 1171
18556	CEFBS_HasMVEInt, // MVE_VMAXs16 = 1172
18557	CEFBS_HasMVEInt, // MVE_VMAXs32 = 1173
18558	CEFBS_HasMVEInt, // MVE_VMAXs8 = 1174
18559	CEFBS_HasMVEInt, // MVE_VMAXu16 = 1175
18560	CEFBS_HasMVEInt, // MVE_VMAXu32 = 1176
18561	CEFBS_HasMVEInt, // MVE_VMAXu8 = 1177
18562	CEFBS_HasMVEInt, // MVE_VMINAVs16 = 1178
18563	CEFBS_HasMVEInt, // MVE_VMINAVs32 = 1179
18564	CEFBS_HasMVEInt, // MVE_VMINAVs8 = 1180
18565	CEFBS_HasMVEInt, // MVE_VMINAs16 = 1181
18566	CEFBS_HasMVEInt, // MVE_VMINAs32 = 1182
18567	CEFBS_HasMVEInt, // MVE_VMINAs8 = 1183
18568	CEFBS_HasMVEFloat, // MVE_VMINNMAVf16 = 1184
18569	CEFBS_HasMVEFloat, // MVE_VMINNMAVf32 = 1185
18570	CEFBS_HasMVEFloat, // MVE_VMINNMAf16 = 1186
18571	CEFBS_HasMVEFloat, // MVE_VMINNMAf32 = 1187
18572	CEFBS_HasMVEFloat, // MVE_VMINNMVf16 = 1188
18573	CEFBS_HasMVEFloat, // MVE_VMINNMVf32 = 1189
18574	CEFBS_HasMVEFloat, // MVE_VMINNMf16 = 1190
18575	CEFBS_HasMVEFloat, // MVE_VMINNMf32 = 1191
18576	CEFBS_HasMVEInt, // MVE_VMINVs16 = 1192
18577	CEFBS_HasMVEInt, // MVE_VMINVs32 = 1193
18578	CEFBS_HasMVEInt, // MVE_VMINVs8 = 1194
18579	CEFBS_HasMVEInt, // MVE_VMINVu16 = 1195
18580	CEFBS_HasMVEInt, // MVE_VMINVu32 = 1196
18581	CEFBS_HasMVEInt, // MVE_VMINVu8 = 1197
18582	CEFBS_HasMVEInt, // MVE_VMINs16 = 1198
18583	CEFBS_HasMVEInt, // MVE_VMINs32 = 1199
18584	CEFBS_HasMVEInt, // MVE_VMINs8 = 1200
18585	CEFBS_HasMVEInt, // MVE_VMINu16 = 1201
18586	CEFBS_HasMVEInt, // MVE_VMINu32 = 1202
18587	CEFBS_HasMVEInt, // MVE_VMINu8 = 1203
18588	CEFBS_HasMVEInt, // MVE_VMLADAVas16 = 1204
18589	CEFBS_HasMVEInt, // MVE_VMLADAVas32 = 1205
18590	CEFBS_HasMVEInt, // MVE_VMLADAVas8 = 1206
18591	CEFBS_HasMVEInt, // MVE_VMLADAVau16 = 1207
18592	CEFBS_HasMVEInt, // MVE_VMLADAVau32 = 1208
18593	CEFBS_HasMVEInt, // MVE_VMLADAVau8 = 1209
18594	CEFBS_HasMVEInt, // MVE_VMLADAVaxs16 = 1210
18595	CEFBS_HasMVEInt, // MVE_VMLADAVaxs32 = 1211
18596	CEFBS_HasMVEInt, // MVE_VMLADAVaxs8 = 1212
18597	CEFBS_HasMVEInt, // MVE_VMLADAVs16 = 1213
18598	CEFBS_HasMVEInt, // MVE_VMLADAVs32 = 1214
18599	CEFBS_HasMVEInt, // MVE_VMLADAVs8 = 1215
18600	CEFBS_HasMVEInt, // MVE_VMLADAVu16 = 1216
18601	CEFBS_HasMVEInt, // MVE_VMLADAVu32 = 1217
18602	CEFBS_HasMVEInt, // MVE_VMLADAVu8 = 1218
18603	CEFBS_HasMVEInt, // MVE_VMLADAVxs16 = 1219
18604	CEFBS_HasMVEInt, // MVE_VMLADAVxs32 = 1220
18605	CEFBS_HasMVEInt, // MVE_VMLADAVxs8 = 1221
18606	CEFBS_HasMVEInt, // MVE_VMLALDAVas16 = 1222
18607	CEFBS_HasMVEInt, // MVE_VMLALDAVas32 = 1223
18608	CEFBS_HasMVEInt, // MVE_VMLALDAVau16 = 1224
18609	CEFBS_HasMVEInt, // MVE_VMLALDAVau32 = 1225
18610	CEFBS_HasMVEInt, // MVE_VMLALDAVaxs16 = 1226
18611	CEFBS_HasMVEInt, // MVE_VMLALDAVaxs32 = 1227
18612	CEFBS_HasMVEInt, // MVE_VMLALDAVs16 = 1228
18613	CEFBS_HasMVEInt, // MVE_VMLALDAVs32 = 1229
18614	CEFBS_HasMVEInt, // MVE_VMLALDAVu16 = 1230
18615	CEFBS_HasMVEInt, // MVE_VMLALDAVu32 = 1231
18616	CEFBS_HasMVEInt, // MVE_VMLALDAVxs16 = 1232
18617	CEFBS_HasMVEInt, // MVE_VMLALDAVxs32 = 1233
18618	CEFBS_HasMVEInt, // MVE_VMLAS_qr_s16 = 1234
18619	CEFBS_HasMVEInt, // MVE_VMLAS_qr_s32 = 1235
18620	CEFBS_HasMVEInt, // MVE_VMLAS_qr_s8 = 1236
18621	CEFBS_HasMVEInt, // MVE_VMLAS_qr_u16 = 1237
18622	CEFBS_HasMVEInt, // MVE_VMLAS_qr_u32 = 1238
18623	CEFBS_HasMVEInt, // MVE_VMLAS_qr_u8 = 1239
18624	CEFBS_HasMVEInt, // MVE_VMLA_qr_s16 = 1240
18625	CEFBS_HasMVEInt, // MVE_VMLA_qr_s32 = 1241
18626	CEFBS_HasMVEInt, // MVE_VMLA_qr_s8 = 1242
18627	CEFBS_HasMVEInt, // MVE_VMLA_qr_u16 = 1243
18628	CEFBS_HasMVEInt, // MVE_VMLA_qr_u32 = 1244
18629	CEFBS_HasMVEInt, // MVE_VMLA_qr_u8 = 1245
18630	CEFBS_HasMVEInt, // MVE_VMLSDAVas16 = 1246
18631	CEFBS_HasMVEInt, // MVE_VMLSDAVas32 = 1247
18632	CEFBS_HasMVEInt, // MVE_VMLSDAVas8 = 1248
18633	CEFBS_HasMVEInt, // MVE_VMLSDAVaxs16 = 1249
18634	CEFBS_HasMVEInt, // MVE_VMLSDAVaxs32 = 1250
18635	CEFBS_HasMVEInt, // MVE_VMLSDAVaxs8 = 1251
18636	CEFBS_HasMVEInt, // MVE_VMLSDAVs16 = 1252
18637	CEFBS_HasMVEInt, // MVE_VMLSDAVs32 = 1253
18638	CEFBS_HasMVEInt, // MVE_VMLSDAVs8 = 1254
18639	CEFBS_HasMVEInt, // MVE_VMLSDAVxs16 = 1255
18640	CEFBS_HasMVEInt, // MVE_VMLSDAVxs32 = 1256
18641	CEFBS_HasMVEInt, // MVE_VMLSDAVxs8 = 1257
18642	CEFBS_HasMVEInt, // MVE_VMLSLDAVas16 = 1258
18643	CEFBS_HasMVEInt, // MVE_VMLSLDAVas32 = 1259
18644	CEFBS_HasMVEInt, // MVE_VMLSLDAVaxs16 = 1260
18645	CEFBS_HasMVEInt, // MVE_VMLSLDAVaxs32 = 1261
18646	CEFBS_HasMVEInt, // MVE_VMLSLDAVs16 = 1262
18647	CEFBS_HasMVEInt, // MVE_VMLSLDAVs32 = 1263
18648	CEFBS_HasMVEInt, // MVE_VMLSLDAVxs16 = 1264
18649	CEFBS_HasMVEInt, // MVE_VMLSLDAVxs32 = 1265
18650	CEFBS_HasMVEInt, // MVE_VMOVLs16bh = 1266
18651	CEFBS_HasMVEInt, // MVE_VMOVLs16th = 1267
18652	CEFBS_HasMVEInt, // MVE_VMOVLs8bh = 1268
18653	CEFBS_HasMVEInt, // MVE_VMOVLs8th = 1269
18654	CEFBS_HasMVEInt, // MVE_VMOVLu16bh = 1270
18655	CEFBS_HasMVEInt, // MVE_VMOVLu16th = 1271
18656	CEFBS_HasMVEInt, // MVE_VMOVLu8bh = 1272
18657	CEFBS_HasMVEInt, // MVE_VMOVLu8th = 1273
18658	CEFBS_HasMVEInt, // MVE_VMOVNi16bh = 1274
18659	CEFBS_HasMVEInt, // MVE_VMOVNi16th = 1275
18660	CEFBS_HasMVEInt, // MVE_VMOVNi32bh = 1276
18661	CEFBS_HasMVEInt, // MVE_VMOVNi32th = 1277
18662	CEFBS_HasFPRegsV8_1M, // MVE_VMOV_from_lane_32 = 1278
18663	CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_from_lane_s16 = 1279
18664	CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_from_lane_s8 = 1280
18665	CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_from_lane_u16 = 1281
18666	CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_from_lane_u8 = 1282
18667	CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_q_rr = 1283
18668	CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_rr_q = 1284
18669	CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_to_lane_16 = 1285
18670	CEFBS_HasFPRegsV8_1M, // MVE_VMOV_to_lane_32 = 1286
18671	CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_to_lane_8 = 1287
18672	CEFBS_HasMVEInt, // MVE_VMOVimmf32 = 1288
18673	CEFBS_HasMVEInt, // MVE_VMOVimmi16 = 1289
18674	CEFBS_HasMVEInt, // MVE_VMOVimmi32 = 1290
18675	CEFBS_HasMVEInt, // MVE_VMOVimmi64 = 1291
18676	CEFBS_HasMVEInt, // MVE_VMOVimmi8 = 1292
18677	CEFBS_HasMVEInt, // MVE_VMULHs16 = 1293
18678	CEFBS_HasMVEInt, // MVE_VMULHs32 = 1294
18679	CEFBS_HasMVEInt, // MVE_VMULHs8 = 1295
18680	CEFBS_HasMVEInt, // MVE_VMULHu16 = 1296
18681	CEFBS_HasMVEInt, // MVE_VMULHu32 = 1297
18682	CEFBS_HasMVEInt, // MVE_VMULHu8 = 1298
18683	CEFBS_HasMVEInt, // MVE_VMULLBp16 = 1299
18684	CEFBS_HasMVEInt, // MVE_VMULLBp8 = 1300
18685	CEFBS_HasMVEInt, // MVE_VMULLBs16 = 1301
18686	CEFBS_HasMVEInt, // MVE_VMULLBs32 = 1302
18687	CEFBS_HasMVEInt, // MVE_VMULLBs8 = 1303
18688	CEFBS_HasMVEInt, // MVE_VMULLBu16 = 1304
18689	CEFBS_HasMVEInt, // MVE_VMULLBu32 = 1305
18690	CEFBS_HasMVEInt, // MVE_VMULLBu8 = 1306
18691	CEFBS_HasMVEInt, // MVE_VMULLTp16 = 1307
18692	CEFBS_HasMVEInt, // MVE_VMULLTp8 = 1308
18693	CEFBS_HasMVEInt, // MVE_VMULLTs16 = 1309
18694	CEFBS_HasMVEInt, // MVE_VMULLTs32 = 1310
18695	CEFBS_HasMVEInt, // MVE_VMULLTs8 = 1311
18696	CEFBS_HasMVEInt, // MVE_VMULLTu16 = 1312
18697	CEFBS_HasMVEInt, // MVE_VMULLTu32 = 1313
18698	CEFBS_HasMVEInt, // MVE_VMULLTu8 = 1314
18699	CEFBS_HasMVEFloat, // MVE_VMUL_qr_f16 = 1315
18700	CEFBS_HasMVEFloat, // MVE_VMUL_qr_f32 = 1316
18701	CEFBS_HasMVEInt, // MVE_VMUL_qr_i16 = 1317
18702	CEFBS_HasMVEInt, // MVE_VMUL_qr_i32 = 1318
18703	CEFBS_HasMVEInt, // MVE_VMUL_qr_i8 = 1319
18704	CEFBS_HasMVEFloat, // MVE_VMULf16 = 1320
18705	CEFBS_HasMVEFloat, // MVE_VMULf32 = 1321
18706	CEFBS_HasMVEInt, // MVE_VMULi16 = 1322
18707	CEFBS_HasMVEInt, // MVE_VMULi32 = 1323
18708	CEFBS_HasMVEInt, // MVE_VMULi8 = 1324
18709	CEFBS_HasMVEInt, // MVE_VMVN = 1325
18710	CEFBS_HasMVEInt, // MVE_VMVNimmi16 = 1326
18711	CEFBS_HasMVEInt, // MVE_VMVNimmi32 = 1327
18712	CEFBS_HasMVEFloat, // MVE_VNEGf16 = 1328
18713	CEFBS_HasMVEFloat, // MVE_VNEGf32 = 1329
18714	CEFBS_HasMVEInt, // MVE_VNEGs16 = 1330
18715	CEFBS_HasMVEInt, // MVE_VNEGs32 = 1331
18716	CEFBS_HasMVEInt, // MVE_VNEGs8 = 1332
18717	CEFBS_HasMVEInt, // MVE_VORN = 1333
18718	CEFBS_HasMVEInt, // MVE_VORR = 1334
18719	CEFBS_HasMVEInt, // MVE_VORRimmi16 = 1335
18720	CEFBS_HasMVEInt, // MVE_VORRimmi32 = 1336
18721	CEFBS_HasMVEInt, // MVE_VPNOT = 1337
18722	CEFBS_HasMVEInt, // MVE_VPSEL = 1338
18723	CEFBS_HasMVEInt, // MVE_VPST = 1339
18724	CEFBS_HasMVEInt, // MVE_VPTv16i8 = 1340
18725	CEFBS_HasMVEInt, // MVE_VPTv16i8r = 1341
18726	CEFBS_HasMVEInt, // MVE_VPTv16s8 = 1342
18727	CEFBS_HasMVEInt, // MVE_VPTv16s8r = 1343
18728	CEFBS_HasMVEInt, // MVE_VPTv16u8 = 1344
18729	CEFBS_HasMVEInt, // MVE_VPTv16u8r = 1345
18730	CEFBS_HasMVEFloat, // MVE_VPTv4f32 = 1346
18731	CEFBS_HasMVEFloat, // MVE_VPTv4f32r = 1347
18732	CEFBS_HasMVEInt, // MVE_VPTv4i32 = 1348
18733	CEFBS_HasMVEInt, // MVE_VPTv4i32r = 1349
18734	CEFBS_HasMVEInt, // MVE_VPTv4s32 = 1350
18735	CEFBS_HasMVEInt, // MVE_VPTv4s32r = 1351
18736	CEFBS_HasMVEInt, // MVE_VPTv4u32 = 1352
18737	CEFBS_HasMVEInt, // MVE_VPTv4u32r = 1353
18738	CEFBS_HasMVEFloat, // MVE_VPTv8f16 = 1354
18739	CEFBS_HasMVEFloat, // MVE_VPTv8f16r = 1355
18740	CEFBS_HasMVEInt, // MVE_VPTv8i16 = 1356
18741	CEFBS_HasMVEInt, // MVE_VPTv8i16r = 1357
18742	CEFBS_HasMVEInt, // MVE_VPTv8s16 = 1358
18743	CEFBS_HasMVEInt, // MVE_VPTv8s16r = 1359
18744	CEFBS_HasMVEInt, // MVE_VPTv8u16 = 1360
18745	CEFBS_HasMVEInt, // MVE_VPTv8u16r = 1361
18746	CEFBS_HasMVEInt, // MVE_VQABSs16 = 1362
18747	CEFBS_HasMVEInt, // MVE_VQABSs32 = 1363
18748	CEFBS_HasMVEInt, // MVE_VQABSs8 = 1364
18749	CEFBS_HasMVEInt, // MVE_VQADD_qr_s16 = 1365
18750	CEFBS_HasMVEInt, // MVE_VQADD_qr_s32 = 1366
18751	CEFBS_HasMVEInt, // MVE_VQADD_qr_s8 = 1367
18752	CEFBS_HasMVEInt, // MVE_VQADD_qr_u16 = 1368
18753	CEFBS_HasMVEInt, // MVE_VQADD_qr_u32 = 1369
18754	CEFBS_HasMVEInt, // MVE_VQADD_qr_u8 = 1370
18755	CEFBS_HasMVEInt, // MVE_VQADDs16 = 1371
18756	CEFBS_HasMVEInt, // MVE_VQADDs32 = 1372
18757	CEFBS_HasMVEInt, // MVE_VQADDs8 = 1373
18758	CEFBS_HasMVEInt, // MVE_VQADDu16 = 1374
18759	CEFBS_HasMVEInt, // MVE_VQADDu32 = 1375
18760	CEFBS_HasMVEInt, // MVE_VQADDu8 = 1376
18761	CEFBS_HasMVEInt, // MVE_VQDMLADHXs16 = 1377
18762	CEFBS_HasMVEInt, // MVE_VQDMLADHXs32 = 1378
18763	CEFBS_HasMVEInt, // MVE_VQDMLADHXs8 = 1379
18764	CEFBS_HasMVEInt, // MVE_VQDMLADHs16 = 1380
18765	CEFBS_HasMVEInt, // MVE_VQDMLADHs32 = 1381
18766	CEFBS_HasMVEInt, // MVE_VQDMLADHs8 = 1382
18767	CEFBS_HasMVEInt, // MVE_VQDMLAH_qrs16 = 1383
18768	CEFBS_HasMVEInt, // MVE_VQDMLAH_qrs32 = 1384
18769	CEFBS_HasMVEInt, // MVE_VQDMLAH_qrs8 = 1385
18770	CEFBS_HasMVEInt, // MVE_VQDMLASH_qrs16 = 1386
18771	CEFBS_HasMVEInt, // MVE_VQDMLASH_qrs32 = 1387
18772	CEFBS_HasMVEInt, // MVE_VQDMLASH_qrs8 = 1388
18773	CEFBS_HasMVEInt, // MVE_VQDMLSDHXs16 = 1389
18774	CEFBS_HasMVEInt, // MVE_VQDMLSDHXs32 = 1390
18775	CEFBS_HasMVEInt, // MVE_VQDMLSDHXs8 = 1391
18776	CEFBS_HasMVEInt, // MVE_VQDMLSDHs16 = 1392
18777	CEFBS_HasMVEInt, // MVE_VQDMLSDHs32 = 1393
18778	CEFBS_HasMVEInt, // MVE_VQDMLSDHs8 = 1394
18779	CEFBS_HasMVEInt, // MVE_VQDMULH_qr_s16 = 1395
18780	CEFBS_HasMVEInt, // MVE_VQDMULH_qr_s32 = 1396
18781	CEFBS_HasMVEInt, // MVE_VQDMULH_qr_s8 = 1397
18782	CEFBS_HasMVEInt, // MVE_VQDMULHi16 = 1398
18783	CEFBS_HasMVEInt, // MVE_VQDMULHi32 = 1399
18784	CEFBS_HasMVEInt, // MVE_VQDMULHi8 = 1400
18785	CEFBS_HasMVEInt, // MVE_VQDMULL_qr_s16bh = 1401
18786	CEFBS_HasMVEInt, // MVE_VQDMULL_qr_s16th = 1402
18787	CEFBS_HasMVEInt, // MVE_VQDMULL_qr_s32bh = 1403
18788	CEFBS_HasMVEInt, // MVE_VQDMULL_qr_s32th = 1404
18789	CEFBS_HasMVEInt, // MVE_VQDMULLs16bh = 1405
18790	CEFBS_HasMVEInt, // MVE_VQDMULLs16th = 1406
18791	CEFBS_HasMVEInt, // MVE_VQDMULLs32bh = 1407
18792	CEFBS_HasMVEInt, // MVE_VQDMULLs32th = 1408
18793	CEFBS_HasMVEInt, // MVE_VQMOVNs16bh = 1409
18794	CEFBS_HasMVEInt, // MVE_VQMOVNs16th = 1410
18795	CEFBS_HasMVEInt, // MVE_VQMOVNs32bh = 1411
18796	CEFBS_HasMVEInt, // MVE_VQMOVNs32th = 1412
18797	CEFBS_HasMVEInt, // MVE_VQMOVNu16bh = 1413
18798	CEFBS_HasMVEInt, // MVE_VQMOVNu16th = 1414
18799	CEFBS_HasMVEInt, // MVE_VQMOVNu32bh = 1415
18800	CEFBS_HasMVEInt, // MVE_VQMOVNu32th = 1416
18801	CEFBS_HasMVEInt, // MVE_VQMOVUNs16bh = 1417
18802	CEFBS_HasMVEInt, // MVE_VQMOVUNs16th = 1418
18803	CEFBS_HasMVEInt, // MVE_VQMOVUNs32bh = 1419
18804	CEFBS_HasMVEInt, // MVE_VQMOVUNs32th = 1420
18805	CEFBS_HasMVEInt, // MVE_VQNEGs16 = 1421
18806	CEFBS_HasMVEInt, // MVE_VQNEGs32 = 1422
18807	CEFBS_HasMVEInt, // MVE_VQNEGs8 = 1423
18808	CEFBS_HasMVEInt, // MVE_VQRDMLADHXs16 = 1424
18809	CEFBS_HasMVEInt, // MVE_VQRDMLADHXs32 = 1425
18810	CEFBS_HasMVEInt, // MVE_VQRDMLADHXs8 = 1426
18811	CEFBS_HasMVEInt, // MVE_VQRDMLADHs16 = 1427
18812	CEFBS_HasMVEInt, // MVE_VQRDMLADHs32 = 1428
18813	CEFBS_HasMVEInt, // MVE_VQRDMLADHs8 = 1429
18814	CEFBS_HasMVEInt, // MVE_VQRDMLAH_qrs16 = 1430
18815	CEFBS_HasMVEInt, // MVE_VQRDMLAH_qrs32 = 1431
18816	CEFBS_HasMVEInt, // MVE_VQRDMLAH_qrs8 = 1432
18817	CEFBS_HasMVEInt, // MVE_VQRDMLASH_qrs16 = 1433
18818	CEFBS_HasMVEInt, // MVE_VQRDMLASH_qrs32 = 1434
18819	CEFBS_HasMVEInt, // MVE_VQRDMLASH_qrs8 = 1435
18820	CEFBS_HasMVEInt, // MVE_VQRDMLSDHXs16 = 1436
18821	CEFBS_HasMVEInt, // MVE_VQRDMLSDHXs32 = 1437
18822	CEFBS_HasMVEInt, // MVE_VQRDMLSDHXs8 = 1438
18823	CEFBS_HasMVEInt, // MVE_VQRDMLSDHs16 = 1439
18824	CEFBS_HasMVEInt, // MVE_VQRDMLSDHs32 = 1440
18825	CEFBS_HasMVEInt, // MVE_VQRDMLSDHs8 = 1441
18826	CEFBS_HasMVEInt, // MVE_VQRDMULH_qr_s16 = 1442
18827	CEFBS_HasMVEInt, // MVE_VQRDMULH_qr_s32 = 1443
18828	CEFBS_HasMVEInt, // MVE_VQRDMULH_qr_s8 = 1444
18829	CEFBS_HasMVEInt, // MVE_VQRDMULHi16 = 1445
18830	CEFBS_HasMVEInt, // MVE_VQRDMULHi32 = 1446
18831	CEFBS_HasMVEInt, // MVE_VQRDMULHi8 = 1447
18832	CEFBS_HasMVEInt, // MVE_VQRSHL_by_vecs16 = 1448
18833	CEFBS_HasMVEInt, // MVE_VQRSHL_by_vecs32 = 1449
18834	CEFBS_HasMVEInt, // MVE_VQRSHL_by_vecs8 = 1450
18835	CEFBS_HasMVEInt, // MVE_VQRSHL_by_vecu16 = 1451
18836	CEFBS_HasMVEInt, // MVE_VQRSHL_by_vecu32 = 1452
18837	CEFBS_HasMVEInt, // MVE_VQRSHL_by_vecu8 = 1453
18838	CEFBS_HasMVEInt, // MVE_VQRSHL_qrs16 = 1454
18839	CEFBS_HasMVEInt, // MVE_VQRSHL_qrs32 = 1455
18840	CEFBS_HasMVEInt, // MVE_VQRSHL_qrs8 = 1456
18841	CEFBS_HasMVEInt, // MVE_VQRSHL_qru16 = 1457
18842	CEFBS_HasMVEInt, // MVE_VQRSHL_qru32 = 1458
18843	CEFBS_HasMVEInt, // MVE_VQRSHL_qru8 = 1459
18844	CEFBS_HasMVEInt, // MVE_VQRSHRNbhs16 = 1460
18845	CEFBS_HasMVEInt, // MVE_VQRSHRNbhs32 = 1461
18846	CEFBS_HasMVEInt, // MVE_VQRSHRNbhu16 = 1462
18847	CEFBS_HasMVEInt, // MVE_VQRSHRNbhu32 = 1463
18848	CEFBS_HasMVEInt, // MVE_VQRSHRNths16 = 1464
18849	CEFBS_HasMVEInt, // MVE_VQRSHRNths32 = 1465
18850	CEFBS_HasMVEInt, // MVE_VQRSHRNthu16 = 1466
18851	CEFBS_HasMVEInt, // MVE_VQRSHRNthu32 = 1467
18852	CEFBS_HasMVEInt, // MVE_VQRSHRUNs16bh = 1468
18853	CEFBS_HasMVEInt, // MVE_VQRSHRUNs16th = 1469
18854	CEFBS_HasMVEInt, // MVE_VQRSHRUNs32bh = 1470
18855	CEFBS_HasMVEInt, // MVE_VQRSHRUNs32th = 1471
18856	CEFBS_HasMVEInt, // MVE_VQSHLU_imms16 = 1472
18857	CEFBS_HasMVEInt, // MVE_VQSHLU_imms32 = 1473
18858	CEFBS_HasMVEInt, // MVE_VQSHLU_imms8 = 1474
18859	CEFBS_HasMVEInt, // MVE_VQSHL_by_vecs16 = 1475
18860	CEFBS_HasMVEInt, // MVE_VQSHL_by_vecs32 = 1476
18861	CEFBS_HasMVEInt, // MVE_VQSHL_by_vecs8 = 1477
18862	CEFBS_HasMVEInt, // MVE_VQSHL_by_vecu16 = 1478
18863	CEFBS_HasMVEInt, // MVE_VQSHL_by_vecu32 = 1479
18864	CEFBS_HasMVEInt, // MVE_VQSHL_by_vecu8 = 1480
18865	CEFBS_HasMVEInt, // MVE_VQSHL_qrs16 = 1481
18866	CEFBS_HasMVEInt, // MVE_VQSHL_qrs32 = 1482
18867	CEFBS_HasMVEInt, // MVE_VQSHL_qrs8 = 1483
18868	CEFBS_HasMVEInt, // MVE_VQSHL_qru16 = 1484
18869	CEFBS_HasMVEInt, // MVE_VQSHL_qru32 = 1485
18870	CEFBS_HasMVEInt, // MVE_VQSHL_qru8 = 1486
18871	CEFBS_HasMVEInt, // MVE_VQSHLimms16 = 1487
18872	CEFBS_HasMVEInt, // MVE_VQSHLimms32 = 1488
18873	CEFBS_HasMVEInt, // MVE_VQSHLimms8 = 1489
18874	CEFBS_HasMVEInt, // MVE_VQSHLimmu16 = 1490
18875	CEFBS_HasMVEInt, // MVE_VQSHLimmu32 = 1491
18876	CEFBS_HasMVEInt, // MVE_VQSHLimmu8 = 1492
18877	CEFBS_HasMVEInt, // MVE_VQSHRNbhs16 = 1493
18878	CEFBS_HasMVEInt, // MVE_VQSHRNbhs32 = 1494
18879	CEFBS_HasMVEInt, // MVE_VQSHRNbhu16 = 1495
18880	CEFBS_HasMVEInt, // MVE_VQSHRNbhu32 = 1496
18881	CEFBS_HasMVEInt, // MVE_VQSHRNths16 = 1497
18882	CEFBS_HasMVEInt, // MVE_VQSHRNths32 = 1498
18883	CEFBS_HasMVEInt, // MVE_VQSHRNthu16 = 1499
18884	CEFBS_HasMVEInt, // MVE_VQSHRNthu32 = 1500
18885	CEFBS_HasMVEInt, // MVE_VQSHRUNs16bh = 1501
18886	CEFBS_HasMVEInt, // MVE_VQSHRUNs16th = 1502
18887	CEFBS_HasMVEInt, // MVE_VQSHRUNs32bh = 1503
18888	CEFBS_HasMVEInt, // MVE_VQSHRUNs32th = 1504
18889	CEFBS_HasMVEInt, // MVE_VQSUB_qr_s16 = 1505
18890	CEFBS_HasMVEInt, // MVE_VQSUB_qr_s32 = 1506
18891	CEFBS_HasMVEInt, // MVE_VQSUB_qr_s8 = 1507
18892	CEFBS_HasMVEInt, // MVE_VQSUB_qr_u16 = 1508
18893	CEFBS_HasMVEInt, // MVE_VQSUB_qr_u32 = 1509
18894	CEFBS_HasMVEInt, // MVE_VQSUB_qr_u8 = 1510
18895	CEFBS_HasMVEInt, // MVE_VQSUBs16 = 1511
18896	CEFBS_HasMVEInt, // MVE_VQSUBs32 = 1512
18897	CEFBS_HasMVEInt, // MVE_VQSUBs8 = 1513
18898	CEFBS_HasMVEInt, // MVE_VQSUBu16 = 1514
18899	CEFBS_HasMVEInt, // MVE_VQSUBu32 = 1515
18900	CEFBS_HasMVEInt, // MVE_VQSUBu8 = 1516
18901	CEFBS_HasMVEInt, // MVE_VREV16_8 = 1517
18902	CEFBS_HasMVEInt, // MVE_VREV32_16 = 1518
18903	CEFBS_HasMVEInt, // MVE_VREV32_8 = 1519
18904	CEFBS_HasMVEInt, // MVE_VREV64_16 = 1520
18905	CEFBS_HasMVEInt, // MVE_VREV64_32 = 1521
18906	CEFBS_HasMVEInt, // MVE_VREV64_8 = 1522
18907	CEFBS_HasMVEInt, // MVE_VRHADDs16 = 1523
18908	CEFBS_HasMVEInt, // MVE_VRHADDs32 = 1524
18909	CEFBS_HasMVEInt, // MVE_VRHADDs8 = 1525
18910	CEFBS_HasMVEInt, // MVE_VRHADDu16 = 1526
18911	CEFBS_HasMVEInt, // MVE_VRHADDu32 = 1527
18912	CEFBS_HasMVEInt, // MVE_VRHADDu8 = 1528
18913	CEFBS_HasMVEFloat, // MVE_VRINTf16A = 1529
18914	CEFBS_HasMVEFloat, // MVE_VRINTf16M = 1530
18915	CEFBS_HasMVEFloat, // MVE_VRINTf16N = 1531
18916	CEFBS_HasMVEFloat, // MVE_VRINTf16P = 1532
18917	CEFBS_HasMVEFloat, // MVE_VRINTf16X = 1533
18918	CEFBS_HasMVEFloat, // MVE_VRINTf16Z = 1534
18919	CEFBS_HasMVEFloat, // MVE_VRINTf32A = 1535
18920	CEFBS_HasMVEFloat, // MVE_VRINTf32M = 1536
18921	CEFBS_HasMVEFloat, // MVE_VRINTf32N = 1537
18922	CEFBS_HasMVEFloat, // MVE_VRINTf32P = 1538
18923	CEFBS_HasMVEFloat, // MVE_VRINTf32X = 1539
18924	CEFBS_HasMVEFloat, // MVE_VRINTf32Z = 1540
18925	CEFBS_HasMVEInt, // MVE_VRMLALDAVHas32 = 1541
18926	CEFBS_HasMVEInt, // MVE_VRMLALDAVHau32 = 1542
18927	CEFBS_HasMVEInt, // MVE_VRMLALDAVHaxs32 = 1543
18928	CEFBS_HasMVEInt, // MVE_VRMLALDAVHs32 = 1544
18929	CEFBS_HasMVEInt, // MVE_VRMLALDAVHu32 = 1545
18930	CEFBS_HasMVEInt, // MVE_VRMLALDAVHxs32 = 1546
18931	CEFBS_HasMVEInt, // MVE_VRMLSLDAVHas32 = 1547
18932	CEFBS_HasMVEInt, // MVE_VRMLSLDAVHaxs32 = 1548
18933	CEFBS_HasMVEInt, // MVE_VRMLSLDAVHs32 = 1549
18934	CEFBS_HasMVEInt, // MVE_VRMLSLDAVHxs32 = 1550
18935	CEFBS_HasMVEInt, // MVE_VRMULHs16 = 1551
18936	CEFBS_HasMVEInt, // MVE_VRMULHs32 = 1552
18937	CEFBS_HasMVEInt, // MVE_VRMULHs8 = 1553
18938	CEFBS_HasMVEInt, // MVE_VRMULHu16 = 1554
18939	CEFBS_HasMVEInt, // MVE_VRMULHu32 = 1555
18940	CEFBS_HasMVEInt, // MVE_VRMULHu8 = 1556
18941	CEFBS_HasMVEInt, // MVE_VRSHL_by_vecs16 = 1557
18942	CEFBS_HasMVEInt, // MVE_VRSHL_by_vecs32 = 1558
18943	CEFBS_HasMVEInt, // MVE_VRSHL_by_vecs8 = 1559
18944	CEFBS_HasMVEInt, // MVE_VRSHL_by_vecu16 = 1560
18945	CEFBS_HasMVEInt, // MVE_VRSHL_by_vecu32 = 1561
18946	CEFBS_HasMVEInt, // MVE_VRSHL_by_vecu8 = 1562
18947	CEFBS_HasMVEInt, // MVE_VRSHL_qrs16 = 1563
18948	CEFBS_HasMVEInt, // MVE_VRSHL_qrs32 = 1564
18949	CEFBS_HasMVEInt, // MVE_VRSHL_qrs8 = 1565
18950	CEFBS_HasMVEInt, // MVE_VRSHL_qru16 = 1566
18951	CEFBS_HasMVEInt, // MVE_VRSHL_qru32 = 1567
18952	CEFBS_HasMVEInt, // MVE_VRSHL_qru8 = 1568
18953	CEFBS_HasMVEInt, // MVE_VRSHRNi16bh = 1569
18954	CEFBS_HasMVEInt, // MVE_VRSHRNi16th = 1570
18955	CEFBS_HasMVEInt, // MVE_VRSHRNi32bh = 1571
18956	CEFBS_HasMVEInt, // MVE_VRSHRNi32th = 1572
18957	CEFBS_HasMVEInt, // MVE_VRSHR_imms16 = 1573
18958	CEFBS_HasMVEInt, // MVE_VRSHR_imms32 = 1574
18959	CEFBS_HasMVEInt, // MVE_VRSHR_imms8 = 1575
18960	CEFBS_HasMVEInt, // MVE_VRSHR_immu16 = 1576
18961	CEFBS_HasMVEInt, // MVE_VRSHR_immu32 = 1577
18962	CEFBS_HasMVEInt, // MVE_VRSHR_immu8 = 1578
18963	CEFBS_HasMVEInt, // MVE_VSBC = 1579
18964	CEFBS_HasMVEInt, // MVE_VSBCI = 1580
18965	CEFBS_HasMVEInt, // MVE_VSHLC = 1581
18966	CEFBS_HasMVEInt, // MVE_VSHLL_imms16bh = 1582
18967	CEFBS_HasMVEInt, // MVE_VSHLL_imms16th = 1583
18968	CEFBS_HasMVEInt, // MVE_VSHLL_imms8bh = 1584
18969	CEFBS_HasMVEInt, // MVE_VSHLL_imms8th = 1585
18970	CEFBS_HasMVEInt, // MVE_VSHLL_immu16bh = 1586
18971	CEFBS_HasMVEInt, // MVE_VSHLL_immu16th = 1587
18972	CEFBS_HasMVEInt, // MVE_VSHLL_immu8bh = 1588
18973	CEFBS_HasMVEInt, // MVE_VSHLL_immu8th = 1589
18974	CEFBS_HasMVEInt, // MVE_VSHLL_lws16bh = 1590
18975	CEFBS_HasMVEInt, // MVE_VSHLL_lws16th = 1591
18976	CEFBS_HasMVEInt, // MVE_VSHLL_lws8bh = 1592
18977	CEFBS_HasMVEInt, // MVE_VSHLL_lws8th = 1593
18978	CEFBS_HasMVEInt, // MVE_VSHLL_lwu16bh = 1594
18979	CEFBS_HasMVEInt, // MVE_VSHLL_lwu16th = 1595
18980	CEFBS_HasMVEInt, // MVE_VSHLL_lwu8bh = 1596
18981	CEFBS_HasMVEInt, // MVE_VSHLL_lwu8th = 1597
18982	CEFBS_HasMVEInt, // MVE_VSHL_by_vecs16 = 1598
18983	CEFBS_HasMVEInt, // MVE_VSHL_by_vecs32 = 1599
18984	CEFBS_HasMVEInt, // MVE_VSHL_by_vecs8 = 1600
18985	CEFBS_HasMVEInt, // MVE_VSHL_by_vecu16 = 1601
18986	CEFBS_HasMVEInt, // MVE_VSHL_by_vecu32 = 1602
18987	CEFBS_HasMVEInt, // MVE_VSHL_by_vecu8 = 1603
18988	CEFBS_HasMVEInt, // MVE_VSHL_immi16 = 1604
18989	CEFBS_HasMVEInt, // MVE_VSHL_immi32 = 1605
18990	CEFBS_HasMVEInt, // MVE_VSHL_immi8 = 1606
18991	CEFBS_HasMVEInt, // MVE_VSHL_qrs16 = 1607
18992	CEFBS_HasMVEInt, // MVE_VSHL_qrs32 = 1608
18993	CEFBS_HasMVEInt, // MVE_VSHL_qrs8 = 1609
18994	CEFBS_HasMVEInt, // MVE_VSHL_qru16 = 1610
18995	CEFBS_HasMVEInt, // MVE_VSHL_qru32 = 1611
18996	CEFBS_HasMVEInt, // MVE_VSHL_qru8 = 1612
18997	CEFBS_HasMVEInt, // MVE_VSHRNi16bh = 1613
18998	CEFBS_HasMVEInt, // MVE_VSHRNi16th = 1614
18999	CEFBS_HasMVEInt, // MVE_VSHRNi32bh = 1615
19000	CEFBS_HasMVEInt, // MVE_VSHRNi32th = 1616
19001	CEFBS_HasMVEInt, // MVE_VSHR_imms16 = 1617
19002	CEFBS_HasMVEInt, // MVE_VSHR_imms32 = 1618
19003	CEFBS_HasMVEInt, // MVE_VSHR_imms8 = 1619
19004	CEFBS_HasMVEInt, // MVE_VSHR_immu16 = 1620
19005	CEFBS_HasMVEInt, // MVE_VSHR_immu32 = 1621
19006	CEFBS_HasMVEInt, // MVE_VSHR_immu8 = 1622
19007	CEFBS_HasMVEInt, // MVE_VSLIimm16 = 1623
19008	CEFBS_HasMVEInt, // MVE_VSLIimm32 = 1624
19009	CEFBS_HasMVEInt, // MVE_VSLIimm8 = 1625
19010	CEFBS_HasMVEInt, // MVE_VSRIimm16 = 1626
19011	CEFBS_HasMVEInt, // MVE_VSRIimm32 = 1627
19012	CEFBS_HasMVEInt, // MVE_VSRIimm8 = 1628
19013	CEFBS_HasMVEInt, // MVE_VST20_16 = 1629
19014	CEFBS_HasMVEInt, // MVE_VST20_16_wb = 1630
19015	CEFBS_HasMVEInt, // MVE_VST20_32 = 1631
19016	CEFBS_HasMVEInt, // MVE_VST20_32_wb = 1632
19017	CEFBS_HasMVEInt, // MVE_VST20_8 = 1633
19018	CEFBS_HasMVEInt, // MVE_VST20_8_wb = 1634
19019	CEFBS_HasMVEInt, // MVE_VST21_16 = 1635
19020	CEFBS_HasMVEInt, // MVE_VST21_16_wb = 1636
19021	CEFBS_HasMVEInt, // MVE_VST21_32 = 1637
19022	CEFBS_HasMVEInt, // MVE_VST21_32_wb = 1638
19023	CEFBS_HasMVEInt, // MVE_VST21_8 = 1639
19024	CEFBS_HasMVEInt, // MVE_VST21_8_wb = 1640
19025	CEFBS_HasMVEInt, // MVE_VST40_16 = 1641
19026	CEFBS_HasMVEInt, // MVE_VST40_16_wb = 1642
19027	CEFBS_HasMVEInt, // MVE_VST40_32 = 1643
19028	CEFBS_HasMVEInt, // MVE_VST40_32_wb = 1644
19029	CEFBS_HasMVEInt, // MVE_VST40_8 = 1645
19030	CEFBS_HasMVEInt, // MVE_VST40_8_wb = 1646
19031	CEFBS_HasMVEInt, // MVE_VST41_16 = 1647
19032	CEFBS_HasMVEInt, // MVE_VST41_16_wb = 1648
19033	CEFBS_HasMVEInt, // MVE_VST41_32 = 1649
19034	CEFBS_HasMVEInt, // MVE_VST41_32_wb = 1650
19035	CEFBS_HasMVEInt, // MVE_VST41_8 = 1651
19036	CEFBS_HasMVEInt, // MVE_VST41_8_wb = 1652
19037	CEFBS_HasMVEInt, // MVE_VST42_16 = 1653
19038	CEFBS_HasMVEInt, // MVE_VST42_16_wb = 1654
19039	CEFBS_HasMVEInt, // MVE_VST42_32 = 1655
19040	CEFBS_HasMVEInt, // MVE_VST42_32_wb = 1656
19041	CEFBS_HasMVEInt, // MVE_VST42_8 = 1657
19042	CEFBS_HasMVEInt, // MVE_VST42_8_wb = 1658
19043	CEFBS_HasMVEInt, // MVE_VST43_16 = 1659
19044	CEFBS_HasMVEInt, // MVE_VST43_16_wb = 1660
19045	CEFBS_HasMVEInt, // MVE_VST43_32 = 1661
19046	CEFBS_HasMVEInt, // MVE_VST43_32_wb = 1662
19047	CEFBS_HasMVEInt, // MVE_VST43_8 = 1663
19048	CEFBS_HasMVEInt, // MVE_VST43_8_wb = 1664
19049	CEFBS_HasMVEInt, // MVE_VSTRB16 = 1665
19050	CEFBS_HasMVEInt, // MVE_VSTRB16_post = 1666
19051	CEFBS_HasMVEInt, // MVE_VSTRB16_pre = 1667
19052	CEFBS_HasMVEInt, // MVE_VSTRB16_rq = 1668
19053	CEFBS_HasMVEInt, // MVE_VSTRB32 = 1669
19054	CEFBS_HasMVEInt, // MVE_VSTRB32_post = 1670
19055	CEFBS_HasMVEInt, // MVE_VSTRB32_pre = 1671
19056	CEFBS_HasMVEInt, // MVE_VSTRB32_rq = 1672
19057	CEFBS_HasMVEInt, // MVE_VSTRB8_rq = 1673
19058	CEFBS_HasMVEInt, // MVE_VSTRBU8 = 1674
19059	CEFBS_HasMVEInt, // MVE_VSTRBU8_post = 1675
19060	CEFBS_HasMVEInt, // MVE_VSTRBU8_pre = 1676
19061	CEFBS_HasMVEInt, // MVE_VSTRD64_qi = 1677
19062	CEFBS_HasMVEInt, // MVE_VSTRD64_qi_pre = 1678
19063	CEFBS_HasMVEInt, // MVE_VSTRD64_rq = 1679
19064	CEFBS_HasMVEInt, // MVE_VSTRD64_rq_u = 1680
19065	CEFBS_HasMVEInt, // MVE_VSTRH16_rq = 1681
19066	CEFBS_HasMVEInt, // MVE_VSTRH16_rq_u = 1682
19067	CEFBS_HasMVEInt, // MVE_VSTRH32 = 1683
19068	CEFBS_HasMVEInt, // MVE_VSTRH32_post = 1684
19069	CEFBS_HasMVEInt, // MVE_VSTRH32_pre = 1685
19070	CEFBS_HasMVEInt, // MVE_VSTRH32_rq = 1686
19071	CEFBS_HasMVEInt, // MVE_VSTRH32_rq_u = 1687
19072	CEFBS_HasMVEInt, // MVE_VSTRHU16 = 1688
19073	CEFBS_HasMVEInt, // MVE_VSTRHU16_post = 1689
19074	CEFBS_HasMVEInt, // MVE_VSTRHU16_pre = 1690
19075	CEFBS_HasMVEInt, // MVE_VSTRW32_qi = 1691
19076	CEFBS_HasMVEInt, // MVE_VSTRW32_qi_pre = 1692
19077	CEFBS_HasMVEInt, // MVE_VSTRW32_rq = 1693
19078	CEFBS_HasMVEInt, // MVE_VSTRW32_rq_u = 1694
19079	CEFBS_HasMVEInt, // MVE_VSTRWU32 = 1695
19080	CEFBS_HasMVEInt, // MVE_VSTRWU32_post = 1696
19081	CEFBS_HasMVEInt, // MVE_VSTRWU32_pre = 1697
19082	CEFBS_HasMVEFloat, // MVE_VSUB_qr_f16 = 1698
19083	CEFBS_HasMVEFloat, // MVE_VSUB_qr_f32 = 1699
19084	CEFBS_HasMVEInt, // MVE_VSUB_qr_i16 = 1700
19085	CEFBS_HasMVEInt, // MVE_VSUB_qr_i32 = 1701
19086	CEFBS_HasMVEInt, // MVE_VSUB_qr_i8 = 1702
19087	CEFBS_HasMVEFloat, // MVE_VSUBf16 = 1703
19088	CEFBS_HasMVEFloat, // MVE_VSUBf32 = 1704
19089	CEFBS_HasMVEInt, // MVE_VSUBi16 = 1705
19090	CEFBS_HasMVEInt, // MVE_VSUBi32 = 1706
19091	CEFBS_HasMVEInt, // MVE_VSUBi8 = 1707
19092	CEFBS_HasMVEInt, // MVE_WLSTP_16 = 1708
19093	CEFBS_HasMVEInt, // MVE_WLSTP_32 = 1709
19094	CEFBS_HasMVEInt, // MVE_WLSTP_64 = 1710
19095	CEFBS_HasMVEInt, // MVE_WLSTP_8 = 1711
19096	CEFBS_IsARM, // MVNi = 1712
19097	CEFBS_IsARM, // MVNr = 1713
19098	CEFBS_IsARM, // MVNsi = 1714
19099	CEFBS_IsARM, // MVNsr = 1715
19100	CEFBS_HasV8_HasNEON, // NEON_VMAXNMNDf = 1716
19101	CEFBS_HasV8_HasNEON_HasFullFP16, // NEON_VMAXNMNDh = 1717
19102	CEFBS_HasV8_HasNEON, // NEON_VMAXNMNQf = 1718
19103	CEFBS_HasV8_HasNEON_HasFullFP16, // NEON_VMAXNMNQh = 1719
19104	CEFBS_HasV8_HasNEON, // NEON_VMINNMNDf = 1720
19105	CEFBS_HasV8_HasNEON_HasFullFP16, // NEON_VMINNMNDh = 1721
19106	CEFBS_HasV8_HasNEON, // NEON_VMINNMNQf = 1722
19107	CEFBS_HasV8_HasNEON_HasFullFP16, // NEON_VMINNMNQh = 1723
19108	CEFBS_IsARM, // ORRri = 1724
19109	CEFBS_IsARM, // ORRrr = 1725
19110	CEFBS_IsARM, // ORRrsi = 1726
19111	CEFBS_IsARM, // ORRrsr = 1727
19112	CEFBS_IsARM_HasV6, // PKHBT = 1728
19113	CEFBS_IsARM_HasV6, // PKHTB = 1729
19114	CEFBS_IsARM_HasV7_HasMP, // PLDWi12 = 1730
19115	CEFBS_IsARM_HasV7_HasMP, // PLDWrs = 1731
19116	CEFBS_IsARM, // PLDi12 = 1732
19117	CEFBS_IsARM, // PLDrs = 1733
19118	CEFBS_IsARM_HasV7, // PLIi12 = 1734
19119	CEFBS_IsARM_HasV7, // PLIrs = 1735
19120	CEFBS_IsARM, // QADD = 1736
19121	CEFBS_IsARM, // QADD16 = 1737
19122	CEFBS_IsARM, // QADD8 = 1738
19123	CEFBS_IsARM, // QASX = 1739
19124	CEFBS_IsARM, // QDADD = 1740
19125	CEFBS_IsARM, // QDSUB = 1741
19126	CEFBS_IsARM, // QSAX = 1742
19127	CEFBS_IsARM, // QSUB = 1743
19128	CEFBS_IsARM, // QSUB16 = 1744
19129	CEFBS_IsARM, // QSUB8 = 1745
19130	CEFBS_IsARM_HasV6T2, // RBIT = 1746
19131	CEFBS_IsARM_HasV6, // REV = 1747
19132	CEFBS_IsARM_HasV6, // REV16 = 1748
19133	CEFBS_IsARM_HasV6, // REVSH = 1749
19134	CEFBS_IsARM, // RFEDA = 1750
19135	CEFBS_IsARM, // RFEDA_UPD = 1751
19136	CEFBS_IsARM, // RFEDB = 1752
19137	CEFBS_IsARM, // RFEDB_UPD = 1753
19138	CEFBS_IsARM, // RFEIA = 1754
19139	CEFBS_IsARM, // RFEIA_UPD = 1755
19140	CEFBS_IsARM, // RFEIB = 1756
19141	CEFBS_IsARM, // RFEIB_UPD = 1757
19142	CEFBS_IsARM, // RSBri = 1758
19143	CEFBS_IsARM, // RSBrr = 1759
19144	CEFBS_IsARM, // RSBrsi = 1760
19145	CEFBS_IsARM, // RSBrsr = 1761
19146	CEFBS_IsARM, // RSCri = 1762
19147	CEFBS_IsARM, // RSCrr = 1763
19148	CEFBS_IsARM, // RSCrsi = 1764
19149	CEFBS_IsARM, // RSCrsr = 1765
19150	CEFBS_IsARM, // SADD16 = 1766
19151	CEFBS_IsARM, // SADD8 = 1767
19152	CEFBS_IsARM, // SASX = 1768
19153	CEFBS_IsARM_HasSB, // SB = 1769
19154	CEFBS_IsARM, // SBCri = 1770
19155	CEFBS_IsARM, // SBCrr = 1771
19156	CEFBS_IsARM, // SBCrsi = 1772
19157	CEFBS_IsARM, // SBCrsr = 1773
19158	CEFBS_IsARM_HasV6T2, // SBFX = 1774
19159	CEFBS_IsARM_HasDivideInARM, // SDIV = 1775
19160	CEFBS_IsARM_HasV6, // SEL = 1776
19161	CEFBS_IsARM, // SETEND = 1777
19162	CEFBS_IsARM_HasV8_HasV8_1a, // SETPAN = 1778
19163	CEFBS_HasV8_HasCrypto, // SHA1C = 1779
19164	CEFBS_HasV8_HasCrypto, // SHA1H = 1780
19165	CEFBS_HasV8_HasCrypto, // SHA1M = 1781
19166	CEFBS_HasV8_HasCrypto, // SHA1P = 1782
19167	CEFBS_HasV8_HasCrypto, // SHA1SU0 = 1783
19168	CEFBS_HasV8_HasCrypto, // SHA1SU1 = 1784
19169	CEFBS_HasV8_HasCrypto, // SHA256H = 1785
19170	CEFBS_HasV8_HasCrypto, // SHA256H2 = 1786
19171	CEFBS_HasV8_HasCrypto, // SHA256SU0 = 1787
19172	CEFBS_HasV8_HasCrypto, // SHA256SU1 = 1788
19173	CEFBS_IsARM, // SHADD16 = 1789
19174	CEFBS_IsARM, // SHADD8 = 1790
19175	CEFBS_IsARM, // SHASX = 1791
19176	CEFBS_IsARM, // SHSAX = 1792
19177	CEFBS_IsARM, // SHSUB16 = 1793
19178	CEFBS_IsARM, // SHSUB8 = 1794
19179	CEFBS_IsARM_HasTrustZone, // SMC = 1795
19180	CEFBS_IsARM_HasV5TE, // SMLABB = 1796
19181	CEFBS_IsARM_HasV5TE, // SMLABT = 1797
19182	CEFBS_IsARM_HasV6, // SMLAD = 1798
19183	CEFBS_IsARM_HasV6, // SMLADX = 1799
19184	CEFBS_IsARM_HasV6, // SMLAL = 1800
19185	CEFBS_IsARM_HasV5TE, // SMLALBB = 1801
19186	CEFBS_IsARM_HasV5TE, // SMLALBT = 1802
19187	CEFBS_IsARM_HasV6, // SMLALD = 1803
19188	CEFBS_IsARM_HasV6, // SMLALDX = 1804
19189	CEFBS_IsARM_HasV5TE, // SMLALTB = 1805
19190	CEFBS_IsARM_HasV5TE, // SMLALTT = 1806
19191	CEFBS_IsARM_HasV5TE, // SMLATB = 1807
19192	CEFBS_IsARM_HasV5TE, // SMLATT = 1808
19193	CEFBS_IsARM_HasV5TE, // SMLAWB = 1809
19194	CEFBS_IsARM_HasV5TE, // SMLAWT = 1810
19195	CEFBS_IsARM_HasV6, // SMLSD = 1811
19196	CEFBS_IsARM_HasV6, // SMLSDX = 1812
19197	CEFBS_IsARM_HasV6, // SMLSLD = 1813
19198	CEFBS_IsARM_HasV6, // SMLSLDX = 1814
19199	CEFBS_IsARM_HasV6, // SMMLA = 1815
19200	CEFBS_IsARM_HasV6, // SMMLAR = 1816
19201	CEFBS_IsARM_HasV6, // SMMLS = 1817
19202	CEFBS_IsARM_HasV6, // SMMLSR = 1818
19203	CEFBS_IsARM_HasV6, // SMMUL = 1819
19204	CEFBS_IsARM_HasV6, // SMMULR = 1820
19205	CEFBS_IsARM_HasV6, // SMUAD = 1821
19206	CEFBS_IsARM_HasV6, // SMUADX = 1822
19207	CEFBS_IsARM_HasV5TE, // SMULBB = 1823
19208	CEFBS_IsARM_HasV5TE, // SMULBT = 1824
19209	CEFBS_IsARM_HasV6, // SMULL = 1825
19210	CEFBS_IsARM_HasV5TE, // SMULTB = 1826
19211	CEFBS_IsARM_HasV5TE, // SMULTT = 1827
19212	CEFBS_IsARM_HasV5TE, // SMULWB = 1828
19213	CEFBS_IsARM_HasV5TE, // SMULWT = 1829
19214	CEFBS_IsARM_HasV6, // SMUSD = 1830
19215	CEFBS_IsARM_HasV6, // SMUSDX = 1831
19216	CEFBS_IsARM, // SRSDA = 1832
19217	CEFBS_IsARM, // SRSDA_UPD = 1833
19218	CEFBS_IsARM, // SRSDB = 1834
19219	CEFBS_IsARM, // SRSDB_UPD = 1835
19220	CEFBS_IsARM, // SRSIA = 1836
19221	CEFBS_IsARM, // SRSIA_UPD = 1837
19222	CEFBS_IsARM, // SRSIB = 1838
19223	CEFBS_IsARM, // SRSIB_UPD = 1839
19224	CEFBS_IsARM_HasV6, // SSAT = 1840
19225	CEFBS_IsARM_HasV6, // SSAT16 = 1841
19226	CEFBS_IsARM, // SSAX = 1842
19227	CEFBS_IsARM, // SSUB16 = 1843
19228	CEFBS_IsARM, // SSUB8 = 1844
19229	CEFBS_IsARM_PreV8, // STC2L_OFFSET = 1845
19230	CEFBS_IsARM_PreV8, // STC2L_OPTION = 1846
19231	CEFBS_IsARM_PreV8, // STC2L_POST = 1847
19232	CEFBS_IsARM_PreV8, // STC2L_PRE = 1848
19233	CEFBS_IsARM_PreV8, // STC2_OFFSET = 1849
19234	CEFBS_IsARM_PreV8, // STC2_OPTION = 1850
19235	CEFBS_IsARM_PreV8, // STC2_POST = 1851
19236	CEFBS_IsARM_PreV8, // STC2_PRE = 1852
19237	CEFBS_IsARM, // STCL_OFFSET = 1853
19238	CEFBS_IsARM, // STCL_OPTION = 1854
19239	CEFBS_IsARM, // STCL_POST = 1855
19240	CEFBS_IsARM, // STCL_PRE = 1856
19241	CEFBS_IsARM, // STC_OFFSET = 1857
19242	CEFBS_IsARM, // STC_OPTION = 1858
19243	CEFBS_IsARM, // STC_POST = 1859
19244	CEFBS_IsARM, // STC_PRE = 1860
19245	CEFBS_IsARM_HasAcquireRelease, // STL = 1861
19246	CEFBS_IsARM_HasAcquireRelease, // STLB = 1862
19247	CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // STLEX = 1863
19248	CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // STLEXB = 1864
19249	CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // STLEXD = 1865
19250	CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // STLEXH = 1866
19251	CEFBS_IsARM_HasAcquireRelease, // STLH = 1867
19252	CEFBS_IsARM, // STMDA = 1868
19253	CEFBS_IsARM, // STMDA_UPD = 1869
19254	CEFBS_IsARM, // STMDB = 1870
19255	CEFBS_IsARM, // STMDB_UPD = 1871
19256	CEFBS_IsARM, // STMIA = 1872
19257	CEFBS_IsARM, // STMIA_UPD = 1873
19258	CEFBS_IsARM, // STMIB = 1874
19259	CEFBS_IsARM, // STMIB_UPD = 1875
19260	CEFBS_IsARM, // STRBT_POST_IMM = 1876
19261	CEFBS_IsARM, // STRBT_POST_REG = 1877
19262	CEFBS_IsARM, // STRB_POST_IMM = 1878
19263	CEFBS_IsARM, // STRB_POST_REG = 1879
19264	CEFBS_IsARM, // STRB_PRE_IMM = 1880
19265	CEFBS_IsARM, // STRB_PRE_REG = 1881
19266	CEFBS_IsARM, // STRBi12 = 1882
19267	CEFBS_IsARM, // STRBrs = 1883
19268	CEFBS_IsARM_HasV5TE, // STRD = 1884
19269	CEFBS_IsARM, // STRD_POST = 1885
19270	CEFBS_IsARM, // STRD_PRE = 1886
19271	CEFBS_IsARM, // STREX = 1887
19272	CEFBS_IsARM, // STREXB = 1888
19273	CEFBS_IsARM, // STREXD = 1889
19274	CEFBS_IsARM, // STREXH = 1890
19275	CEFBS_IsARM, // STRH = 1891
19276	CEFBS_IsARM, // STRHTi = 1892
19277	CEFBS_IsARM, // STRHTr = 1893
19278	CEFBS_IsARM, // STRH_POST = 1894
19279	CEFBS_IsARM, // STRH_PRE = 1895
19280	CEFBS_IsARM, // STRT_POST_IMM = 1896
19281	CEFBS_IsARM, // STRT_POST_REG = 1897
19282	CEFBS_IsARM, // STR_POST_IMM = 1898
19283	CEFBS_IsARM, // STR_POST_REG = 1899
19284	CEFBS_IsARM, // STR_PRE_IMM = 1900
19285	CEFBS_IsARM, // STR_PRE_REG = 1901
19286	CEFBS_IsARM, // STRi12 = 1902
19287	CEFBS_IsARM, // STRrs = 1903
19288	CEFBS_IsARM, // SUBri = 1904
19289	CEFBS_IsARM, // SUBrr = 1905
19290	CEFBS_IsARM, // SUBrsi = 1906
19291	CEFBS_IsARM, // SUBrsr = 1907
19292	CEFBS_IsARM, // SVC = 1908
19293	CEFBS_IsARM_PreV8, // SWP = 1909
19294	CEFBS_IsARM_PreV8, // SWPB = 1910
19295	CEFBS_IsARM_HasV6, // SXTAB = 1911
19296	CEFBS_IsARM_HasV6, // SXTAB16 = 1912
19297	CEFBS_IsARM_HasV6, // SXTAH = 1913
19298	CEFBS_IsARM_HasV6, // SXTB = 1914
19299	CEFBS_IsARM_HasV6, // SXTB16 = 1915
19300	CEFBS_IsARM_HasV6, // SXTH = 1916
19301	CEFBS_IsARM, // TEQri = 1917
19302	CEFBS_IsARM, // TEQrr = 1918
19303	CEFBS_IsARM, // TEQrsi = 1919
19304	CEFBS_IsARM, // TEQrsr = 1920
19305	CEFBS_IsARM, // TRAP = 1921
19306	CEFBS_IsARM_UseNaClTrap, // TRAPNaCl = 1922
19307	CEFBS_IsARM_HasV8_4a, // TSB = 1923
19308	CEFBS_IsARM, // TSTri = 1924
19309	CEFBS_IsARM, // TSTrr = 1925
19310	CEFBS_IsARM, // TSTrsi = 1926
19311	CEFBS_IsARM, // TSTrsr = 1927
19312	CEFBS_IsARM, // UADD16 = 1928
19313	CEFBS_IsARM, // UADD8 = 1929
19314	CEFBS_IsARM, // UASX = 1930
19315	CEFBS_IsARM_HasV6T2, // UBFX = 1931
19316	CEFBS_IsARM, // UDF = 1932
19317	CEFBS_IsARM_HasDivideInARM, // UDIV = 1933
19318	CEFBS_IsARM, // UHADD16 = 1934
19319	CEFBS_IsARM, // UHADD8 = 1935
19320	CEFBS_IsARM, // UHASX = 1936
19321	CEFBS_IsARM, // UHSAX = 1937
19322	CEFBS_IsARM, // UHSUB16 = 1938
19323	CEFBS_IsARM, // UHSUB8 = 1939
19324	CEFBS_IsARM_HasV6, // UMAAL = 1940
19325	CEFBS_IsARM_HasV6, // UMLAL = 1941
19326	CEFBS_IsARM_HasV6, // UMULL = 1942
19327	CEFBS_IsARM, // UQADD16 = 1943
19328	CEFBS_IsARM, // UQADD8 = 1944
19329	CEFBS_IsARM, // UQASX = 1945
19330	CEFBS_IsARM, // UQSAX = 1946
19331	CEFBS_IsARM, // UQSUB16 = 1947
19332	CEFBS_IsARM, // UQSUB8 = 1948
19333	CEFBS_IsARM_HasV6, // USAD8 = 1949
19334	CEFBS_IsARM_HasV6, // USADA8 = 1950
19335	CEFBS_IsARM_HasV6, // USAT = 1951
19336	CEFBS_IsARM_HasV6, // USAT16 = 1952
19337	CEFBS_IsARM, // USAX = 1953
19338	CEFBS_IsARM, // USUB16 = 1954
19339	CEFBS_IsARM, // USUB8 = 1955
19340	CEFBS_IsARM_HasV6, // UXTAB = 1956
19341	CEFBS_IsARM_HasV6, // UXTAB16 = 1957
19342	CEFBS_IsARM_HasV6, // UXTAH = 1958
19343	CEFBS_IsARM_HasV6, // UXTB = 1959
19344	CEFBS_IsARM_HasV6, // UXTB16 = 1960
19345	CEFBS_IsARM_HasV6, // UXTH = 1961
19346	CEFBS_HasNEON, // VABALsv2i64 = 1962
19347	CEFBS_HasNEON, // VABALsv4i32 = 1963
19348	CEFBS_HasNEON, // VABALsv8i16 = 1964
19349	CEFBS_HasNEON, // VABALuv2i64 = 1965
19350	CEFBS_HasNEON, // VABALuv4i32 = 1966
19351	CEFBS_HasNEON, // VABALuv8i16 = 1967
19352	CEFBS_HasNEON, // VABAsv16i8 = 1968
19353	CEFBS_HasNEON, // VABAsv2i32 = 1969
19354	CEFBS_HasNEON, // VABAsv4i16 = 1970
19355	CEFBS_HasNEON, // VABAsv4i32 = 1971
19356	CEFBS_HasNEON, // VABAsv8i16 = 1972
19357	CEFBS_HasNEON, // VABAsv8i8 = 1973
19358	CEFBS_HasNEON, // VABAuv16i8 = 1974
19359	CEFBS_HasNEON, // VABAuv2i32 = 1975
19360	CEFBS_HasNEON, // VABAuv4i16 = 1976
19361	CEFBS_HasNEON, // VABAuv4i32 = 1977
19362	CEFBS_HasNEON, // VABAuv8i16 = 1978
19363	CEFBS_HasNEON, // VABAuv8i8 = 1979
19364	CEFBS_HasNEON, // VABDLsv2i64 = 1980
19365	CEFBS_HasNEON, // VABDLsv4i32 = 1981
19366	CEFBS_HasNEON, // VABDLsv8i16 = 1982
19367	CEFBS_HasNEON, // VABDLuv2i64 = 1983
19368	CEFBS_HasNEON, // VABDLuv4i32 = 1984
19369	CEFBS_HasNEON, // VABDLuv8i16 = 1985
19370	CEFBS_HasNEON, // VABDfd = 1986
19371	CEFBS_HasNEON, // VABDfq = 1987
19372	CEFBS_HasNEON_HasFullFP16, // VABDhd = 1988
19373	CEFBS_HasNEON_HasFullFP16, // VABDhq = 1989
19374	CEFBS_HasNEON, // VABDsv16i8 = 1990
19375	CEFBS_HasNEON, // VABDsv2i32 = 1991
19376	CEFBS_HasNEON, // VABDsv4i16 = 1992
19377	CEFBS_HasNEON, // VABDsv4i32 = 1993
19378	CEFBS_HasNEON, // VABDsv8i16 = 1994
19379	CEFBS_HasNEON, // VABDsv8i8 = 1995
19380	CEFBS_HasNEON, // VABDuv16i8 = 1996
19381	CEFBS_HasNEON, // VABDuv2i32 = 1997
19382	CEFBS_HasNEON, // VABDuv4i16 = 1998
19383	CEFBS_HasNEON, // VABDuv4i32 = 1999
19384	CEFBS_HasNEON, // VABDuv8i16 = 2000
19385	CEFBS_HasNEON, // VABDuv8i8 = 2001
19386	CEFBS_HasVFP2_HasDPVFP, // VABSD = 2002
19387	CEFBS_HasFullFP16, // VABSH = 2003
19388	CEFBS_HasVFP2, // VABSS = 2004
19389	CEFBS_HasNEON, // VABSfd = 2005
19390	CEFBS_HasNEON, // VABSfq = 2006
19391	CEFBS_HasNEON_HasFullFP16, // VABShd = 2007
19392	CEFBS_HasNEON_HasFullFP16, // VABShq = 2008
19393	CEFBS_HasNEON, // VABSv16i8 = 2009
19394	CEFBS_HasNEON, // VABSv2i32 = 2010
19395	CEFBS_HasNEON, // VABSv4i16 = 2011
19396	CEFBS_HasNEON, // VABSv4i32 = 2012
19397	CEFBS_HasNEON, // VABSv8i16 = 2013
19398	CEFBS_HasNEON, // VABSv8i8 = 2014
19399	CEFBS_HasNEON, // VACGEfd = 2015
19400	CEFBS_HasNEON, // VACGEfq = 2016
19401	CEFBS_HasNEON_HasFullFP16, // VACGEhd = 2017
19402	CEFBS_HasNEON_HasFullFP16, // VACGEhq = 2018
19403	CEFBS_HasNEON, // VACGTfd = 2019
19404	CEFBS_HasNEON, // VACGTfq = 2020
19405	CEFBS_HasNEON_HasFullFP16, // VACGThd = 2021
19406	CEFBS_HasNEON_HasFullFP16, // VACGThq = 2022
19407	CEFBS_HasVFP2_HasDPVFP, // VADDD = 2023
19408	CEFBS_HasFullFP16, // VADDH = 2024
19409	CEFBS_HasNEON, // VADDHNv2i32 = 2025
19410	CEFBS_HasNEON, // VADDHNv4i16 = 2026
19411	CEFBS_HasNEON, // VADDHNv8i8 = 2027
19412	CEFBS_HasNEON, // VADDLsv2i64 = 2028
19413	CEFBS_HasNEON, // VADDLsv4i32 = 2029
19414	CEFBS_HasNEON, // VADDLsv8i16 = 2030
19415	CEFBS_HasNEON, // VADDLuv2i64 = 2031
19416	CEFBS_HasNEON, // VADDLuv4i32 = 2032
19417	CEFBS_HasNEON, // VADDLuv8i16 = 2033
19418	CEFBS_HasVFP2, // VADDS = 2034
19419	CEFBS_HasNEON, // VADDWsv2i64 = 2035
19420	CEFBS_HasNEON, // VADDWsv4i32 = 2036
19421	CEFBS_HasNEON, // VADDWsv8i16 = 2037
19422	CEFBS_HasNEON, // VADDWuv2i64 = 2038
19423	CEFBS_HasNEON, // VADDWuv4i32 = 2039
19424	CEFBS_HasNEON, // VADDWuv8i16 = 2040
19425	CEFBS_HasNEON, // VADDfd = 2041
19426	CEFBS_HasNEON, // VADDfq = 2042
19427	CEFBS_HasNEON_HasFullFP16, // VADDhd = 2043
19428	CEFBS_HasNEON_HasFullFP16, // VADDhq = 2044
19429	CEFBS_HasNEON, // VADDv16i8 = 2045
19430	CEFBS_HasNEON, // VADDv1i64 = 2046
19431	CEFBS_HasNEON, // VADDv2i32 = 2047
19432	CEFBS_HasNEON, // VADDv2i64 = 2048
19433	CEFBS_HasNEON, // VADDv4i16 = 2049
19434	CEFBS_HasNEON, // VADDv4i32 = 2050
19435	CEFBS_HasNEON, // VADDv8i16 = 2051
19436	CEFBS_HasNEON, // VADDv8i8 = 2052
19437	CEFBS_HasNEON, // VANDd = 2053
19438	CEFBS_HasNEON, // VANDq = 2054
19439	CEFBS_HasBF16_HasNEON, // VBF16MALBQ = 2055
19440	CEFBS_HasBF16_HasNEON, // VBF16MALBQI = 2056
19441	CEFBS_HasBF16_HasNEON, // VBF16MALTQ = 2057
19442	CEFBS_HasBF16_HasNEON, // VBF16MALTQI = 2058
19443	CEFBS_HasNEON, // VBICd = 2059
19444	CEFBS_HasNEON, // VBICiv2i32 = 2060
19445	CEFBS_HasNEON, // VBICiv4i16 = 2061
19446	CEFBS_HasNEON, // VBICiv4i32 = 2062
19447	CEFBS_HasNEON, // VBICiv8i16 = 2063
19448	CEFBS_HasNEON, // VBICq = 2064
19449	CEFBS_HasNEON, // VBIFd = 2065
19450	CEFBS_HasNEON, // VBIFq = 2066
19451	CEFBS_HasNEON, // VBITd = 2067
19452	CEFBS_HasNEON, // VBITq = 2068
19453	CEFBS_HasNEON, // VBSLd = 2069
19454	CEFBS_HasNEON, // VBSLq = 2070
19455	CEFBS_HasNEON, // VBSPd = 2071
19456	CEFBS_HasNEON, // VBSPq = 2072
19457	CEFBS_HasNEON_HasV8_3a, // VCADDv2f32 = 2073
19458	CEFBS_HasNEON_HasV8_3a_HasFullFP16, // VCADDv4f16 = 2074
19459	CEFBS_HasNEON_HasV8_3a, // VCADDv4f32 = 2075
19460	CEFBS_HasNEON_HasV8_3a_HasFullFP16, // VCADDv8f16 = 2076
19461	CEFBS_HasNEON, // VCEQfd = 2077
19462	CEFBS_HasNEON, // VCEQfq = 2078
19463	CEFBS_HasNEON_HasFullFP16, // VCEQhd = 2079
19464	CEFBS_HasNEON_HasFullFP16, // VCEQhq = 2080
19465	CEFBS_HasNEON, // VCEQv16i8 = 2081
19466	CEFBS_HasNEON, // VCEQv2i32 = 2082
19467	CEFBS_HasNEON, // VCEQv4i16 = 2083
19468	CEFBS_HasNEON, // VCEQv4i32 = 2084
19469	CEFBS_HasNEON, // VCEQv8i16 = 2085
19470	CEFBS_HasNEON, // VCEQv8i8 = 2086
19471	CEFBS_HasNEON, // VCEQzv16i8 = 2087
19472	CEFBS_HasNEON, // VCEQzv2f32 = 2088
19473	CEFBS_HasNEON, // VCEQzv2i32 = 2089
19474	CEFBS_HasNEON_HasFullFP16, // VCEQzv4f16 = 2090
19475	CEFBS_HasNEON, // VCEQzv4f32 = 2091
19476	CEFBS_HasNEON, // VCEQzv4i16 = 2092
19477	CEFBS_HasNEON, // VCEQzv4i32 = 2093
19478	CEFBS_HasNEON_HasFullFP16, // VCEQzv8f16 = 2094
19479	CEFBS_HasNEON, // VCEQzv8i16 = 2095
19480	CEFBS_HasNEON, // VCEQzv8i8 = 2096
19481	CEFBS_HasNEON, // VCGEfd = 2097
19482	CEFBS_HasNEON, // VCGEfq = 2098
19483	CEFBS_HasNEON_HasFullFP16, // VCGEhd = 2099
19484	CEFBS_HasNEON_HasFullFP16, // VCGEhq = 2100
19485	CEFBS_HasNEON, // VCGEsv16i8 = 2101
19486	CEFBS_HasNEON, // VCGEsv2i32 = 2102
19487	CEFBS_HasNEON, // VCGEsv4i16 = 2103
19488	CEFBS_HasNEON, // VCGEsv4i32 = 2104
19489	CEFBS_HasNEON, // VCGEsv8i16 = 2105
19490	CEFBS_HasNEON, // VCGEsv8i8 = 2106
19491	CEFBS_HasNEON, // VCGEuv16i8 = 2107
19492	CEFBS_HasNEON, // VCGEuv2i32 = 2108
19493	CEFBS_HasNEON, // VCGEuv4i16 = 2109
19494	CEFBS_HasNEON, // VCGEuv4i32 = 2110
19495	CEFBS_HasNEON, // VCGEuv8i16 = 2111
19496	CEFBS_HasNEON, // VCGEuv8i8 = 2112
19497	CEFBS_HasNEON, // VCGEzv16i8 = 2113
19498	CEFBS_HasNEON, // VCGEzv2f32 = 2114
19499	CEFBS_HasNEON, // VCGEzv2i32 = 2115
19500	CEFBS_HasNEON_HasFullFP16, // VCGEzv4f16 = 2116
19501	CEFBS_HasNEON, // VCGEzv4f32 = 2117
19502	CEFBS_HasNEON, // VCGEzv4i16 = 2118
19503	CEFBS_HasNEON, // VCGEzv4i32 = 2119
19504	CEFBS_HasNEON_HasFullFP16, // VCGEzv8f16 = 2120
19505	CEFBS_HasNEON, // VCGEzv8i16 = 2121
19506	CEFBS_HasNEON, // VCGEzv8i8 = 2122
19507	CEFBS_HasNEON, // VCGTfd = 2123
19508	CEFBS_HasNEON, // VCGTfq = 2124
19509	CEFBS_HasNEON_HasFullFP16, // VCGThd = 2125
19510	CEFBS_HasNEON_HasFullFP16, // VCGThq = 2126
19511	CEFBS_HasNEON, // VCGTsv16i8 = 2127
19512	CEFBS_HasNEON, // VCGTsv2i32 = 2128
19513	CEFBS_HasNEON, // VCGTsv4i16 = 2129
19514	CEFBS_HasNEON, // VCGTsv4i32 = 2130
19515	CEFBS_HasNEON, // VCGTsv8i16 = 2131
19516	CEFBS_HasNEON, // VCGTsv8i8 = 2132
19517	CEFBS_HasNEON, // VCGTuv16i8 = 2133
19518	CEFBS_HasNEON, // VCGTuv2i32 = 2134
19519	CEFBS_HasNEON, // VCGTuv4i16 = 2135
19520	CEFBS_HasNEON, // VCGTuv4i32 = 2136
19521	CEFBS_HasNEON, // VCGTuv8i16 = 2137
19522	CEFBS_HasNEON, // VCGTuv8i8 = 2138
19523	CEFBS_HasNEON, // VCGTzv16i8 = 2139
19524	CEFBS_HasNEON, // VCGTzv2f32 = 2140
19525	CEFBS_HasNEON, // VCGTzv2i32 = 2141
19526	CEFBS_HasNEON_HasFullFP16, // VCGTzv4f16 = 2142
19527	CEFBS_HasNEON, // VCGTzv4f32 = 2143
19528	CEFBS_HasNEON, // VCGTzv4i16 = 2144
19529	CEFBS_HasNEON, // VCGTzv4i32 = 2145
19530	CEFBS_HasNEON_HasFullFP16, // VCGTzv8f16 = 2146
19531	CEFBS_HasNEON, // VCGTzv8i16 = 2147
19532	CEFBS_HasNEON, // VCGTzv8i8 = 2148
19533	CEFBS_HasNEON, // VCLEzv16i8 = 2149
19534	CEFBS_HasNEON, // VCLEzv2f32 = 2150
19535	CEFBS_HasNEON, // VCLEzv2i32 = 2151
19536	CEFBS_HasNEON_HasFullFP16, // VCLEzv4f16 = 2152
19537	CEFBS_HasNEON, // VCLEzv4f32 = 2153
19538	CEFBS_HasNEON, // VCLEzv4i16 = 2154
19539	CEFBS_HasNEON, // VCLEzv4i32 = 2155
19540	CEFBS_HasNEON_HasFullFP16, // VCLEzv8f16 = 2156
19541	CEFBS_HasNEON, // VCLEzv8i16 = 2157
19542	CEFBS_HasNEON, // VCLEzv8i8 = 2158
19543	CEFBS_HasNEON, // VCLSv16i8 = 2159
19544	CEFBS_HasNEON, // VCLSv2i32 = 2160
19545	CEFBS_HasNEON, // VCLSv4i16 = 2161
19546	CEFBS_HasNEON, // VCLSv4i32 = 2162
19547	CEFBS_HasNEON, // VCLSv8i16 = 2163
19548	CEFBS_HasNEON, // VCLSv8i8 = 2164
19549	CEFBS_HasNEON, // VCLTzv16i8 = 2165
19550	CEFBS_HasNEON, // VCLTzv2f32 = 2166
19551	CEFBS_HasNEON, // VCLTzv2i32 = 2167
19552	CEFBS_HasNEON_HasFullFP16, // VCLTzv4f16 = 2168
19553	CEFBS_HasNEON, // VCLTzv4f32 = 2169
19554	CEFBS_HasNEON, // VCLTzv4i16 = 2170
19555	CEFBS_HasNEON, // VCLTzv4i32 = 2171
19556	CEFBS_HasNEON_HasFullFP16, // VCLTzv8f16 = 2172
19557	CEFBS_HasNEON, // VCLTzv8i16 = 2173
19558	CEFBS_HasNEON, // VCLTzv8i8 = 2174
19559	CEFBS_HasNEON, // VCLZv16i8 = 2175
19560	CEFBS_HasNEON, // VCLZv2i32 = 2176
19561	CEFBS_HasNEON, // VCLZv4i16 = 2177
19562	CEFBS_HasNEON, // VCLZv4i32 = 2178
19563	CEFBS_HasNEON, // VCLZv8i16 = 2179
19564	CEFBS_HasNEON, // VCLZv8i8 = 2180
19565	CEFBS_HasNEON_HasV8_3a, // VCMLAv2f32 = 2181
19566	CEFBS_HasNEON_HasV8_3a, // VCMLAv2f32_indexed = 2182
19567	CEFBS_HasNEON_HasV8_3a_HasFullFP16, // VCMLAv4f16 = 2183
19568	CEFBS_HasNEON_HasV8_3a_HasFullFP16, // VCMLAv4f16_indexed = 2184
19569	CEFBS_HasNEON_HasV8_3a, // VCMLAv4f32 = 2185
19570	CEFBS_HasNEON_HasV8_3a, // VCMLAv4f32_indexed = 2186
19571	CEFBS_HasNEON_HasV8_3a_HasFullFP16, // VCMLAv8f16 = 2187
19572	CEFBS_HasNEON_HasV8_3a_HasFullFP16, // VCMLAv8f16_indexed = 2188
19573	CEFBS_HasVFP2_HasDPVFP, // VCMPD = 2189
19574	CEFBS_HasVFP2_HasDPVFP, // VCMPED = 2190
19575	CEFBS_HasFullFP16, // VCMPEH = 2191
19576	CEFBS_HasVFP2, // VCMPES = 2192
19577	CEFBS_HasVFP2_HasDPVFP, // VCMPEZD = 2193
19578	CEFBS_HasFullFP16, // VCMPEZH = 2194
19579	CEFBS_HasVFP2, // VCMPEZS = 2195
19580	CEFBS_HasFullFP16, // VCMPH = 2196
19581	CEFBS_HasVFP2, // VCMPS = 2197
19582	CEFBS_HasVFP2_HasDPVFP, // VCMPZD = 2198
19583	CEFBS_HasFullFP16, // VCMPZH = 2199
19584	CEFBS_HasVFP2, // VCMPZS = 2200
19585	CEFBS_HasNEON, // VCNTd = 2201
19586	CEFBS_HasNEON, // VCNTq = 2202
19587	CEFBS_HasV8_HasNEON, // VCVTANSDf = 2203
19588	CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTANSDh = 2204
19589	CEFBS_HasV8_HasNEON, // VCVTANSQf = 2205
19590	CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTANSQh = 2206
19591	CEFBS_HasV8_HasNEON, // VCVTANUDf = 2207
19592	CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTANUDh = 2208
19593	CEFBS_HasV8_HasNEON, // VCVTANUQf = 2209
19594	CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTANUQh = 2210
19595	CEFBS_HasFPARMv8_HasDPVFP, // VCVTASD = 2211
19596	CEFBS_HasFullFP16, // VCVTASH = 2212
19597	CEFBS_HasFPARMv8, // VCVTASS = 2213
19598	CEFBS_HasFPARMv8_HasDPVFP, // VCVTAUD = 2214
19599	CEFBS_HasFullFP16, // VCVTAUH = 2215
19600	CEFBS_HasFPARMv8, // VCVTAUS = 2216
19601	CEFBS_HasFPARMv8_HasDPVFP, // VCVTBDH = 2217
19602	CEFBS_HasFPARMv8_HasDPVFP, // VCVTBHD = 2218
19603	CEFBS_HasFP16, // VCVTBHS = 2219
19604	CEFBS_HasFP16, // VCVTBSH = 2220
19605	CEFBS_HasVFP2_HasDPVFP, // VCVTDS = 2221
19606	CEFBS_HasV8_HasNEON, // VCVTMNSDf = 2222
19607	CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTMNSDh = 2223
19608	CEFBS_HasV8_HasNEON, // VCVTMNSQf = 2224
19609	CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTMNSQh = 2225
19610	CEFBS_HasV8_HasNEON, // VCVTMNUDf = 2226
19611	CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTMNUDh = 2227
19612	CEFBS_HasV8_HasNEON, // VCVTMNUQf = 2228
19613	CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTMNUQh = 2229
19614	CEFBS_HasFPARMv8_HasDPVFP, // VCVTMSD = 2230
19615	CEFBS_HasFullFP16, // VCVTMSH = 2231
19616	CEFBS_HasFPARMv8, // VCVTMSS = 2232
19617	CEFBS_HasFPARMv8_HasDPVFP, // VCVTMUD = 2233
19618	CEFBS_HasFullFP16, // VCVTMUH = 2234
19619	CEFBS_HasFPARMv8, // VCVTMUS = 2235
19620	CEFBS_HasV8_HasNEON, // VCVTNNSDf = 2236
19621	CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTNNSDh = 2237
19622	CEFBS_HasV8_HasNEON, // VCVTNNSQf = 2238
19623	CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTNNSQh = 2239
19624	CEFBS_HasV8_HasNEON, // VCVTNNUDf = 2240
19625	CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTNNUDh = 2241
19626	CEFBS_HasV8_HasNEON, // VCVTNNUQf = 2242
19627	CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTNNUQh = 2243
19628	CEFBS_HasFPARMv8_HasDPVFP, // VCVTNSD = 2244
19629	CEFBS_HasFullFP16, // VCVTNSH = 2245
19630	CEFBS_HasFPARMv8, // VCVTNSS = 2246
19631	CEFBS_HasFPARMv8_HasDPVFP, // VCVTNUD = 2247
19632	CEFBS_HasFullFP16, // VCVTNUH = 2248
19633	CEFBS_HasFPARMv8, // VCVTNUS = 2249
19634	CEFBS_HasV8_HasNEON, // VCVTPNSDf = 2250
19635	CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTPNSDh = 2251
19636	CEFBS_HasV8_HasNEON, // VCVTPNSQf = 2252
19637	CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTPNSQh = 2253
19638	CEFBS_HasV8_HasNEON, // VCVTPNUDf = 2254
19639	CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTPNUDh = 2255
19640	CEFBS_HasV8_HasNEON, // VCVTPNUQf = 2256
19641	CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTPNUQh = 2257
19642	CEFBS_HasFPARMv8_HasDPVFP, // VCVTPSD = 2258
19643	CEFBS_HasFullFP16, // VCVTPSH = 2259
19644	CEFBS_HasFPARMv8, // VCVTPSS = 2260
19645	CEFBS_HasFPARMv8_HasDPVFP, // VCVTPUD = 2261
19646	CEFBS_HasFullFP16, // VCVTPUH = 2262
19647	CEFBS_HasFPARMv8, // VCVTPUS = 2263
19648	CEFBS_HasVFP2_HasDPVFP, // VCVTSD = 2264
19649	CEFBS_HasFPARMv8_HasDPVFP, // VCVTTDH = 2265
19650	CEFBS_HasFPARMv8_HasDPVFP, // VCVTTHD = 2266
19651	CEFBS_HasFP16, // VCVTTHS = 2267
19652	CEFBS_HasFP16, // VCVTTSH = 2268
19653	CEFBS_HasNEON_HasFP16, // VCVTf2h = 2269
19654	CEFBS_HasNEON, // VCVTf2sd = 2270
19655	CEFBS_HasNEON, // VCVTf2sq = 2271
19656	CEFBS_HasNEON, // VCVTf2ud = 2272
19657	CEFBS_HasNEON, // VCVTf2uq = 2273
19658	CEFBS_HasNEON, // VCVTf2xsd = 2274
19659	CEFBS_HasNEON, // VCVTf2xsq = 2275
19660	CEFBS_HasNEON, // VCVTf2xud = 2276
19661	CEFBS_HasNEON, // VCVTf2xuq = 2277
19662	CEFBS_HasNEON_HasFP16, // VCVTh2f = 2278
19663	CEFBS_HasNEON_HasFullFP16, // VCVTh2sd = 2279
19664	CEFBS_HasNEON_HasFullFP16, // VCVTh2sq = 2280
19665	CEFBS_HasNEON_HasFullFP16, // VCVTh2ud = 2281
19666	CEFBS_HasNEON_HasFullFP16, // VCVTh2uq = 2282
19667	CEFBS_HasNEON_HasFullFP16, // VCVTh2xsd = 2283
19668	CEFBS_HasNEON_HasFullFP16, // VCVTh2xsq = 2284
19669	CEFBS_HasNEON_HasFullFP16, // VCVTh2xud = 2285
19670	CEFBS_HasNEON_HasFullFP16, // VCVTh2xuq = 2286
19671	CEFBS_HasNEON, // VCVTs2fd = 2287
19672	CEFBS_HasNEON, // VCVTs2fq = 2288
19673	CEFBS_HasNEON_HasFullFP16, // VCVTs2hd = 2289
19674	CEFBS_HasNEON_HasFullFP16, // VCVTs2hq = 2290
19675	CEFBS_HasNEON, // VCVTu2fd = 2291
19676	CEFBS_HasNEON, // VCVTu2fq = 2292
19677	CEFBS_HasNEON_HasFullFP16, // VCVTu2hd = 2293
19678	CEFBS_HasNEON_HasFullFP16, // VCVTu2hq = 2294
19679	CEFBS_HasNEON, // VCVTxs2fd = 2295
19680	CEFBS_HasNEON, // VCVTxs2fq = 2296
19681	CEFBS_HasNEON_HasFullFP16, // VCVTxs2hd = 2297
19682	CEFBS_HasNEON_HasFullFP16, // VCVTxs2hq = 2298
19683	CEFBS_HasNEON, // VCVTxu2fd = 2299
19684	CEFBS_HasNEON, // VCVTxu2fq = 2300
19685	CEFBS_HasNEON_HasFullFP16, // VCVTxu2hd = 2301
19686	CEFBS_HasNEON_HasFullFP16, // VCVTxu2hq = 2302
19687	CEFBS_HasVFP2_HasDPVFP, // VDIVD = 2303
19688	CEFBS_HasFullFP16, // VDIVH = 2304
19689	CEFBS_HasVFP2, // VDIVS = 2305
19690	CEFBS_HasNEON, // VDUP16d = 2306
19691	CEFBS_HasNEON, // VDUP16q = 2307
19692	CEFBS_HasNEON, // VDUP32d = 2308
19693	CEFBS_HasNEON, // VDUP32q = 2309
19694	CEFBS_HasNEON, // VDUP8d = 2310
19695	CEFBS_HasNEON, // VDUP8q = 2311
19696	CEFBS_HasNEON, // VDUPLN16d = 2312
19697	CEFBS_HasNEON, // VDUPLN16q = 2313
19698	CEFBS_HasNEON, // VDUPLN32d = 2314
19699	CEFBS_HasNEON, // VDUPLN32q = 2315
19700	CEFBS_HasNEON, // VDUPLN8d = 2316
19701	CEFBS_HasNEON, // VDUPLN8q = 2317
19702	CEFBS_HasNEON, // VEORd = 2318
19703	CEFBS_HasNEON, // VEORq = 2319
19704	CEFBS_HasNEON, // VEXTd16 = 2320
19705	CEFBS_HasNEON, // VEXTd32 = 2321
19706	CEFBS_HasNEON, // VEXTd8 = 2322
19707	CEFBS_HasNEON, // VEXTq16 = 2323
19708	CEFBS_HasNEON, // VEXTq32 = 2324
19709	CEFBS_HasNEON, // VEXTq64 = 2325
19710	CEFBS_HasNEON, // VEXTq8 = 2326
19711	CEFBS_HasVFP4_HasDPVFP, // VFMAD = 2327
19712	CEFBS_HasFullFP16, // VFMAH = 2328
19713	CEFBS_HasNEON_HasFP16FML, // VFMALD = 2329
19714	CEFBS_HasNEON_HasFP16FML, // VFMALDI = 2330
19715	CEFBS_HasNEON_HasFP16FML, // VFMALQ = 2331
19716	CEFBS_HasNEON_HasFP16FML, // VFMALQI = 2332
19717	CEFBS_HasVFP4, // VFMAS = 2333
19718	CEFBS_HasNEON_HasVFP4, // VFMAfd = 2334
19719	CEFBS_HasNEON_HasVFP4, // VFMAfq = 2335
19720	CEFBS_HasNEON_HasFullFP16, // VFMAhd = 2336
19721	CEFBS_HasNEON_HasFullFP16, // VFMAhq = 2337
19722	CEFBS_HasVFP4_HasDPVFP, // VFMSD = 2338
19723	CEFBS_HasFullFP16, // VFMSH = 2339
19724	CEFBS_HasNEON_HasFP16FML, // VFMSLD = 2340
19725	CEFBS_HasNEON_HasFP16FML, // VFMSLDI = 2341
19726	CEFBS_HasNEON_HasFP16FML, // VFMSLQ = 2342
19727	CEFBS_HasNEON_HasFP16FML, // VFMSLQI = 2343
19728	CEFBS_HasVFP4, // VFMSS = 2344
19729	CEFBS_HasNEON_HasVFP4, // VFMSfd = 2345
19730	CEFBS_HasNEON_HasVFP4, // VFMSfq = 2346
19731	CEFBS_HasNEON_HasFullFP16, // VFMShd = 2347
19732	CEFBS_HasNEON_HasFullFP16, // VFMShq = 2348
19733	CEFBS_HasVFP4_HasDPVFP, // VFNMAD = 2349
19734	CEFBS_HasFullFP16, // VFNMAH = 2350
19735	CEFBS_HasVFP4, // VFNMAS = 2351
19736	CEFBS_HasVFP4_HasDPVFP, // VFNMSD = 2352
19737	CEFBS_HasFullFP16, // VFNMSH = 2353
19738	CEFBS_HasVFP4, // VFNMSS = 2354
19739	CEFBS_HasFPARMv8_HasDPVFP, // VFP_VMAXNMD = 2355
19740	CEFBS_HasFullFP16, // VFP_VMAXNMH = 2356
19741	CEFBS_HasFPARMv8, // VFP_VMAXNMS = 2357
19742	CEFBS_HasFPARMv8_HasDPVFP, // VFP_VMINNMD = 2358
19743	CEFBS_HasFullFP16, // VFP_VMINNMH = 2359
19744	CEFBS_HasFPARMv8, // VFP_VMINNMS = 2360
19745	CEFBS_HasFPRegs, // VGETLNi32 = 2361
19746	CEFBS_HasNEON, // VGETLNs16 = 2362
19747	CEFBS_HasNEON, // VGETLNs8 = 2363
19748	CEFBS_HasNEON, // VGETLNu16 = 2364
19749	CEFBS_HasNEON, // VGETLNu8 = 2365
19750	CEFBS_HasNEON, // VHADDsv16i8 = 2366
19751	CEFBS_HasNEON, // VHADDsv2i32 = 2367
19752	CEFBS_HasNEON, // VHADDsv4i16 = 2368
19753	CEFBS_HasNEON, // VHADDsv4i32 = 2369
19754	CEFBS_HasNEON, // VHADDsv8i16 = 2370
19755	CEFBS_HasNEON, // VHADDsv8i8 = 2371
19756	CEFBS_HasNEON, // VHADDuv16i8 = 2372
19757	CEFBS_HasNEON, // VHADDuv2i32 = 2373
19758	CEFBS_HasNEON, // VHADDuv4i16 = 2374
19759	CEFBS_HasNEON, // VHADDuv4i32 = 2375
19760	CEFBS_HasNEON, // VHADDuv8i16 = 2376
19761	CEFBS_HasNEON, // VHADDuv8i8 = 2377
19762	CEFBS_HasNEON, // VHSUBsv16i8 = 2378
19763	CEFBS_HasNEON, // VHSUBsv2i32 = 2379
19764	CEFBS_HasNEON, // VHSUBsv4i16 = 2380
19765	CEFBS_HasNEON, // VHSUBsv4i32 = 2381
19766	CEFBS_HasNEON, // VHSUBsv8i16 = 2382
19767	CEFBS_HasNEON, // VHSUBsv8i8 = 2383
19768	CEFBS_HasNEON, // VHSUBuv16i8 = 2384
19769	CEFBS_HasNEON, // VHSUBuv2i32 = 2385
19770	CEFBS_HasNEON, // VHSUBuv4i16 = 2386
19771	CEFBS_HasNEON, // VHSUBuv4i32 = 2387
19772	CEFBS_HasNEON, // VHSUBuv8i16 = 2388
19773	CEFBS_HasNEON, // VHSUBuv8i8 = 2389
19774	CEFBS_HasFullFP16, // VINSH = 2390
19775	CEFBS_HasFPARMv8_HasV8_3a, // VJCVT = 2391
19776	CEFBS_HasNEON, // VLD1DUPd16 = 2392
19777	CEFBS_HasNEON, // VLD1DUPd16wb_fixed = 2393
19778	CEFBS_HasNEON, // VLD1DUPd16wb_register = 2394
19779	CEFBS_HasNEON, // VLD1DUPd32 = 2395
19780	CEFBS_HasNEON, // VLD1DUPd32wb_fixed = 2396
19781	CEFBS_HasNEON, // VLD1DUPd32wb_register = 2397
19782	CEFBS_HasNEON, // VLD1DUPd8 = 2398
19783	CEFBS_HasNEON, // VLD1DUPd8wb_fixed = 2399
19784	CEFBS_HasNEON, // VLD1DUPd8wb_register = 2400
19785	CEFBS_HasNEON, // VLD1DUPq16 = 2401
19786	CEFBS_HasNEON, // VLD1DUPq16wb_fixed = 2402
19787	CEFBS_HasNEON, // VLD1DUPq16wb_register = 2403
19788	CEFBS_HasNEON, // VLD1DUPq32 = 2404
19789	CEFBS_HasNEON, // VLD1DUPq32wb_fixed = 2405
19790	CEFBS_HasNEON, // VLD1DUPq32wb_register = 2406
19791	CEFBS_HasNEON, // VLD1DUPq8 = 2407
19792	CEFBS_HasNEON, // VLD1DUPq8wb_fixed = 2408
19793	CEFBS_HasNEON, // VLD1DUPq8wb_register = 2409
19794	CEFBS_HasNEON, // VLD1LNd16 = 2410
19795	CEFBS_HasNEON, // VLD1LNd16_UPD = 2411
19796	CEFBS_HasNEON, // VLD1LNd32 = 2412
19797	CEFBS_HasNEON, // VLD1LNd32_UPD = 2413
19798	CEFBS_HasNEON, // VLD1LNd8 = 2414
19799	CEFBS_HasNEON, // VLD1LNd8_UPD = 2415
19800	CEFBS_HasNEON, // VLD1LNq16Pseudo = 2416
19801	CEFBS_HasNEON, // VLD1LNq16Pseudo_UPD = 2417
19802	CEFBS_HasNEON, // VLD1LNq32Pseudo = 2418
19803	CEFBS_HasNEON, // VLD1LNq32Pseudo_UPD = 2419
19804	CEFBS_HasNEON, // VLD1LNq8Pseudo = 2420
19805	CEFBS_HasNEON, // VLD1LNq8Pseudo_UPD = 2421
19806	CEFBS_HasNEON, // VLD1d16 = 2422
19807	CEFBS_HasNEON, // VLD1d16Q = 2423
19808	CEFBS_HasNEON, // VLD1d16QPseudo = 2424
19809	CEFBS_HasNEON, // VLD1d16Qwb_fixed = 2425
19810	CEFBS_HasNEON, // VLD1d16Qwb_register = 2426
19811	CEFBS_HasNEON, // VLD1d16T = 2427
19812	CEFBS_HasNEON, // VLD1d16TPseudo = 2428
19813	CEFBS_HasNEON, // VLD1d16Twb_fixed = 2429
19814	CEFBS_HasNEON, // VLD1d16Twb_register = 2430
19815	CEFBS_HasNEON, // VLD1d16wb_fixed = 2431
19816	CEFBS_HasNEON, // VLD1d16wb_register = 2432
19817	CEFBS_HasNEON, // VLD1d32 = 2433
19818	CEFBS_HasNEON, // VLD1d32Q = 2434
19819	CEFBS_HasNEON, // VLD1d32QPseudo = 2435
19820	CEFBS_HasNEON, // VLD1d32Qwb_fixed = 2436
19821	CEFBS_HasNEON, // VLD1d32Qwb_register = 2437
19822	CEFBS_HasNEON, // VLD1d32T = 2438
19823	CEFBS_HasNEON, // VLD1d32TPseudo = 2439
19824	CEFBS_HasNEON, // VLD1d32Twb_fixed = 2440
19825	CEFBS_HasNEON, // VLD1d32Twb_register = 2441
19826	CEFBS_HasNEON, // VLD1d32wb_fixed = 2442
19827	CEFBS_HasNEON, // VLD1d32wb_register = 2443
19828	CEFBS_HasNEON, // VLD1d64 = 2444
19829	CEFBS_HasNEON, // VLD1d64Q = 2445
19830	CEFBS_HasNEON, // VLD1d64QPseudo = 2446
19831	CEFBS_HasNEON, // VLD1d64QPseudoWB_fixed = 2447
19832	CEFBS_HasNEON, // VLD1d64QPseudoWB_register = 2448
19833	CEFBS_HasNEON, // VLD1d64Qwb_fixed = 2449
19834	CEFBS_HasNEON, // VLD1d64Qwb_register = 2450
19835	CEFBS_HasNEON, // VLD1d64T = 2451
19836	CEFBS_HasNEON, // VLD1d64TPseudo = 2452
19837	CEFBS_HasNEON, // VLD1d64TPseudoWB_fixed = 2453
19838	CEFBS_HasNEON, // VLD1d64TPseudoWB_register = 2454
19839	CEFBS_HasNEON, // VLD1d64Twb_fixed = 2455
19840	CEFBS_HasNEON, // VLD1d64Twb_register = 2456
19841	CEFBS_HasNEON, // VLD1d64wb_fixed = 2457
19842	CEFBS_HasNEON, // VLD1d64wb_register = 2458
19843	CEFBS_HasNEON, // VLD1d8 = 2459
19844	CEFBS_HasNEON, // VLD1d8Q = 2460
19845	CEFBS_HasNEON, // VLD1d8QPseudo = 2461
19846	CEFBS_HasNEON, // VLD1d8Qwb_fixed = 2462
19847	CEFBS_HasNEON, // VLD1d8Qwb_register = 2463
19848	CEFBS_HasNEON, // VLD1d8T = 2464
19849	CEFBS_HasNEON, // VLD1d8TPseudo = 2465
19850	CEFBS_HasNEON, // VLD1d8Twb_fixed = 2466
19851	CEFBS_HasNEON, // VLD1d8Twb_register = 2467
19852	CEFBS_HasNEON, // VLD1d8wb_fixed = 2468
19853	CEFBS_HasNEON, // VLD1d8wb_register = 2469
19854	CEFBS_HasNEON, // VLD1q16 = 2470
19855	CEFBS_HasNEON, // VLD1q16HighQPseudo = 2471
19856	CEFBS_HasNEON, // VLD1q16HighTPseudo = 2472
19857	CEFBS_HasNEON, // VLD1q16LowQPseudo_UPD = 2473
19858	CEFBS_HasNEON, // VLD1q16LowTPseudo_UPD = 2474
19859	CEFBS_HasNEON, // VLD1q16wb_fixed = 2475
19860	CEFBS_HasNEON, // VLD1q16wb_register = 2476
19861	CEFBS_HasNEON, // VLD1q32 = 2477
19862	CEFBS_HasNEON, // VLD1q32HighQPseudo = 2478
19863	CEFBS_HasNEON, // VLD1q32HighTPseudo = 2479
19864	CEFBS_HasNEON, // VLD1q32LowQPseudo_UPD = 2480
19865	CEFBS_HasNEON, // VLD1q32LowTPseudo_UPD = 2481
19866	CEFBS_HasNEON, // VLD1q32wb_fixed = 2482
19867	CEFBS_HasNEON, // VLD1q32wb_register = 2483
19868	CEFBS_HasNEON, // VLD1q64 = 2484
19869	CEFBS_HasNEON, // VLD1q64HighQPseudo = 2485
19870	CEFBS_HasNEON, // VLD1q64HighTPseudo = 2486
19871	CEFBS_HasNEON, // VLD1q64LowQPseudo_UPD = 2487
19872	CEFBS_HasNEON, // VLD1q64LowTPseudo_UPD = 2488
19873	CEFBS_HasNEON, // VLD1q64wb_fixed = 2489
19874	CEFBS_HasNEON, // VLD1q64wb_register = 2490
19875	CEFBS_HasNEON, // VLD1q8 = 2491
19876	CEFBS_HasNEON, // VLD1q8HighQPseudo = 2492
19877	CEFBS_HasNEON, // VLD1q8HighTPseudo = 2493
19878	CEFBS_HasNEON, // VLD1q8LowQPseudo_UPD = 2494
19879	CEFBS_HasNEON, // VLD1q8LowTPseudo_UPD = 2495
19880	CEFBS_HasNEON, // VLD1q8wb_fixed = 2496
19881	CEFBS_HasNEON, // VLD1q8wb_register = 2497
19882	CEFBS_HasNEON, // VLD2DUPd16 = 2498
19883	CEFBS_HasNEON, // VLD2DUPd16wb_fixed = 2499
19884	CEFBS_HasNEON, // VLD2DUPd16wb_register = 2500
19885	CEFBS_HasNEON, // VLD2DUPd16x2 = 2501
19886	CEFBS_HasNEON, // VLD2DUPd16x2wb_fixed = 2502
19887	CEFBS_HasNEON, // VLD2DUPd16x2wb_register = 2503
19888	CEFBS_HasNEON, // VLD2DUPd32 = 2504
19889	CEFBS_HasNEON, // VLD2DUPd32wb_fixed = 2505
19890	CEFBS_HasNEON, // VLD2DUPd32wb_register = 2506
19891	CEFBS_HasNEON, // VLD2DUPd32x2 = 2507
19892	CEFBS_HasNEON, // VLD2DUPd32x2wb_fixed = 2508
19893	CEFBS_HasNEON, // VLD2DUPd32x2wb_register = 2509
19894	CEFBS_HasNEON, // VLD2DUPd8 = 2510
19895	CEFBS_HasNEON, // VLD2DUPd8wb_fixed = 2511
19896	CEFBS_HasNEON, // VLD2DUPd8wb_register = 2512
19897	CEFBS_HasNEON, // VLD2DUPd8x2 = 2513
19898	CEFBS_HasNEON, // VLD2DUPd8x2wb_fixed = 2514
19899	CEFBS_HasNEON, // VLD2DUPd8x2wb_register = 2515
19900	CEFBS_HasNEON, // VLD2DUPq16EvenPseudo = 2516
19901	CEFBS_HasNEON, // VLD2DUPq16OddPseudo = 2517
19902	CEFBS_HasNEON, // VLD2DUPq32EvenPseudo = 2518
19903	CEFBS_HasNEON, // VLD2DUPq32OddPseudo = 2519
19904	CEFBS_HasNEON, // VLD2DUPq8EvenPseudo = 2520
19905	CEFBS_HasNEON, // VLD2DUPq8OddPseudo = 2521
19906	CEFBS_HasNEON, // VLD2LNd16 = 2522
19907	CEFBS_HasNEON, // VLD2LNd16Pseudo = 2523
19908	CEFBS_HasNEON, // VLD2LNd16Pseudo_UPD = 2524
19909	CEFBS_HasNEON, // VLD2LNd16_UPD = 2525
19910	CEFBS_HasNEON, // VLD2LNd32 = 2526
19911	CEFBS_HasNEON, // VLD2LNd32Pseudo = 2527
19912	CEFBS_HasNEON, // VLD2LNd32Pseudo_UPD = 2528
19913	CEFBS_HasNEON, // VLD2LNd32_UPD = 2529
19914	CEFBS_HasNEON, // VLD2LNd8 = 2530
19915	CEFBS_HasNEON, // VLD2LNd8Pseudo = 2531
19916	CEFBS_HasNEON, // VLD2LNd8Pseudo_UPD = 2532
19917	CEFBS_HasNEON, // VLD2LNd8_UPD = 2533
19918	CEFBS_HasNEON, // VLD2LNq16 = 2534
19919	CEFBS_HasNEON, // VLD2LNq16Pseudo = 2535
19920	CEFBS_HasNEON, // VLD2LNq16Pseudo_UPD = 2536
19921	CEFBS_HasNEON, // VLD2LNq16_UPD = 2537
19922	CEFBS_HasNEON, // VLD2LNq32 = 2538
19923	CEFBS_HasNEON, // VLD2LNq32Pseudo = 2539
19924	CEFBS_HasNEON, // VLD2LNq32Pseudo_UPD = 2540
19925	CEFBS_HasNEON, // VLD2LNq32_UPD = 2541
19926	CEFBS_HasNEON, // VLD2b16 = 2542
19927	CEFBS_HasNEON, // VLD2b16wb_fixed = 2543
19928	CEFBS_HasNEON, // VLD2b16wb_register = 2544
19929	CEFBS_HasNEON, // VLD2b32 = 2545
19930	CEFBS_HasNEON, // VLD2b32wb_fixed = 2546
19931	CEFBS_HasNEON, // VLD2b32wb_register = 2547
19932	CEFBS_HasNEON, // VLD2b8 = 2548
19933	CEFBS_HasNEON, // VLD2b8wb_fixed = 2549
19934	CEFBS_HasNEON, // VLD2b8wb_register = 2550
19935	CEFBS_HasNEON, // VLD2d16 = 2551
19936	CEFBS_HasNEON, // VLD2d16wb_fixed = 2552
19937	CEFBS_HasNEON, // VLD2d16wb_register = 2553
19938	CEFBS_HasNEON, // VLD2d32 = 2554
19939	CEFBS_HasNEON, // VLD2d32wb_fixed = 2555
19940	CEFBS_HasNEON, // VLD2d32wb_register = 2556
19941	CEFBS_HasNEON, // VLD2d8 = 2557
19942	CEFBS_HasNEON, // VLD2d8wb_fixed = 2558
19943	CEFBS_HasNEON, // VLD2d8wb_register = 2559
19944	CEFBS_HasNEON, // VLD2q16 = 2560
19945	CEFBS_HasNEON, // VLD2q16Pseudo = 2561
19946	CEFBS_HasNEON, // VLD2q16PseudoWB_fixed = 2562
19947	CEFBS_HasNEON, // VLD2q16PseudoWB_register = 2563
19948	CEFBS_HasNEON, // VLD2q16wb_fixed = 2564
19949	CEFBS_HasNEON, // VLD2q16wb_register = 2565
19950	CEFBS_HasNEON, // VLD2q32 = 2566
19951	CEFBS_HasNEON, // VLD2q32Pseudo = 2567
19952	CEFBS_HasNEON, // VLD2q32PseudoWB_fixed = 2568
19953	CEFBS_HasNEON, // VLD2q32PseudoWB_register = 2569
19954	CEFBS_HasNEON, // VLD2q32wb_fixed = 2570
19955	CEFBS_HasNEON, // VLD2q32wb_register = 2571
19956	CEFBS_HasNEON, // VLD2q8 = 2572
19957	CEFBS_HasNEON, // VLD2q8Pseudo = 2573
19958	CEFBS_HasNEON, // VLD2q8PseudoWB_fixed = 2574
19959	CEFBS_HasNEON, // VLD2q8PseudoWB_register = 2575
19960	CEFBS_HasNEON, // VLD2q8wb_fixed = 2576
19961	CEFBS_HasNEON, // VLD2q8wb_register = 2577
19962	CEFBS_HasNEON, // VLD3DUPd16 = 2578
19963	CEFBS_HasNEON, // VLD3DUPd16Pseudo = 2579
19964	CEFBS_HasNEON, // VLD3DUPd16Pseudo_UPD = 2580
19965	CEFBS_HasNEON, // VLD3DUPd16_UPD = 2581
19966	CEFBS_HasNEON, // VLD3DUPd32 = 2582
19967	CEFBS_HasNEON, // VLD3DUPd32Pseudo = 2583
19968	CEFBS_HasNEON, // VLD3DUPd32Pseudo_UPD = 2584
19969	CEFBS_HasNEON, // VLD3DUPd32_UPD = 2585
19970	CEFBS_HasNEON, // VLD3DUPd8 = 2586
19971	CEFBS_HasNEON, // VLD3DUPd8Pseudo = 2587
19972	CEFBS_HasNEON, // VLD3DUPd8Pseudo_UPD = 2588
19973	CEFBS_HasNEON, // VLD3DUPd8_UPD = 2589
19974	CEFBS_HasNEON, // VLD3DUPq16 = 2590
19975	CEFBS_HasNEON, // VLD3DUPq16EvenPseudo = 2591
19976	CEFBS_HasNEON, // VLD3DUPq16OddPseudo = 2592
19977	CEFBS_HasNEON, // VLD3DUPq16_UPD = 2593
19978	CEFBS_HasNEON, // VLD3DUPq32 = 2594
19979	CEFBS_HasNEON, // VLD3DUPq32EvenPseudo = 2595
19980	CEFBS_HasNEON, // VLD3DUPq32OddPseudo = 2596
19981	CEFBS_HasNEON, // VLD3DUPq32_UPD = 2597
19982	CEFBS_HasNEON, // VLD3DUPq8 = 2598
19983	CEFBS_HasNEON, // VLD3DUPq8EvenPseudo = 2599
19984	CEFBS_HasNEON, // VLD3DUPq8OddPseudo = 2600
19985	CEFBS_HasNEON, // VLD3DUPq8_UPD = 2601
19986	CEFBS_HasNEON, // VLD3LNd16 = 2602
19987	CEFBS_HasNEON, // VLD3LNd16Pseudo = 2603
19988	CEFBS_HasNEON, // VLD3LNd16Pseudo_UPD = 2604
19989	CEFBS_HasNEON, // VLD3LNd16_UPD = 2605
19990	CEFBS_HasNEON, // VLD3LNd32 = 2606
19991	CEFBS_HasNEON, // VLD3LNd32Pseudo = 2607
19992	CEFBS_HasNEON, // VLD3LNd32Pseudo_UPD = 2608
19993	CEFBS_HasNEON, // VLD3LNd32_UPD = 2609
19994	CEFBS_HasNEON, // VLD3LNd8 = 2610
19995	CEFBS_HasNEON, // VLD3LNd8Pseudo = 2611
19996	CEFBS_HasNEON, // VLD3LNd8Pseudo_UPD = 2612
19997	CEFBS_HasNEON, // VLD3LNd8_UPD = 2613
19998	CEFBS_HasNEON, // VLD3LNq16 = 2614
19999	CEFBS_HasNEON, // VLD3LNq16Pseudo = 2615
20000	CEFBS_HasNEON, // VLD3LNq16Pseudo_UPD = 2616
20001	CEFBS_HasNEON, // VLD3LNq16_UPD = 2617
20002	CEFBS_HasNEON, // VLD3LNq32 = 2618
20003	CEFBS_HasNEON, // VLD3LNq32Pseudo = 2619
20004	CEFBS_HasNEON, // VLD3LNq32Pseudo_UPD = 2620
20005	CEFBS_HasNEON, // VLD3LNq32_UPD = 2621
20006	CEFBS_HasNEON, // VLD3d16 = 2622
20007	CEFBS_HasNEON, // VLD3d16Pseudo = 2623
20008	CEFBS_HasNEON, // VLD3d16Pseudo_UPD = 2624
20009	CEFBS_HasNEON, // VLD3d16_UPD = 2625
20010	CEFBS_HasNEON, // VLD3d32 = 2626
20011	CEFBS_HasNEON, // VLD3d32Pseudo = 2627
20012	CEFBS_HasNEON, // VLD3d32Pseudo_UPD = 2628
20013	CEFBS_HasNEON, // VLD3d32_UPD = 2629
20014	CEFBS_HasNEON, // VLD3d8 = 2630
20015	CEFBS_HasNEON, // VLD3d8Pseudo = 2631
20016	CEFBS_HasNEON, // VLD3d8Pseudo_UPD = 2632
20017	CEFBS_HasNEON, // VLD3d8_UPD = 2633
20018	CEFBS_HasNEON, // VLD3q16 = 2634
20019	CEFBS_HasNEON, // VLD3q16Pseudo_UPD = 2635
20020	CEFBS_HasNEON, // VLD3q16_UPD = 2636
20021	CEFBS_HasNEON, // VLD3q16oddPseudo = 2637
20022	CEFBS_HasNEON, // VLD3q16oddPseudo_UPD = 2638
20023	CEFBS_HasNEON, // VLD3q32 = 2639
20024	CEFBS_HasNEON, // VLD3q32Pseudo_UPD = 2640
20025	CEFBS_HasNEON, // VLD3q32_UPD = 2641
20026	CEFBS_HasNEON, // VLD3q32oddPseudo = 2642
20027	CEFBS_HasNEON, // VLD3q32oddPseudo_UPD = 2643
20028	CEFBS_HasNEON, // VLD3q8 = 2644
20029	CEFBS_HasNEON, // VLD3q8Pseudo_UPD = 2645
20030	CEFBS_HasNEON, // VLD3q8_UPD = 2646
20031	CEFBS_HasNEON, // VLD3q8oddPseudo = 2647
20032	CEFBS_HasNEON, // VLD3q8oddPseudo_UPD = 2648
20033	CEFBS_HasNEON, // VLD4DUPd16 = 2649
20034	CEFBS_HasNEON, // VLD4DUPd16Pseudo = 2650
20035	CEFBS_HasNEON, // VLD4DUPd16Pseudo_UPD = 2651
20036	CEFBS_HasNEON, // VLD4DUPd16_UPD = 2652
20037	CEFBS_HasNEON, // VLD4DUPd32 = 2653
20038	CEFBS_HasNEON, // VLD4DUPd32Pseudo = 2654
20039	CEFBS_HasNEON, // VLD4DUPd32Pseudo_UPD = 2655
20040	CEFBS_HasNEON, // VLD4DUPd32_UPD = 2656
20041	CEFBS_HasNEON, // VLD4DUPd8 = 2657
20042	CEFBS_HasNEON, // VLD4DUPd8Pseudo = 2658
20043	CEFBS_HasNEON, // VLD4DUPd8Pseudo_UPD = 2659
20044	CEFBS_HasNEON, // VLD4DUPd8_UPD = 2660
20045	CEFBS_HasNEON, // VLD4DUPq16 = 2661
20046	CEFBS_HasNEON, // VLD4DUPq16EvenPseudo = 2662
20047	CEFBS_HasNEON, // VLD4DUPq16OddPseudo = 2663
20048	CEFBS_HasNEON, // VLD4DUPq16_UPD = 2664
20049	CEFBS_HasNEON, // VLD4DUPq32 = 2665
20050	CEFBS_HasNEON, // VLD4DUPq32EvenPseudo = 2666
20051	CEFBS_HasNEON, // VLD4DUPq32OddPseudo = 2667
20052	CEFBS_HasNEON, // VLD4DUPq32_UPD = 2668
20053	CEFBS_HasNEON, // VLD4DUPq8 = 2669
20054	CEFBS_HasNEON, // VLD4DUPq8EvenPseudo = 2670
20055	CEFBS_HasNEON, // VLD4DUPq8OddPseudo = 2671
20056	CEFBS_HasNEON, // VLD4DUPq8_UPD = 2672
20057	CEFBS_HasNEON, // VLD4LNd16 = 2673
20058	CEFBS_HasNEON, // VLD4LNd16Pseudo = 2674
20059	CEFBS_HasNEON, // VLD4LNd16Pseudo_UPD = 2675
20060	CEFBS_HasNEON, // VLD4LNd16_UPD = 2676
20061	CEFBS_HasNEON, // VLD4LNd32 = 2677
20062	CEFBS_HasNEON, // VLD4LNd32Pseudo = 2678
20063	CEFBS_HasNEON, // VLD4LNd32Pseudo_UPD = 2679
20064	CEFBS_HasNEON, // VLD4LNd32_UPD = 2680
20065	CEFBS_HasNEON, // VLD4LNd8 = 2681
20066	CEFBS_HasNEON, // VLD4LNd8Pseudo = 2682
20067	CEFBS_HasNEON, // VLD4LNd8Pseudo_UPD = 2683
20068	CEFBS_HasNEON, // VLD4LNd8_UPD = 2684
20069	CEFBS_HasNEON, // VLD4LNq16 = 2685
20070	CEFBS_HasNEON, // VLD4LNq16Pseudo = 2686
20071	CEFBS_HasNEON, // VLD4LNq16Pseudo_UPD = 2687
20072	CEFBS_HasNEON, // VLD4LNq16_UPD = 2688
20073	CEFBS_HasNEON, // VLD4LNq32 = 2689
20074	CEFBS_HasNEON, // VLD4LNq32Pseudo = 2690
20075	CEFBS_HasNEON, // VLD4LNq32Pseudo_UPD = 2691
20076	CEFBS_HasNEON, // VLD4LNq32_UPD = 2692
20077	CEFBS_HasNEON, // VLD4d16 = 2693
20078	CEFBS_HasNEON, // VLD4d16Pseudo = 2694
20079	CEFBS_HasNEON, // VLD4d16Pseudo_UPD = 2695
20080	CEFBS_HasNEON, // VLD4d16_UPD = 2696
20081	CEFBS_HasNEON, // VLD4d32 = 2697
20082	CEFBS_HasNEON, // VLD4d32Pseudo = 2698
20083	CEFBS_HasNEON, // VLD4d32Pseudo_UPD = 2699
20084	CEFBS_HasNEON, // VLD4d32_UPD = 2700
20085	CEFBS_HasNEON, // VLD4d8 = 2701
20086	CEFBS_HasNEON, // VLD4d8Pseudo = 2702
20087	CEFBS_HasNEON, // VLD4d8Pseudo_UPD = 2703
20088	CEFBS_HasNEON, // VLD4d8_UPD = 2704
20089	CEFBS_HasNEON, // VLD4q16 = 2705
20090	CEFBS_HasNEON, // VLD4q16Pseudo_UPD = 2706
20091	CEFBS_HasNEON, // VLD4q16_UPD = 2707
20092	CEFBS_HasNEON, // VLD4q16oddPseudo = 2708
20093	CEFBS_HasNEON, // VLD4q16oddPseudo_UPD = 2709
20094	CEFBS_HasNEON, // VLD4q32 = 2710
20095	CEFBS_HasNEON, // VLD4q32Pseudo_UPD = 2711
20096	CEFBS_HasNEON, // VLD4q32_UPD = 2712
20097	CEFBS_HasNEON, // VLD4q32oddPseudo = 2713
20098	CEFBS_HasNEON, // VLD4q32oddPseudo_UPD = 2714
20099	CEFBS_HasNEON, // VLD4q8 = 2715
20100	CEFBS_HasNEON, // VLD4q8Pseudo_UPD = 2716
20101	CEFBS_HasNEON, // VLD4q8_UPD = 2717
20102	CEFBS_HasNEON, // VLD4q8oddPseudo = 2718
20103	CEFBS_HasNEON, // VLD4q8oddPseudo_UPD = 2719
20104	CEFBS_HasFPRegs, // VLDMDDB_UPD = 2720
20105	CEFBS_HasFPRegs, // VLDMDIA = 2721
20106	CEFBS_HasFPRegs, // VLDMDIA_UPD = 2722
20107	CEFBS_HasVFP2, // VLDMQIA = 2723
20108	CEFBS_HasFPRegs, // VLDMSDB_UPD = 2724
20109	CEFBS_HasFPRegs, // VLDMSIA = 2725
20110	CEFBS_HasFPRegs, // VLDMSIA_UPD = 2726
20111	CEFBS_HasFPRegs, // VLDRD = 2727
20112	CEFBS_HasFPRegs16, // VLDRH = 2728
20113	CEFBS_HasFPRegs, // VLDRS = 2729
20114	CEFBS_HasV8_1MMainline_Has8MSecExt, // VLDR_FPCXTNS_off = 2730
20115	CEFBS_HasV8_1MMainline_Has8MSecExt, // VLDR_FPCXTNS_post = 2731
20116	CEFBS_HasV8_1MMainline_Has8MSecExt, // VLDR_FPCXTNS_pre = 2732
20117	CEFBS_HasV8_1MMainline_Has8MSecExt, // VLDR_FPCXTS_off = 2733
20118	CEFBS_HasV8_1MMainline_Has8MSecExt, // VLDR_FPCXTS_post = 2734
20119	CEFBS_HasV8_1MMainline_Has8MSecExt, // VLDR_FPCXTS_pre = 2735
20120	CEFBS_HasFPRegs_HasV8_1MMainline, // VLDR_FPSCR_NZCVQC_off = 2736
20121	CEFBS_HasFPRegs_HasV8_1MMainline, // VLDR_FPSCR_NZCVQC_post = 2737
20122	CEFBS_HasFPRegs_HasV8_1MMainline, // VLDR_FPSCR_NZCVQC_pre = 2738
20123	CEFBS_HasFPRegs_HasV8_1MMainline, // VLDR_FPSCR_off = 2739
20124	CEFBS_HasFPRegs_HasV8_1MMainline, // VLDR_FPSCR_post = 2740
20125	CEFBS_HasFPRegs_HasV8_1MMainline, // VLDR_FPSCR_pre = 2741
20126	CEFBS_HasV8_1MMainline_HasMVEInt, // VLDR_P0_off = 2742
20127	CEFBS_HasV8_1MMainline_HasMVEInt, // VLDR_P0_post = 2743
20128	CEFBS_HasV8_1MMainline_HasMVEInt, // VLDR_P0_pre = 2744
20129	CEFBS_HasV8_1MMainline_HasMVEInt, // VLDR_VPR_off = 2745
20130	CEFBS_HasV8_1MMainline_HasMVEInt, // VLDR_VPR_post = 2746
20131	CEFBS_HasV8_1MMainline_HasMVEInt, // VLDR_VPR_pre = 2747
20132	CEFBS_HasV8MMainline_Has8MSecExt, // VLLDM = 2748
20133	CEFBS_HasV8MMainline_Has8MSecExt, // VLSTM = 2749
20134	CEFBS_HasNEON, // VMAXfd = 2750
20135	CEFBS_HasNEON, // VMAXfq = 2751
20136	CEFBS_HasNEON_HasFullFP16, // VMAXhd = 2752
20137	CEFBS_HasNEON_HasFullFP16, // VMAXhq = 2753
20138	CEFBS_HasNEON, // VMAXsv16i8 = 2754
20139	CEFBS_HasNEON, // VMAXsv2i32 = 2755
20140	CEFBS_HasNEON, // VMAXsv4i16 = 2756
20141	CEFBS_HasNEON, // VMAXsv4i32 = 2757
20142	CEFBS_HasNEON, // VMAXsv8i16 = 2758
20143	CEFBS_HasNEON, // VMAXsv8i8 = 2759
20144	CEFBS_HasNEON, // VMAXuv16i8 = 2760
20145	CEFBS_HasNEON, // VMAXuv2i32 = 2761
20146	CEFBS_HasNEON, // VMAXuv4i16 = 2762
20147	CEFBS_HasNEON, // VMAXuv4i32 = 2763
20148	CEFBS_HasNEON, // VMAXuv8i16 = 2764
20149	CEFBS_HasNEON, // VMAXuv8i8 = 2765
20150	CEFBS_HasNEON, // VMINfd = 2766
20151	CEFBS_HasNEON, // VMINfq = 2767
20152	CEFBS_HasNEON_HasFullFP16, // VMINhd = 2768
20153	CEFBS_HasNEON_HasFullFP16, // VMINhq = 2769
20154	CEFBS_HasNEON, // VMINsv16i8 = 2770
20155	CEFBS_HasNEON, // VMINsv2i32 = 2771
20156	CEFBS_HasNEON, // VMINsv4i16 = 2772
20157	CEFBS_HasNEON, // VMINsv4i32 = 2773
20158	CEFBS_HasNEON, // VMINsv8i16 = 2774
20159	CEFBS_HasNEON, // VMINsv8i8 = 2775
20160	CEFBS_HasNEON, // VMINuv16i8 = 2776
20161	CEFBS_HasNEON, // VMINuv2i32 = 2777
20162	CEFBS_HasNEON, // VMINuv4i16 = 2778
20163	CEFBS_HasNEON, // VMINuv4i32 = 2779
20164	CEFBS_HasNEON, // VMINuv8i16 = 2780
20165	CEFBS_HasNEON, // VMINuv8i8 = 2781
20166	CEFBS_HasVFP2_HasDPVFP, // VMLAD = 2782
20167	CEFBS_HasFullFP16, // VMLAH = 2783
20168	CEFBS_HasNEON, // VMLALslsv2i32 = 2784
20169	CEFBS_HasNEON, // VMLALslsv4i16 = 2785
20170	CEFBS_HasNEON, // VMLALsluv2i32 = 2786
20171	CEFBS_HasNEON, // VMLALsluv4i16 = 2787
20172	CEFBS_HasNEON, // VMLALsv2i64 = 2788
20173	CEFBS_HasNEON, // VMLALsv4i32 = 2789
20174	CEFBS_HasNEON, // VMLALsv8i16 = 2790
20175	CEFBS_HasNEON, // VMLALuv2i64 = 2791
20176	CEFBS_HasNEON, // VMLALuv4i32 = 2792
20177	CEFBS_HasNEON, // VMLALuv8i16 = 2793
20178	CEFBS_HasVFP2, // VMLAS = 2794
20179	CEFBS_HasNEON, // VMLAfd = 2795
20180	CEFBS_HasNEON, // VMLAfq = 2796
20181	CEFBS_HasNEON_HasFullFP16, // VMLAhd = 2797
20182	CEFBS_HasNEON_HasFullFP16, // VMLAhq = 2798
20183	CEFBS_HasNEON, // VMLAslfd = 2799
20184	CEFBS_HasNEON, // VMLAslfq = 2800
20185	CEFBS_HasNEON_HasFullFP16, // VMLAslhd = 2801
20186	CEFBS_HasNEON_HasFullFP16, // VMLAslhq = 2802
20187	CEFBS_HasNEON, // VMLAslv2i32 = 2803
20188	CEFBS_HasNEON, // VMLAslv4i16 = 2804
20189	CEFBS_HasNEON, // VMLAslv4i32 = 2805
20190	CEFBS_HasNEON, // VMLAslv8i16 = 2806
20191	CEFBS_HasNEON, // VMLAv16i8 = 2807
20192	CEFBS_HasNEON, // VMLAv2i32 = 2808
20193	CEFBS_HasNEON, // VMLAv4i16 = 2809
20194	CEFBS_HasNEON, // VMLAv4i32 = 2810
20195	CEFBS_HasNEON, // VMLAv8i16 = 2811
20196	CEFBS_HasNEON, // VMLAv8i8 = 2812
20197	CEFBS_HasVFP2_HasDPVFP, // VMLSD = 2813
20198	CEFBS_HasFullFP16, // VMLSH = 2814
20199	CEFBS_HasNEON, // VMLSLslsv2i32 = 2815
20200	CEFBS_HasNEON, // VMLSLslsv4i16 = 2816
20201	CEFBS_HasNEON, // VMLSLsluv2i32 = 2817
20202	CEFBS_HasNEON, // VMLSLsluv4i16 = 2818
20203	CEFBS_HasNEON, // VMLSLsv2i64 = 2819
20204	CEFBS_HasNEON, // VMLSLsv4i32 = 2820
20205	CEFBS_HasNEON, // VMLSLsv8i16 = 2821
20206	CEFBS_HasNEON, // VMLSLuv2i64 = 2822
20207	CEFBS_HasNEON, // VMLSLuv4i32 = 2823
20208	CEFBS_HasNEON, // VMLSLuv8i16 = 2824
20209	CEFBS_HasVFP2, // VMLSS = 2825
20210	CEFBS_HasNEON, // VMLSfd = 2826
20211	CEFBS_HasNEON, // VMLSfq = 2827
20212	CEFBS_HasNEON_HasFullFP16, // VMLShd = 2828
20213	CEFBS_HasNEON_HasFullFP16, // VMLShq = 2829
20214	CEFBS_HasNEON, // VMLSslfd = 2830
20215	CEFBS_HasNEON, // VMLSslfq = 2831
20216	CEFBS_HasNEON_HasFullFP16, // VMLSslhd = 2832
20217	CEFBS_HasNEON_HasFullFP16, // VMLSslhq = 2833
20218	CEFBS_HasNEON, // VMLSslv2i32 = 2834
20219	CEFBS_HasNEON, // VMLSslv4i16 = 2835
20220	CEFBS_HasNEON, // VMLSslv4i32 = 2836
20221	CEFBS_HasNEON, // VMLSslv8i16 = 2837
20222	CEFBS_HasNEON, // VMLSv16i8 = 2838
20223	CEFBS_HasNEON, // VMLSv2i32 = 2839
20224	CEFBS_HasNEON, // VMLSv4i16 = 2840
20225	CEFBS_HasNEON, // VMLSv4i32 = 2841
20226	CEFBS_HasNEON, // VMLSv8i16 = 2842
20227	CEFBS_HasNEON, // VMLSv8i8 = 2843
20228	CEFBS_HasBF16_HasNEON, // VMMLA = 2844
20229	CEFBS_HasFPRegs64, // VMOVD = 2845
20230	CEFBS_HasFPRegs, // VMOVDRR = 2846
20231	CEFBS_HasFullFP16, // VMOVH = 2847
20232	CEFBS_HasFPRegs16, // VMOVHR = 2848
20233	CEFBS_HasNEON, // VMOVLsv2i64 = 2849
20234	CEFBS_HasNEON, // VMOVLsv4i32 = 2850
20235	CEFBS_HasNEON, // VMOVLsv8i16 = 2851
20236	CEFBS_HasNEON, // VMOVLuv2i64 = 2852
20237	CEFBS_HasNEON, // VMOVLuv4i32 = 2853
20238	CEFBS_HasNEON, // VMOVLuv8i16 = 2854
20239	CEFBS_HasNEON, // VMOVNv2i32 = 2855
20240	CEFBS_HasNEON, // VMOVNv4i16 = 2856
20241	CEFBS_HasNEON, // VMOVNv8i8 = 2857
20242	CEFBS_HasFPRegs16, // VMOVRH = 2858
20243	CEFBS_HasFPRegs, // VMOVRRD = 2859
20244	CEFBS_HasFPRegs, // VMOVRRS = 2860
20245	CEFBS_HasFPRegs, // VMOVRS = 2861
20246	CEFBS_HasFPRegs, // VMOVS = 2862
20247	CEFBS_HasFPRegs, // VMOVSR = 2863
20248	CEFBS_HasFPRegs, // VMOVSRR = 2864
20249	CEFBS_HasNEON, // VMOVv16i8 = 2865
20250	CEFBS_HasNEON, // VMOVv1i64 = 2866
20251	CEFBS_HasNEON, // VMOVv2f32 = 2867
20252	CEFBS_HasNEON, // VMOVv2i32 = 2868
20253	CEFBS_HasNEON, // VMOVv2i64 = 2869
20254	CEFBS_HasNEON, // VMOVv4f32 = 2870
20255	CEFBS_HasNEON, // VMOVv4i16 = 2871
20256	CEFBS_HasNEON, // VMOVv4i32 = 2872
20257	CEFBS_HasNEON, // VMOVv8i16 = 2873
20258	CEFBS_HasNEON, // VMOVv8i8 = 2874
20259	CEFBS_HasFPRegs, // VMRS = 2875
20260	CEFBS_HasV8_1MMainline_Has8MSecExt, // VMRS_FPCXTNS = 2876
20261	CEFBS_HasV8_1MMainline_Has8MSecExt, // VMRS_FPCXTS = 2877
20262	CEFBS_HasVFP2, // VMRS_FPEXC = 2878
20263	CEFBS_HasVFP2, // VMRS_FPINST = 2879
20264	CEFBS_HasVFP2, // VMRS_FPINST2 = 2880
20265	CEFBS_HasV8_1MMainline_HasFPRegs, // VMRS_FPSCR_NZCVQC = 2881
20266	CEFBS_HasVFP2, // VMRS_FPSID = 2882
20267	CEFBS_HasVFP2, // VMRS_MVFR0 = 2883
20268	CEFBS_HasVFP2, // VMRS_MVFR1 = 2884
20269	CEFBS_HasFPARMv8, // VMRS_MVFR2 = 2885
20270	CEFBS_HasV8_1MMainline_HasMVEInt, // VMRS_P0 = 2886
20271	CEFBS_HasV8_1MMainline_HasMVEInt, // VMRS_VPR = 2887
20272	CEFBS_HasFPRegs, // VMSR = 2888
20273	CEFBS_HasV8_1MMainline_Has8MSecExt, // VMSR_FPCXTNS = 2889
20274	CEFBS_HasV8_1MMainline_Has8MSecExt, // VMSR_FPCXTS = 2890
20275	CEFBS_HasVFP2, // VMSR_FPEXC = 2891
20276	CEFBS_HasVFP2, // VMSR_FPINST = 2892
20277	CEFBS_HasVFP2, // VMSR_FPINST2 = 2893
20278	CEFBS_HasV8_1MMainline_HasFPRegs, // VMSR_FPSCR_NZCVQC = 2894
20279	CEFBS_HasVFP2, // VMSR_FPSID = 2895
20280	CEFBS_HasV8_1MMainline_HasMVEInt, // VMSR_P0 = 2896
20281	CEFBS_HasV8_1MMainline_HasMVEInt, // VMSR_VPR = 2897
20282	CEFBS_HasVFP2_HasDPVFP, // VMULD = 2898
20283	CEFBS_HasFullFP16, // VMULH = 2899
20284	CEFBS_HasV8_HasCrypto, // VMULLp64 = 2900
20285	CEFBS_HasNEON, // VMULLp8 = 2901
20286	CEFBS_HasNEON, // VMULLslsv2i32 = 2902
20287	CEFBS_HasNEON, // VMULLslsv4i16 = 2903
20288	CEFBS_HasNEON, // VMULLsluv2i32 = 2904
20289	CEFBS_HasNEON, // VMULLsluv4i16 = 2905
20290	CEFBS_HasNEON, // VMULLsv2i64 = 2906
20291	CEFBS_HasNEON, // VMULLsv4i32 = 2907
20292	CEFBS_HasNEON, // VMULLsv8i16 = 2908
20293	CEFBS_HasNEON, // VMULLuv2i64 = 2909
20294	CEFBS_HasNEON, // VMULLuv4i32 = 2910
20295	CEFBS_HasNEON, // VMULLuv8i16 = 2911
20296	CEFBS_HasVFP2, // VMULS = 2912
20297	CEFBS_HasNEON, // VMULfd = 2913
20298	CEFBS_HasNEON, // VMULfq = 2914
20299	CEFBS_HasNEON_HasFullFP16, // VMULhd = 2915
20300	CEFBS_HasNEON_HasFullFP16, // VMULhq = 2916
20301	CEFBS_HasNEON, // VMULpd = 2917
20302	CEFBS_HasNEON, // VMULpq = 2918
20303	CEFBS_HasNEON, // VMULslfd = 2919
20304	CEFBS_HasNEON, // VMULslfq = 2920
20305	CEFBS_HasNEON_HasFullFP16, // VMULslhd = 2921
20306	CEFBS_HasNEON_HasFullFP16, // VMULslhq = 2922
20307	CEFBS_HasNEON, // VMULslv2i32 = 2923
20308	CEFBS_HasNEON, // VMULslv4i16 = 2924
20309	CEFBS_HasNEON, // VMULslv4i32 = 2925
20310	CEFBS_HasNEON, // VMULslv8i16 = 2926
20311	CEFBS_HasNEON, // VMULv16i8 = 2927
20312	CEFBS_HasNEON, // VMULv2i32 = 2928
20313	CEFBS_HasNEON, // VMULv4i16 = 2929
20314	CEFBS_HasNEON, // VMULv4i32 = 2930
20315	CEFBS_HasNEON, // VMULv8i16 = 2931
20316	CEFBS_HasNEON, // VMULv8i8 = 2932
20317	CEFBS_HasNEON, // VMVNd = 2933
20318	CEFBS_HasNEON, // VMVNq = 2934
20319	CEFBS_HasNEON, // VMVNv2i32 = 2935
20320	CEFBS_HasNEON, // VMVNv4i16 = 2936
20321	CEFBS_HasNEON, // VMVNv4i32 = 2937
20322	CEFBS_HasNEON, // VMVNv8i16 = 2938
20323	CEFBS_HasVFP2_HasDPVFP, // VNEGD = 2939
20324	CEFBS_HasFullFP16, // VNEGH = 2940
20325	CEFBS_HasVFP2, // VNEGS = 2941
20326	CEFBS_HasNEON, // VNEGf32q = 2942
20327	CEFBS_HasNEON, // VNEGfd = 2943
20328	CEFBS_HasNEON_HasFullFP16, // VNEGhd = 2944
20329	CEFBS_HasNEON_HasFullFP16, // VNEGhq = 2945
20330	CEFBS_HasNEON, // VNEGs16d = 2946
20331	CEFBS_HasNEON, // VNEGs16q = 2947
20332	CEFBS_HasNEON, // VNEGs32d = 2948
20333	CEFBS_HasNEON, // VNEGs32q = 2949
20334	CEFBS_HasNEON, // VNEGs8d = 2950
20335	CEFBS_HasNEON, // VNEGs8q = 2951
20336	CEFBS_HasVFP2_HasDPVFP, // VNMLAD = 2952
20337	CEFBS_HasFullFP16, // VNMLAH = 2953
20338	CEFBS_HasVFP2, // VNMLAS = 2954
20339	CEFBS_HasVFP2_HasDPVFP, // VNMLSD = 2955
20340	CEFBS_HasFullFP16, // VNMLSH = 2956
20341	CEFBS_HasVFP2, // VNMLSS = 2957
20342	CEFBS_HasVFP2_HasDPVFP, // VNMULD = 2958
20343	CEFBS_HasFullFP16, // VNMULH = 2959
20344	CEFBS_HasVFP2, // VNMULS = 2960
20345	CEFBS_HasNEON, // VORNd = 2961
20346	CEFBS_HasNEON, // VORNq = 2962
20347	CEFBS_HasNEON, // VORRd = 2963
20348	CEFBS_HasNEON, // VORRiv2i32 = 2964
20349	CEFBS_HasNEON, // VORRiv4i16 = 2965
20350	CEFBS_HasNEON, // VORRiv4i32 = 2966
20351	CEFBS_HasNEON, // VORRiv8i16 = 2967
20352	CEFBS_HasNEON, // VORRq = 2968
20353	CEFBS_HasNEON, // VPADALsv16i8 = 2969
20354	CEFBS_HasNEON, // VPADALsv2i32 = 2970
20355	CEFBS_HasNEON, // VPADALsv4i16 = 2971
20356	CEFBS_HasNEON, // VPADALsv4i32 = 2972
20357	CEFBS_HasNEON, // VPADALsv8i16 = 2973
20358	CEFBS_HasNEON, // VPADALsv8i8 = 2974
20359	CEFBS_HasNEON, // VPADALuv16i8 = 2975
20360	CEFBS_HasNEON, // VPADALuv2i32 = 2976
20361	CEFBS_HasNEON, // VPADALuv4i16 = 2977
20362	CEFBS_HasNEON, // VPADALuv4i32 = 2978
20363	CEFBS_HasNEON, // VPADALuv8i16 = 2979
20364	CEFBS_HasNEON, // VPADALuv8i8 = 2980
20365	CEFBS_HasNEON, // VPADDLsv16i8 = 2981
20366	CEFBS_HasNEON, // VPADDLsv2i32 = 2982
20367	CEFBS_HasNEON, // VPADDLsv4i16 = 2983
20368	CEFBS_HasNEON, // VPADDLsv4i32 = 2984
20369	CEFBS_HasNEON, // VPADDLsv8i16 = 2985
20370	CEFBS_HasNEON, // VPADDLsv8i8 = 2986
20371	CEFBS_HasNEON, // VPADDLuv16i8 = 2987
20372	CEFBS_HasNEON, // VPADDLuv2i32 = 2988
20373	CEFBS_HasNEON, // VPADDLuv4i16 = 2989
20374	CEFBS_HasNEON, // VPADDLuv4i32 = 2990
20375	CEFBS_HasNEON, // VPADDLuv8i16 = 2991
20376	CEFBS_HasNEON, // VPADDLuv8i8 = 2992
20377	CEFBS_HasNEON, // VPADDf = 2993
20378	CEFBS_HasNEON_HasFullFP16, // VPADDh = 2994
20379	CEFBS_HasNEON, // VPADDi16 = 2995
20380	CEFBS_HasNEON, // VPADDi32 = 2996
20381	CEFBS_HasNEON, // VPADDi8 = 2997
20382	CEFBS_HasNEON, // VPMAXf = 2998
20383	CEFBS_HasNEON_HasFullFP16, // VPMAXh = 2999
20384	CEFBS_HasNEON, // VPMAXs16 = 3000
20385	CEFBS_HasNEON, // VPMAXs32 = 3001
20386	CEFBS_HasNEON, // VPMAXs8 = 3002
20387	CEFBS_HasNEON, // VPMAXu16 = 3003
20388	CEFBS_HasNEON, // VPMAXu32 = 3004
20389	CEFBS_HasNEON, // VPMAXu8 = 3005
20390	CEFBS_HasNEON, // VPMINf = 3006
20391	CEFBS_HasNEON_HasFullFP16, // VPMINh = 3007
20392	CEFBS_HasNEON, // VPMINs16 = 3008
20393	CEFBS_HasNEON, // VPMINs32 = 3009
20394	CEFBS_HasNEON, // VPMINs8 = 3010
20395	CEFBS_HasNEON, // VPMINu16 = 3011
20396	CEFBS_HasNEON, // VPMINu32 = 3012
20397	CEFBS_HasNEON, // VPMINu8 = 3013
20398	CEFBS_HasNEON, // VQABSv16i8 = 3014
20399	CEFBS_HasNEON, // VQABSv2i32 = 3015
20400	CEFBS_HasNEON, // VQABSv4i16 = 3016
20401	CEFBS_HasNEON, // VQABSv4i32 = 3017
20402	CEFBS_HasNEON, // VQABSv8i16 = 3018
20403	CEFBS_HasNEON, // VQABSv8i8 = 3019
20404	CEFBS_HasNEON, // VQADDsv16i8 = 3020
20405	CEFBS_HasNEON, // VQADDsv1i64 = 3021
20406	CEFBS_HasNEON, // VQADDsv2i32 = 3022
20407	CEFBS_HasNEON, // VQADDsv2i64 = 3023
20408	CEFBS_HasNEON, // VQADDsv4i16 = 3024
20409	CEFBS_HasNEON, // VQADDsv4i32 = 3025
20410	CEFBS_HasNEON, // VQADDsv8i16 = 3026
20411	CEFBS_HasNEON, // VQADDsv8i8 = 3027
20412	CEFBS_HasNEON, // VQADDuv16i8 = 3028
20413	CEFBS_HasNEON, // VQADDuv1i64 = 3029
20414	CEFBS_HasNEON, // VQADDuv2i32 = 3030
20415	CEFBS_HasNEON, // VQADDuv2i64 = 3031
20416	CEFBS_HasNEON, // VQADDuv4i16 = 3032
20417	CEFBS_HasNEON, // VQADDuv4i32 = 3033
20418	CEFBS_HasNEON, // VQADDuv8i16 = 3034
20419	CEFBS_HasNEON, // VQADDuv8i8 = 3035
20420	CEFBS_HasNEON, // VQDMLALslv2i32 = 3036
20421	CEFBS_HasNEON, // VQDMLALslv4i16 = 3037
20422	CEFBS_HasNEON, // VQDMLALv2i64 = 3038
20423	CEFBS_HasNEON, // VQDMLALv4i32 = 3039
20424	CEFBS_HasNEON, // VQDMLSLslv2i32 = 3040
20425	CEFBS_HasNEON, // VQDMLSLslv4i16 = 3041
20426	CEFBS_HasNEON, // VQDMLSLv2i64 = 3042
20427	CEFBS_HasNEON, // VQDMLSLv4i32 = 3043
20428	CEFBS_HasNEON, // VQDMULHslv2i32 = 3044
20429	CEFBS_HasNEON, // VQDMULHslv4i16 = 3045
20430	CEFBS_HasNEON, // VQDMULHslv4i32 = 3046
20431	CEFBS_HasNEON, // VQDMULHslv8i16 = 3047
20432	CEFBS_HasNEON, // VQDMULHv2i32 = 3048
20433	CEFBS_HasNEON, // VQDMULHv4i16 = 3049
20434	CEFBS_HasNEON, // VQDMULHv4i32 = 3050
20435	CEFBS_HasNEON, // VQDMULHv8i16 = 3051
20436	CEFBS_HasNEON, // VQDMULLslv2i32 = 3052
20437	CEFBS_HasNEON, // VQDMULLslv4i16 = 3053
20438	CEFBS_HasNEON, // VQDMULLv2i64 = 3054
20439	CEFBS_HasNEON, // VQDMULLv4i32 = 3055
20440	CEFBS_HasNEON, // VQMOVNsuv2i32 = 3056
20441	CEFBS_HasNEON, // VQMOVNsuv4i16 = 3057
20442	CEFBS_HasNEON, // VQMOVNsuv8i8 = 3058
20443	CEFBS_HasNEON, // VQMOVNsv2i32 = 3059
20444	CEFBS_HasNEON, // VQMOVNsv4i16 = 3060
20445	CEFBS_HasNEON, // VQMOVNsv8i8 = 3061
20446	CEFBS_HasNEON, // VQMOVNuv2i32 = 3062
20447	CEFBS_HasNEON, // VQMOVNuv4i16 = 3063
20448	CEFBS_HasNEON, // VQMOVNuv8i8 = 3064
20449	CEFBS_HasNEON, // VQNEGv16i8 = 3065
20450	CEFBS_HasNEON, // VQNEGv2i32 = 3066
20451	CEFBS_HasNEON, // VQNEGv4i16 = 3067
20452	CEFBS_HasNEON, // VQNEGv4i32 = 3068
20453	CEFBS_HasNEON, // VQNEGv8i16 = 3069
20454	CEFBS_HasNEON, // VQNEGv8i8 = 3070
20455	CEFBS_HasNEON_HasV8_1a, // VQRDMLAHslv2i32 = 3071
20456	CEFBS_HasNEON_HasV8_1a, // VQRDMLAHslv4i16 = 3072
20457	CEFBS_HasNEON_HasV8_1a, // VQRDMLAHslv4i32 = 3073
20458	CEFBS_HasNEON_HasV8_1a, // VQRDMLAHslv8i16 = 3074
20459	CEFBS_HasNEON_HasV8_1a, // VQRDMLAHv2i32 = 3075
20460	CEFBS_HasNEON_HasV8_1a, // VQRDMLAHv4i16 = 3076
20461	CEFBS_HasNEON_HasV8_1a, // VQRDMLAHv4i32 = 3077
20462	CEFBS_HasNEON_HasV8_1a, // VQRDMLAHv8i16 = 3078
20463	CEFBS_HasNEON_HasV8_1a, // VQRDMLSHslv2i32 = 3079
20464	CEFBS_HasNEON_HasV8_1a, // VQRDMLSHslv4i16 = 3080
20465	CEFBS_HasNEON_HasV8_1a, // VQRDMLSHslv4i32 = 3081
20466	CEFBS_HasNEON_HasV8_1a, // VQRDMLSHslv8i16 = 3082
20467	CEFBS_HasNEON_HasV8_1a, // VQRDMLSHv2i32 = 3083
20468	CEFBS_HasNEON_HasV8_1a, // VQRDMLSHv4i16 = 3084
20469	CEFBS_HasNEON_HasV8_1a, // VQRDMLSHv4i32 = 3085
20470	CEFBS_HasNEON_HasV8_1a, // VQRDMLSHv8i16 = 3086
20471	CEFBS_HasNEON, // VQRDMULHslv2i32 = 3087
20472	CEFBS_HasNEON, // VQRDMULHslv4i16 = 3088
20473	CEFBS_HasNEON, // VQRDMULHslv4i32 = 3089
20474	CEFBS_HasNEON, // VQRDMULHslv8i16 = 3090
20475	CEFBS_HasNEON, // VQRDMULHv2i32 = 3091
20476	CEFBS_HasNEON, // VQRDMULHv4i16 = 3092
20477	CEFBS_HasNEON, // VQRDMULHv4i32 = 3093
20478	CEFBS_HasNEON, // VQRDMULHv8i16 = 3094
20479	CEFBS_HasNEON, // VQRSHLsv16i8 = 3095
20480	CEFBS_HasNEON, // VQRSHLsv1i64 = 3096
20481	CEFBS_HasNEON, // VQRSHLsv2i32 = 3097
20482	CEFBS_HasNEON, // VQRSHLsv2i64 = 3098
20483	CEFBS_HasNEON, // VQRSHLsv4i16 = 3099
20484	CEFBS_HasNEON, // VQRSHLsv4i32 = 3100
20485	CEFBS_HasNEON, // VQRSHLsv8i16 = 3101
20486	CEFBS_HasNEON, // VQRSHLsv8i8 = 3102
20487	CEFBS_HasNEON, // VQRSHLuv16i8 = 3103
20488	CEFBS_HasNEON, // VQRSHLuv1i64 = 3104
20489	CEFBS_HasNEON, // VQRSHLuv2i32 = 3105
20490	CEFBS_HasNEON, // VQRSHLuv2i64 = 3106
20491	CEFBS_HasNEON, // VQRSHLuv4i16 = 3107
20492	CEFBS_HasNEON, // VQRSHLuv4i32 = 3108
20493	CEFBS_HasNEON, // VQRSHLuv8i16 = 3109
20494	CEFBS_HasNEON, // VQRSHLuv8i8 = 3110
20495	CEFBS_HasNEON, // VQRSHRNsv2i32 = 3111
20496	CEFBS_HasNEON, // VQRSHRNsv4i16 = 3112
20497	CEFBS_HasNEON, // VQRSHRNsv8i8 = 3113
20498	CEFBS_HasNEON, // VQRSHRNuv2i32 = 3114
20499	CEFBS_HasNEON, // VQRSHRNuv4i16 = 3115
20500	CEFBS_HasNEON, // VQRSHRNuv8i8 = 3116
20501	CEFBS_HasNEON, // VQRSHRUNv2i32 = 3117
20502	CEFBS_HasNEON, // VQRSHRUNv4i16 = 3118
20503	CEFBS_HasNEON, // VQRSHRUNv8i8 = 3119
20504	CEFBS_HasNEON, // VQSHLsiv16i8 = 3120
20505	CEFBS_HasNEON, // VQSHLsiv1i64 = 3121
20506	CEFBS_HasNEON, // VQSHLsiv2i32 = 3122
20507	CEFBS_HasNEON, // VQSHLsiv2i64 = 3123
20508	CEFBS_HasNEON, // VQSHLsiv4i16 = 3124
20509	CEFBS_HasNEON, // VQSHLsiv4i32 = 3125
20510	CEFBS_HasNEON, // VQSHLsiv8i16 = 3126
20511	CEFBS_HasNEON, // VQSHLsiv8i8 = 3127
20512	CEFBS_HasNEON, // VQSHLsuv16i8 = 3128
20513	CEFBS_HasNEON, // VQSHLsuv1i64 = 3129
20514	CEFBS_HasNEON, // VQSHLsuv2i32 = 3130
20515	CEFBS_HasNEON, // VQSHLsuv2i64 = 3131
20516	CEFBS_HasNEON, // VQSHLsuv4i16 = 3132
20517	CEFBS_HasNEON, // VQSHLsuv4i32 = 3133
20518	CEFBS_HasNEON, // VQSHLsuv8i16 = 3134
20519	CEFBS_HasNEON, // VQSHLsuv8i8 = 3135
20520	CEFBS_HasNEON, // VQSHLsv16i8 = 3136
20521	CEFBS_HasNEON, // VQSHLsv1i64 = 3137
20522	CEFBS_HasNEON, // VQSHLsv2i32 = 3138
20523	CEFBS_HasNEON, // VQSHLsv2i64 = 3139
20524	CEFBS_HasNEON, // VQSHLsv4i16 = 3140
20525	CEFBS_HasNEON, // VQSHLsv4i32 = 3141
20526	CEFBS_HasNEON, // VQSHLsv8i16 = 3142
20527	CEFBS_HasNEON, // VQSHLsv8i8 = 3143
20528	CEFBS_HasNEON, // VQSHLuiv16i8 = 3144
20529	CEFBS_HasNEON, // VQSHLuiv1i64 = 3145
20530	CEFBS_HasNEON, // VQSHLuiv2i32 = 3146
20531	CEFBS_HasNEON, // VQSHLuiv2i64 = 3147
20532	CEFBS_HasNEON, // VQSHLuiv4i16 = 3148
20533	CEFBS_HasNEON, // VQSHLuiv4i32 = 3149
20534	CEFBS_HasNEON, // VQSHLuiv8i16 = 3150
20535	CEFBS_HasNEON, // VQSHLuiv8i8 = 3151
20536	CEFBS_HasNEON, // VQSHLuv16i8 = 3152
20537	CEFBS_HasNEON, // VQSHLuv1i64 = 3153
20538	CEFBS_HasNEON, // VQSHLuv2i32 = 3154
20539	CEFBS_HasNEON, // VQSHLuv2i64 = 3155
20540	CEFBS_HasNEON, // VQSHLuv4i16 = 3156
20541	CEFBS_HasNEON, // VQSHLuv4i32 = 3157
20542	CEFBS_HasNEON, // VQSHLuv8i16 = 3158
20543	CEFBS_HasNEON, // VQSHLuv8i8 = 3159
20544	CEFBS_HasNEON, // VQSHRNsv2i32 = 3160
20545	CEFBS_HasNEON, // VQSHRNsv4i16 = 3161
20546	CEFBS_HasNEON, // VQSHRNsv8i8 = 3162
20547	CEFBS_HasNEON, // VQSHRNuv2i32 = 3163
20548	CEFBS_HasNEON, // VQSHRNuv4i16 = 3164
20549	CEFBS_HasNEON, // VQSHRNuv8i8 = 3165
20550	CEFBS_HasNEON, // VQSHRUNv2i32 = 3166
20551	CEFBS_HasNEON, // VQSHRUNv4i16 = 3167
20552	CEFBS_HasNEON, // VQSHRUNv8i8 = 3168
20553	CEFBS_HasNEON, // VQSUBsv16i8 = 3169
20554	CEFBS_HasNEON, // VQSUBsv1i64 = 3170
20555	CEFBS_HasNEON, // VQSUBsv2i32 = 3171
20556	CEFBS_HasNEON, // VQSUBsv2i64 = 3172
20557	CEFBS_HasNEON, // VQSUBsv4i16 = 3173
20558	CEFBS_HasNEON, // VQSUBsv4i32 = 3174
20559	CEFBS_HasNEON, // VQSUBsv8i16 = 3175
20560	CEFBS_HasNEON, // VQSUBsv8i8 = 3176
20561	CEFBS_HasNEON, // VQSUBuv16i8 = 3177
20562	CEFBS_HasNEON, // VQSUBuv1i64 = 3178
20563	CEFBS_HasNEON, // VQSUBuv2i32 = 3179
20564	CEFBS_HasNEON, // VQSUBuv2i64 = 3180
20565	CEFBS_HasNEON, // VQSUBuv4i16 = 3181
20566	CEFBS_HasNEON, // VQSUBuv4i32 = 3182
20567	CEFBS_HasNEON, // VQSUBuv8i16 = 3183
20568	CEFBS_HasNEON, // VQSUBuv8i8 = 3184
20569	CEFBS_HasNEON, // VRADDHNv2i32 = 3185
20570	CEFBS_HasNEON, // VRADDHNv4i16 = 3186
20571	CEFBS_HasNEON, // VRADDHNv8i8 = 3187
20572	CEFBS_HasNEON, // VRECPEd = 3188
20573	CEFBS_HasNEON, // VRECPEfd = 3189
20574	CEFBS_HasNEON, // VRECPEfq = 3190
20575	CEFBS_HasNEON_HasFullFP16, // VRECPEhd = 3191
20576	CEFBS_HasNEON_HasFullFP16, // VRECPEhq = 3192
20577	CEFBS_HasNEON, // VRECPEq = 3193
20578	CEFBS_HasNEON, // VRECPSfd = 3194
20579	CEFBS_HasNEON, // VRECPSfq = 3195
20580	CEFBS_HasNEON_HasFullFP16, // VRECPShd = 3196
20581	CEFBS_HasNEON_HasFullFP16, // VRECPShq = 3197
20582	CEFBS_HasNEON, // VREV16d8 = 3198
20583	CEFBS_HasNEON, // VREV16q8 = 3199
20584	CEFBS_HasNEON, // VREV32d16 = 3200
20585	CEFBS_HasNEON, // VREV32d8 = 3201
20586	CEFBS_HasNEON, // VREV32q16 = 3202
20587	CEFBS_HasNEON, // VREV32q8 = 3203
20588	CEFBS_HasNEON, // VREV64d16 = 3204
20589	CEFBS_HasNEON, // VREV64d32 = 3205
20590	CEFBS_HasNEON, // VREV64d8 = 3206
20591	CEFBS_HasNEON, // VREV64q16 = 3207
20592	CEFBS_HasNEON, // VREV64q32 = 3208
20593	CEFBS_HasNEON, // VREV64q8 = 3209
20594	CEFBS_HasNEON, // VRHADDsv16i8 = 3210
20595	CEFBS_HasNEON, // VRHADDsv2i32 = 3211
20596	CEFBS_HasNEON, // VRHADDsv4i16 = 3212
20597	CEFBS_HasNEON, // VRHADDsv4i32 = 3213
20598	CEFBS_HasNEON, // VRHADDsv8i16 = 3214
20599	CEFBS_HasNEON, // VRHADDsv8i8 = 3215
20600	CEFBS_HasNEON, // VRHADDuv16i8 = 3216
20601	CEFBS_HasNEON, // VRHADDuv2i32 = 3217
20602	CEFBS_HasNEON, // VRHADDuv4i16 = 3218
20603	CEFBS_HasNEON, // VRHADDuv4i32 = 3219
20604	CEFBS_HasNEON, // VRHADDuv8i16 = 3220
20605	CEFBS_HasNEON, // VRHADDuv8i8 = 3221
20606	CEFBS_HasFPARMv8_HasDPVFP, // VRINTAD = 3222
20607	CEFBS_HasFullFP16, // VRINTAH = 3223
20608	CEFBS_HasV8_HasNEON, // VRINTANDf = 3224
20609	CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTANDh = 3225
20610	CEFBS_HasV8_HasNEON, // VRINTANQf = 3226
20611	CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTANQh = 3227
20612	CEFBS_HasFPARMv8, // VRINTAS = 3228
20613	CEFBS_HasFPARMv8_HasDPVFP, // VRINTMD = 3229
20614	CEFBS_HasFullFP16, // VRINTMH = 3230
20615	CEFBS_HasV8_HasNEON, // VRINTMNDf = 3231
20616	CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTMNDh = 3232
20617	CEFBS_HasV8_HasNEON, // VRINTMNQf = 3233
20618	CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTMNQh = 3234
20619	CEFBS_HasFPARMv8, // VRINTMS = 3235
20620	CEFBS_HasFPARMv8_HasDPVFP, // VRINTND = 3236
20621	CEFBS_HasFullFP16, // VRINTNH = 3237
20622	CEFBS_HasV8_HasNEON, // VRINTNNDf = 3238
20623	CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTNNDh = 3239
20624	CEFBS_HasV8_HasNEON, // VRINTNNQf = 3240
20625	CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTNNQh = 3241
20626	CEFBS_HasFPARMv8, // VRINTNS = 3242
20627	CEFBS_HasFPARMv8_HasDPVFP, // VRINTPD = 3243
20628	CEFBS_HasFullFP16, // VRINTPH = 3244
20629	CEFBS_HasV8_HasNEON, // VRINTPNDf = 3245
20630	CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTPNDh = 3246
20631	CEFBS_HasV8_HasNEON, // VRINTPNQf = 3247
20632	CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTPNQh = 3248
20633	CEFBS_HasFPARMv8, // VRINTPS = 3249
20634	CEFBS_HasFPARMv8_HasDPVFP, // VRINTRD = 3250
20635	CEFBS_HasFullFP16, // VRINTRH = 3251
20636	CEFBS_HasFPARMv8, // VRINTRS = 3252
20637	CEFBS_HasFPARMv8_HasDPVFP, // VRINTXD = 3253
20638	CEFBS_HasFullFP16, // VRINTXH = 3254
20639	CEFBS_HasV8_HasNEON, // VRINTXNDf = 3255
20640	CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTXNDh = 3256
20641	CEFBS_HasV8_HasNEON, // VRINTXNQf = 3257
20642	CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTXNQh = 3258
20643	CEFBS_HasFPARMv8, // VRINTXS = 3259
20644	CEFBS_HasFPARMv8_HasDPVFP, // VRINTZD = 3260
20645	CEFBS_HasFullFP16, // VRINTZH = 3261
20646	CEFBS_HasV8_HasNEON, // VRINTZNDf = 3262
20647	CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTZNDh = 3263
20648	CEFBS_HasV8_HasNEON, // VRINTZNQf = 3264
20649	CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTZNQh = 3265
20650	CEFBS_HasFPARMv8, // VRINTZS = 3266
20651	CEFBS_HasNEON, // VRSHLsv16i8 = 3267
20652	CEFBS_HasNEON, // VRSHLsv1i64 = 3268
20653	CEFBS_HasNEON, // VRSHLsv2i32 = 3269
20654	CEFBS_HasNEON, // VRSHLsv2i64 = 3270
20655	CEFBS_HasNEON, // VRSHLsv4i16 = 3271
20656	CEFBS_HasNEON, // VRSHLsv4i32 = 3272
20657	CEFBS_HasNEON, // VRSHLsv8i16 = 3273
20658	CEFBS_HasNEON, // VRSHLsv8i8 = 3274
20659	CEFBS_HasNEON, // VRSHLuv16i8 = 3275
20660	CEFBS_HasNEON, // VRSHLuv1i64 = 3276
20661	CEFBS_HasNEON, // VRSHLuv2i32 = 3277
20662	CEFBS_HasNEON, // VRSHLuv2i64 = 3278
20663	CEFBS_HasNEON, // VRSHLuv4i16 = 3279
20664	CEFBS_HasNEON, // VRSHLuv4i32 = 3280
20665	CEFBS_HasNEON, // VRSHLuv8i16 = 3281
20666	CEFBS_HasNEON, // VRSHLuv8i8 = 3282
20667	CEFBS_HasNEON, // VRSHRNv2i32 = 3283
20668	CEFBS_HasNEON, // VRSHRNv4i16 = 3284
20669	CEFBS_HasNEON, // VRSHRNv8i8 = 3285
20670	CEFBS_HasNEON, // VRSHRsv16i8 = 3286
20671	CEFBS_HasNEON, // VRSHRsv1i64 = 3287
20672	CEFBS_HasNEON, // VRSHRsv2i32 = 3288
20673	CEFBS_HasNEON, // VRSHRsv2i64 = 3289
20674	CEFBS_HasNEON, // VRSHRsv4i16 = 3290
20675	CEFBS_HasNEON, // VRSHRsv4i32 = 3291
20676	CEFBS_HasNEON, // VRSHRsv8i16 = 3292
20677	CEFBS_HasNEON, // VRSHRsv8i8 = 3293
20678	CEFBS_HasNEON, // VRSHRuv16i8 = 3294
20679	CEFBS_HasNEON, // VRSHRuv1i64 = 3295
20680	CEFBS_HasNEON, // VRSHRuv2i32 = 3296
20681	CEFBS_HasNEON, // VRSHRuv2i64 = 3297
20682	CEFBS_HasNEON, // VRSHRuv4i16 = 3298
20683	CEFBS_HasNEON, // VRSHRuv4i32 = 3299
20684	CEFBS_HasNEON, // VRSHRuv8i16 = 3300
20685	CEFBS_HasNEON, // VRSHRuv8i8 = 3301
20686	CEFBS_HasNEON, // VRSQRTEd = 3302
20687	CEFBS_HasNEON, // VRSQRTEfd = 3303
20688	CEFBS_HasNEON, // VRSQRTEfq = 3304
20689	CEFBS_HasNEON_HasFullFP16, // VRSQRTEhd = 3305
20690	CEFBS_HasNEON_HasFullFP16, // VRSQRTEhq = 3306
20691	CEFBS_HasNEON, // VRSQRTEq = 3307
20692	CEFBS_HasNEON, // VRSQRTSfd = 3308
20693	CEFBS_HasNEON, // VRSQRTSfq = 3309
20694	CEFBS_HasNEON_HasFullFP16, // VRSQRTShd = 3310
20695	CEFBS_HasNEON_HasFullFP16, // VRSQRTShq = 3311
20696	CEFBS_HasNEON, // VRSRAsv16i8 = 3312
20697	CEFBS_HasNEON, // VRSRAsv1i64 = 3313
20698	CEFBS_HasNEON, // VRSRAsv2i32 = 3314
20699	CEFBS_HasNEON, // VRSRAsv2i64 = 3315
20700	CEFBS_HasNEON, // VRSRAsv4i16 = 3316
20701	CEFBS_HasNEON, // VRSRAsv4i32 = 3317
20702	CEFBS_HasNEON, // VRSRAsv8i16 = 3318
20703	CEFBS_HasNEON, // VRSRAsv8i8 = 3319
20704	CEFBS_HasNEON, // VRSRAuv16i8 = 3320
20705	CEFBS_HasNEON, // VRSRAuv1i64 = 3321
20706	CEFBS_HasNEON, // VRSRAuv2i32 = 3322
20707	CEFBS_HasNEON, // VRSRAuv2i64 = 3323
20708	CEFBS_HasNEON, // VRSRAuv4i16 = 3324
20709	CEFBS_HasNEON, // VRSRAuv4i32 = 3325
20710	CEFBS_HasNEON, // VRSRAuv8i16 = 3326
20711	CEFBS_HasNEON, // VRSRAuv8i8 = 3327
20712	CEFBS_HasNEON, // VRSUBHNv2i32 = 3328
20713	CEFBS_HasNEON, // VRSUBHNv4i16 = 3329
20714	CEFBS_HasNEON, // VRSUBHNv8i8 = 3330
20715	CEFBS_HasV8_1MMainline_Has8MSecExt, // VSCCLRMD = 3331
20716	CEFBS_HasV8_1MMainline_Has8MSecExt, // VSCCLRMS = 3332
20717	CEFBS_HasDotProd, // VSDOTD = 3333
20718	CEFBS_HasDotProd, // VSDOTDI = 3334
20719	CEFBS_HasDotProd, // VSDOTQ = 3335
20720	CEFBS_HasDotProd, // VSDOTQI = 3336
20721	CEFBS_HasFPARMv8_HasDPVFP, // VSELEQD = 3337
20722	CEFBS_HasFullFP16, // VSELEQH = 3338
20723	CEFBS_HasFPARMv8, // VSELEQS = 3339
20724	CEFBS_HasFPARMv8_HasDPVFP, // VSELGED = 3340
20725	CEFBS_HasFullFP16, // VSELGEH = 3341
20726	CEFBS_HasFPARMv8, // VSELGES = 3342
20727	CEFBS_HasFPARMv8_HasDPVFP, // VSELGTD = 3343
20728	CEFBS_HasFullFP16, // VSELGTH = 3344
20729	CEFBS_HasFPARMv8, // VSELGTS = 3345
20730	CEFBS_HasFPARMv8_HasDPVFP, // VSELVSD = 3346
20731	CEFBS_HasFullFP16, // VSELVSH = 3347
20732	CEFBS_HasFPARMv8, // VSELVSS = 3348
20733	CEFBS_HasNEON, // VSETLNi16 = 3349
20734	CEFBS_HasVFP2, // VSETLNi32 = 3350
20735	CEFBS_HasNEON, // VSETLNi8 = 3351
20736	CEFBS_HasNEON, // VSHLLi16 = 3352
20737	CEFBS_HasNEON, // VSHLLi32 = 3353
20738	CEFBS_HasNEON, // VSHLLi8 = 3354
20739	CEFBS_HasNEON, // VSHLLsv2i64 = 3355
20740	CEFBS_HasNEON, // VSHLLsv4i32 = 3356
20741	CEFBS_HasNEON, // VSHLLsv8i16 = 3357
20742	CEFBS_HasNEON, // VSHLLuv2i64 = 3358
20743	CEFBS_HasNEON, // VSHLLuv4i32 = 3359
20744	CEFBS_HasNEON, // VSHLLuv8i16 = 3360
20745	CEFBS_HasNEON, // VSHLiv16i8 = 3361
20746	CEFBS_HasNEON, // VSHLiv1i64 = 3362
20747	CEFBS_HasNEON, // VSHLiv2i32 = 3363
20748	CEFBS_HasNEON, // VSHLiv2i64 = 3364
20749	CEFBS_HasNEON, // VSHLiv4i16 = 3365
20750	CEFBS_HasNEON, // VSHLiv4i32 = 3366
20751	CEFBS_HasNEON, // VSHLiv8i16 = 3367
20752	CEFBS_HasNEON, // VSHLiv8i8 = 3368
20753	CEFBS_HasNEON, // VSHLsv16i8 = 3369
20754	CEFBS_HasNEON, // VSHLsv1i64 = 3370
20755	CEFBS_HasNEON, // VSHLsv2i32 = 3371
20756	CEFBS_HasNEON, // VSHLsv2i64 = 3372
20757	CEFBS_HasNEON, // VSHLsv4i16 = 3373
20758	CEFBS_HasNEON, // VSHLsv4i32 = 3374
20759	CEFBS_HasNEON, // VSHLsv8i16 = 3375
20760	CEFBS_HasNEON, // VSHLsv8i8 = 3376
20761	CEFBS_HasNEON, // VSHLuv16i8 = 3377
20762	CEFBS_HasNEON, // VSHLuv1i64 = 3378
20763	CEFBS_HasNEON, // VSHLuv2i32 = 3379
20764	CEFBS_HasNEON, // VSHLuv2i64 = 3380
20765	CEFBS_HasNEON, // VSHLuv4i16 = 3381
20766	CEFBS_HasNEON, // VSHLuv4i32 = 3382
20767	CEFBS_HasNEON, // VSHLuv8i16 = 3383
20768	CEFBS_HasNEON, // VSHLuv8i8 = 3384
20769	CEFBS_HasNEON, // VSHRNv2i32 = 3385
20770	CEFBS_HasNEON, // VSHRNv4i16 = 3386
20771	CEFBS_HasNEON, // VSHRNv8i8 = 3387
20772	CEFBS_HasNEON, // VSHRsv16i8 = 3388
20773	CEFBS_HasNEON, // VSHRsv1i64 = 3389
20774	CEFBS_HasNEON, // VSHRsv2i32 = 3390
20775	CEFBS_HasNEON, // VSHRsv2i64 = 3391
20776	CEFBS_HasNEON, // VSHRsv4i16 = 3392
20777	CEFBS_HasNEON, // VSHRsv4i32 = 3393
20778	CEFBS_HasNEON, // VSHRsv8i16 = 3394
20779	CEFBS_HasNEON, // VSHRsv8i8 = 3395
20780	CEFBS_HasNEON, // VSHRuv16i8 = 3396
20781	CEFBS_HasNEON, // VSHRuv1i64 = 3397
20782	CEFBS_HasNEON, // VSHRuv2i32 = 3398
20783	CEFBS_HasNEON, // VSHRuv2i64 = 3399
20784	CEFBS_HasNEON, // VSHRuv4i16 = 3400
20785	CEFBS_HasNEON, // VSHRuv4i32 = 3401
20786	CEFBS_HasNEON, // VSHRuv8i16 = 3402
20787	CEFBS_HasNEON, // VSHRuv8i8 = 3403
20788	CEFBS_HasVFP2_HasDPVFP, // VSHTOD = 3404
20789	CEFBS_HasFullFP16, // VSHTOH = 3405
20790	CEFBS_HasVFP2, // VSHTOS = 3406
20791	CEFBS_HasVFP2_HasDPVFP, // VSITOD = 3407
20792	CEFBS_HasFullFP16, // VSITOH = 3408
20793	CEFBS_HasVFP2, // VSITOS = 3409
20794	CEFBS_HasNEON, // VSLIv16i8 = 3410
20795	CEFBS_HasNEON, // VSLIv1i64 = 3411
20796	CEFBS_HasNEON, // VSLIv2i32 = 3412
20797	CEFBS_HasNEON, // VSLIv2i64 = 3413
20798	CEFBS_HasNEON, // VSLIv4i16 = 3414
20799	CEFBS_HasNEON, // VSLIv4i32 = 3415
20800	CEFBS_HasNEON, // VSLIv8i16 = 3416
20801	CEFBS_HasNEON, // VSLIv8i8 = 3417
20802	CEFBS_HasVFP2_HasDPVFP, // VSLTOD = 3418
20803	CEFBS_HasFullFP16, // VSLTOH = 3419
20804	CEFBS_HasVFP2, // VSLTOS = 3420
20805	CEFBS_HasMatMulInt8, // VSMMLA = 3421
20806	CEFBS_HasVFP2_HasDPVFP, // VSQRTD = 3422
20807	CEFBS_HasFullFP16, // VSQRTH = 3423
20808	CEFBS_HasVFP2, // VSQRTS = 3424
20809	CEFBS_HasNEON, // VSRAsv16i8 = 3425
20810	CEFBS_HasNEON, // VSRAsv1i64 = 3426
20811	CEFBS_HasNEON, // VSRAsv2i32 = 3427
20812	CEFBS_HasNEON, // VSRAsv2i64 = 3428
20813	CEFBS_HasNEON, // VSRAsv4i16 = 3429
20814	CEFBS_HasNEON, // VSRAsv4i32 = 3430
20815	CEFBS_HasNEON, // VSRAsv8i16 = 3431
20816	CEFBS_HasNEON, // VSRAsv8i8 = 3432
20817	CEFBS_HasNEON, // VSRAuv16i8 = 3433
20818	CEFBS_HasNEON, // VSRAuv1i64 = 3434
20819	CEFBS_HasNEON, // VSRAuv2i32 = 3435
20820	CEFBS_HasNEON, // VSRAuv2i64 = 3436
20821	CEFBS_HasNEON, // VSRAuv4i16 = 3437
20822	CEFBS_HasNEON, // VSRAuv4i32 = 3438
20823	CEFBS_HasNEON, // VSRAuv8i16 = 3439
20824	CEFBS_HasNEON, // VSRAuv8i8 = 3440
20825	CEFBS_HasNEON, // VSRIv16i8 = 3441
20826	CEFBS_HasNEON, // VSRIv1i64 = 3442
20827	CEFBS_HasNEON, // VSRIv2i32 = 3443
20828	CEFBS_HasNEON, // VSRIv2i64 = 3444
20829	CEFBS_HasNEON, // VSRIv4i16 = 3445
20830	CEFBS_HasNEON, // VSRIv4i32 = 3446
20831	CEFBS_HasNEON, // VSRIv8i16 = 3447
20832	CEFBS_HasNEON, // VSRIv8i8 = 3448
20833	CEFBS_HasNEON, // VST1LNd16 = 3449
20834	CEFBS_HasNEON, // VST1LNd16_UPD = 3450
20835	CEFBS_HasNEON, // VST1LNd32 = 3451
20836	CEFBS_HasNEON, // VST1LNd32_UPD = 3452
20837	CEFBS_HasNEON, // VST1LNd8 = 3453
20838	CEFBS_HasNEON, // VST1LNd8_UPD = 3454
20839	CEFBS_HasNEON, // VST1LNq16Pseudo = 3455
20840	CEFBS_HasNEON, // VST1LNq16Pseudo_UPD = 3456
20841	CEFBS_HasNEON, // VST1LNq32Pseudo = 3457
20842	CEFBS_HasNEON, // VST1LNq32Pseudo_UPD = 3458
20843	CEFBS_HasNEON, // VST1LNq8Pseudo = 3459
20844	CEFBS_HasNEON, // VST1LNq8Pseudo_UPD = 3460
20845	CEFBS_HasNEON, // VST1d16 = 3461
20846	CEFBS_HasNEON, // VST1d16Q = 3462
20847	CEFBS_HasNEON, // VST1d16QPseudo = 3463
20848	CEFBS_HasNEON, // VST1d16Qwb_fixed = 3464
20849	CEFBS_HasNEON, // VST1d16Qwb_register = 3465
20850	CEFBS_HasNEON, // VST1d16T = 3466
20851	CEFBS_HasNEON, // VST1d16TPseudo = 3467
20852	CEFBS_HasNEON, // VST1d16Twb_fixed = 3468
20853	CEFBS_HasNEON, // VST1d16Twb_register = 3469
20854	CEFBS_HasNEON, // VST1d16wb_fixed = 3470
20855	CEFBS_HasNEON, // VST1d16wb_register = 3471
20856	CEFBS_HasNEON, // VST1d32 = 3472
20857	CEFBS_HasNEON, // VST1d32Q = 3473
20858	CEFBS_HasNEON, // VST1d32QPseudo = 3474
20859	CEFBS_HasNEON, // VST1d32Qwb_fixed = 3475
20860	CEFBS_HasNEON, // VST1d32Qwb_register = 3476
20861	CEFBS_HasNEON, // VST1d32T = 3477
20862	CEFBS_HasNEON, // VST1d32TPseudo = 3478
20863	CEFBS_HasNEON, // VST1d32Twb_fixed = 3479
20864	CEFBS_HasNEON, // VST1d32Twb_register = 3480
20865	CEFBS_HasNEON, // VST1d32wb_fixed = 3481
20866	CEFBS_HasNEON, // VST1d32wb_register = 3482
20867	CEFBS_HasNEON, // VST1d64 = 3483
20868	CEFBS_HasNEON, // VST1d64Q = 3484
20869	CEFBS_HasNEON, // VST1d64QPseudo = 3485
20870	CEFBS_HasNEON, // VST1d64QPseudoWB_fixed = 3486
20871	CEFBS_HasNEON, // VST1d64QPseudoWB_register = 3487
20872	CEFBS_HasNEON, // VST1d64Qwb_fixed = 3488
20873	CEFBS_HasNEON, // VST1d64Qwb_register = 3489
20874	CEFBS_HasNEON, // VST1d64T = 3490
20875	CEFBS_HasNEON, // VST1d64TPseudo = 3491
20876	CEFBS_HasNEON, // VST1d64TPseudoWB_fixed = 3492
20877	CEFBS_HasNEON, // VST1d64TPseudoWB_register = 3493
20878	CEFBS_HasNEON, // VST1d64Twb_fixed = 3494
20879	CEFBS_HasNEON, // VST1d64Twb_register = 3495
20880	CEFBS_HasNEON, // VST1d64wb_fixed = 3496
20881	CEFBS_HasNEON, // VST1d64wb_register = 3497
20882	CEFBS_HasNEON, // VST1d8 = 3498
20883	CEFBS_HasNEON, // VST1d8Q = 3499
20884	CEFBS_HasNEON, // VST1d8QPseudo = 3500
20885	CEFBS_HasNEON, // VST1d8Qwb_fixed = 3501
20886	CEFBS_HasNEON, // VST1d8Qwb_register = 3502
20887	CEFBS_HasNEON, // VST1d8T = 3503
20888	CEFBS_HasNEON, // VST1d8TPseudo = 3504
20889	CEFBS_HasNEON, // VST1d8Twb_fixed = 3505
20890	CEFBS_HasNEON, // VST1d8Twb_register = 3506
20891	CEFBS_HasNEON, // VST1d8wb_fixed = 3507
20892	CEFBS_HasNEON, // VST1d8wb_register = 3508
20893	CEFBS_HasNEON, // VST1q16 = 3509
20894	CEFBS_HasNEON, // VST1q16HighQPseudo = 3510
20895	CEFBS_HasNEON, // VST1q16HighTPseudo = 3511
20896	CEFBS_HasNEON, // VST1q16LowQPseudo_UPD = 3512
20897	CEFBS_HasNEON, // VST1q16LowTPseudo_UPD = 3513
20898	CEFBS_HasNEON, // VST1q16wb_fixed = 3514
20899	CEFBS_HasNEON, // VST1q16wb_register = 3515
20900	CEFBS_HasNEON, // VST1q32 = 3516
20901	CEFBS_HasNEON, // VST1q32HighQPseudo = 3517
20902	CEFBS_HasNEON, // VST1q32HighTPseudo = 3518
20903	CEFBS_HasNEON, // VST1q32LowQPseudo_UPD = 3519
20904	CEFBS_HasNEON, // VST1q32LowTPseudo_UPD = 3520
20905	CEFBS_HasNEON, // VST1q32wb_fixed = 3521
20906	CEFBS_HasNEON, // VST1q32wb_register = 3522
20907	CEFBS_HasNEON, // VST1q64 = 3523
20908	CEFBS_HasNEON, // VST1q64HighQPseudo = 3524
20909	CEFBS_HasNEON, // VST1q64HighTPseudo = 3525
20910	CEFBS_HasNEON, // VST1q64LowQPseudo_UPD = 3526
20911	CEFBS_HasNEON, // VST1q64LowTPseudo_UPD = 3527
20912	CEFBS_HasNEON, // VST1q64wb_fixed = 3528
20913	CEFBS_HasNEON, // VST1q64wb_register = 3529
20914	CEFBS_HasNEON, // VST1q8 = 3530
20915	CEFBS_HasNEON, // VST1q8HighQPseudo = 3531
20916	CEFBS_HasNEON, // VST1q8HighTPseudo = 3532
20917	CEFBS_HasNEON, // VST1q8LowQPseudo_UPD = 3533
20918	CEFBS_HasNEON, // VST1q8LowTPseudo_UPD = 3534
20919	CEFBS_HasNEON, // VST1q8wb_fixed = 3535
20920	CEFBS_HasNEON, // VST1q8wb_register = 3536
20921	CEFBS_HasNEON, // VST2LNd16 = 3537
20922	CEFBS_HasNEON, // VST2LNd16Pseudo = 3538
20923	CEFBS_HasNEON, // VST2LNd16Pseudo_UPD = 3539
20924	CEFBS_HasNEON, // VST2LNd16_UPD = 3540
20925	CEFBS_HasNEON, // VST2LNd32 = 3541
20926	CEFBS_HasNEON, // VST2LNd32Pseudo = 3542
20927	CEFBS_HasNEON, // VST2LNd32Pseudo_UPD = 3543
20928	CEFBS_HasNEON, // VST2LNd32_UPD = 3544
20929	CEFBS_HasNEON, // VST2LNd8 = 3545
20930	CEFBS_HasNEON, // VST2LNd8Pseudo = 3546
20931	CEFBS_HasNEON, // VST2LNd8Pseudo_UPD = 3547
20932	CEFBS_HasNEON, // VST2LNd8_UPD = 3548
20933	CEFBS_HasNEON, // VST2LNq16 = 3549
20934	CEFBS_HasNEON, // VST2LNq16Pseudo = 3550
20935	CEFBS_HasNEON, // VST2LNq16Pseudo_UPD = 3551
20936	CEFBS_HasNEON, // VST2LNq16_UPD = 3552
20937	CEFBS_HasNEON, // VST2LNq32 = 3553
20938	CEFBS_HasNEON, // VST2LNq32Pseudo = 3554
20939	CEFBS_HasNEON, // VST2LNq32Pseudo_UPD = 3555
20940	CEFBS_HasNEON, // VST2LNq32_UPD = 3556
20941	CEFBS_HasNEON, // VST2b16 = 3557
20942	CEFBS_HasNEON, // VST2b16wb_fixed = 3558
20943	CEFBS_HasNEON, // VST2b16wb_register = 3559
20944	CEFBS_HasNEON, // VST2b32 = 3560
20945	CEFBS_HasNEON, // VST2b32wb_fixed = 3561
20946	CEFBS_HasNEON, // VST2b32wb_register = 3562
20947	CEFBS_HasNEON, // VST2b8 = 3563
20948	CEFBS_HasNEON, // VST2b8wb_fixed = 3564
20949	CEFBS_HasNEON, // VST2b8wb_register = 3565
20950	CEFBS_HasNEON, // VST2d16 = 3566
20951	CEFBS_HasNEON, // VST2d16wb_fixed = 3567
20952	CEFBS_HasNEON, // VST2d16wb_register = 3568
20953	CEFBS_HasNEON, // VST2d32 = 3569
20954	CEFBS_HasNEON, // VST2d32wb_fixed = 3570
20955	CEFBS_HasNEON, // VST2d32wb_register = 3571
20956	CEFBS_HasNEON, // VST2d8 = 3572
20957	CEFBS_HasNEON, // VST2d8wb_fixed = 3573
20958	CEFBS_HasNEON, // VST2d8wb_register = 3574
20959	CEFBS_HasNEON, // VST2q16 = 3575
20960	CEFBS_HasNEON, // VST2q16Pseudo = 3576
20961	CEFBS_HasNEON, // VST2q16PseudoWB_fixed = 3577
20962	CEFBS_HasNEON, // VST2q16PseudoWB_register = 3578
20963	CEFBS_HasNEON, // VST2q16wb_fixed = 3579
20964	CEFBS_HasNEON, // VST2q16wb_register = 3580
20965	CEFBS_HasNEON, // VST2q32 = 3581
20966	CEFBS_HasNEON, // VST2q32Pseudo = 3582
20967	CEFBS_HasNEON, // VST2q32PseudoWB_fixed = 3583
20968	CEFBS_HasNEON, // VST2q32PseudoWB_register = 3584
20969	CEFBS_HasNEON, // VST2q32wb_fixed = 3585
20970	CEFBS_HasNEON, // VST2q32wb_register = 3586
20971	CEFBS_HasNEON, // VST2q8 = 3587
20972	CEFBS_HasNEON, // VST2q8Pseudo = 3588
20973	CEFBS_HasNEON, // VST2q8PseudoWB_fixed = 3589
20974	CEFBS_HasNEON, // VST2q8PseudoWB_register = 3590
20975	CEFBS_HasNEON, // VST2q8wb_fixed = 3591
20976	CEFBS_HasNEON, // VST2q8wb_register = 3592
20977	CEFBS_HasNEON, // VST3LNd16 = 3593
20978	CEFBS_HasNEON, // VST3LNd16Pseudo = 3594
20979	CEFBS_HasNEON, // VST3LNd16Pseudo_UPD = 3595
20980	CEFBS_HasNEON, // VST3LNd16_UPD = 3596
20981	CEFBS_HasNEON, // VST3LNd32 = 3597
20982	CEFBS_HasNEON, // VST3LNd32Pseudo = 3598
20983	CEFBS_HasNEON, // VST3LNd32Pseudo_UPD = 3599
20984	CEFBS_HasNEON, // VST3LNd32_UPD = 3600
20985	CEFBS_HasNEON, // VST3LNd8 = 3601
20986	CEFBS_HasNEON, // VST3LNd8Pseudo = 3602
20987	CEFBS_HasNEON, // VST3LNd8Pseudo_UPD = 3603
20988	CEFBS_HasNEON, // VST3LNd8_UPD = 3604
20989	CEFBS_HasNEON, // VST3LNq16 = 3605
20990	CEFBS_HasNEON, // VST3LNq16Pseudo = 3606
20991	CEFBS_HasNEON, // VST3LNq16Pseudo_UPD = 3607
20992	CEFBS_HasNEON, // VST3LNq16_UPD = 3608
20993	CEFBS_HasNEON, // VST3LNq32 = 3609
20994	CEFBS_HasNEON, // VST3LNq32Pseudo = 3610
20995	CEFBS_HasNEON, // VST3LNq32Pseudo_UPD = 3611
20996	CEFBS_HasNEON, // VST3LNq32_UPD = 3612
20997	CEFBS_HasNEON, // VST3d16 = 3613
20998	CEFBS_HasNEON, // VST3d16Pseudo = 3614
20999	CEFBS_HasNEON, // VST3d16Pseudo_UPD = 3615
21000	CEFBS_HasNEON, // VST3d16_UPD = 3616
21001	CEFBS_HasNEON, // VST3d32 = 3617
21002	CEFBS_HasNEON, // VST3d32Pseudo = 3618
21003	CEFBS_HasNEON, // VST3d32Pseudo_UPD = 3619
21004	CEFBS_HasNEON, // VST3d32_UPD = 3620
21005	CEFBS_HasNEON, // VST3d8 = 3621
21006	CEFBS_HasNEON, // VST3d8Pseudo = 3622
21007	CEFBS_HasNEON, // VST3d8Pseudo_UPD = 3623
21008	CEFBS_HasNEON, // VST3d8_UPD = 3624
21009	CEFBS_HasNEON, // VST3q16 = 3625
21010	CEFBS_HasNEON, // VST3q16Pseudo_UPD = 3626
21011	CEFBS_HasNEON, // VST3q16_UPD = 3627
21012	CEFBS_HasNEON, // VST3q16oddPseudo = 3628
21013	CEFBS_HasNEON, // VST3q16oddPseudo_UPD = 3629
21014	CEFBS_HasNEON, // VST3q32 = 3630
21015	CEFBS_HasNEON, // VST3q32Pseudo_UPD = 3631
21016	CEFBS_HasNEON, // VST3q32_UPD = 3632
21017	CEFBS_HasNEON, // VST3q32oddPseudo = 3633
21018	CEFBS_HasNEON, // VST3q32oddPseudo_UPD = 3634
21019	CEFBS_HasNEON, // VST3q8 = 3635
21020	CEFBS_HasNEON, // VST3q8Pseudo_UPD = 3636
21021	CEFBS_HasNEON, // VST3q8_UPD = 3637
21022	CEFBS_HasNEON, // VST3q8oddPseudo = 3638
21023	CEFBS_HasNEON, // VST3q8oddPseudo_UPD = 3639
21024	CEFBS_HasNEON, // VST4LNd16 = 3640
21025	CEFBS_HasNEON, // VST4LNd16Pseudo = 3641
21026	CEFBS_HasNEON, // VST4LNd16Pseudo_UPD = 3642
21027	CEFBS_HasNEON, // VST4LNd16_UPD = 3643
21028	CEFBS_HasNEON, // VST4LNd32 = 3644
21029	CEFBS_HasNEON, // VST4LNd32Pseudo = 3645
21030	CEFBS_HasNEON, // VST4LNd32Pseudo_UPD = 3646
21031	CEFBS_HasNEON, // VST4LNd32_UPD = 3647
21032	CEFBS_HasNEON, // VST4LNd8 = 3648
21033	CEFBS_HasNEON, // VST4LNd8Pseudo = 3649
21034	CEFBS_HasNEON, // VST4LNd8Pseudo_UPD = 3650
21035	CEFBS_HasNEON, // VST4LNd8_UPD = 3651
21036	CEFBS_HasNEON, // VST4LNq16 = 3652
21037	CEFBS_HasNEON, // VST4LNq16Pseudo = 3653
21038	CEFBS_HasNEON, // VST4LNq16Pseudo_UPD = 3654
21039	CEFBS_HasNEON, // VST4LNq16_UPD = 3655
21040	CEFBS_HasNEON, // VST4LNq32 = 3656
21041	CEFBS_HasNEON, // VST4LNq32Pseudo = 3657
21042	CEFBS_HasNEON, // VST4LNq32Pseudo_UPD = 3658
21043	CEFBS_HasNEON, // VST4LNq32_UPD = 3659
21044	CEFBS_HasNEON, // VST4d16 = 3660
21045	CEFBS_HasNEON, // VST4d16Pseudo = 3661
21046	CEFBS_HasNEON, // VST4d16Pseudo_UPD = 3662
21047	CEFBS_HasNEON, // VST4d16_UPD = 3663
21048	CEFBS_HasNEON, // VST4d32 = 3664
21049	CEFBS_HasNEON, // VST4d32Pseudo = 3665
21050	CEFBS_HasNEON, // VST4d32Pseudo_UPD = 3666
21051	CEFBS_HasNEON, // VST4d32_UPD = 3667
21052	CEFBS_HasNEON, // VST4d8 = 3668
21053	CEFBS_HasNEON, // VST4d8Pseudo = 3669
21054	CEFBS_HasNEON, // VST4d8Pseudo_UPD = 3670
21055	CEFBS_HasNEON, // VST4d8_UPD = 3671
21056	CEFBS_HasNEON, // VST4q16 = 3672
21057	CEFBS_HasNEON, // VST4q16Pseudo_UPD = 3673
21058	CEFBS_HasNEON, // VST4q16_UPD = 3674
21059	CEFBS_HasNEON, // VST4q16oddPseudo = 3675
21060	CEFBS_HasNEON, // VST4q16oddPseudo_UPD = 3676
21061	CEFBS_HasNEON, // VST4q32 = 3677
21062	CEFBS_HasNEON, // VST4q32Pseudo_UPD = 3678
21063	CEFBS_HasNEON, // VST4q32_UPD = 3679
21064	CEFBS_HasNEON, // VST4q32oddPseudo = 3680
21065	CEFBS_HasNEON, // VST4q32oddPseudo_UPD = 3681
21066	CEFBS_HasNEON, // VST4q8 = 3682
21067	CEFBS_HasNEON, // VST4q8Pseudo_UPD = 3683
21068	CEFBS_HasNEON, // VST4q8_UPD = 3684
21069	CEFBS_HasNEON, // VST4q8oddPseudo = 3685
21070	CEFBS_HasNEON, // VST4q8oddPseudo_UPD = 3686
21071	CEFBS_HasFPRegs, // VSTMDDB_UPD = 3687
21072	CEFBS_HasFPRegs, // VSTMDIA = 3688
21073	CEFBS_HasFPRegs, // VSTMDIA_UPD = 3689
21074	CEFBS_HasVFP2, // VSTMQIA = 3690
21075	CEFBS_HasFPRegs, // VSTMSDB_UPD = 3691
21076	CEFBS_HasFPRegs, // VSTMSIA = 3692
21077	CEFBS_HasFPRegs, // VSTMSIA_UPD = 3693
21078	CEFBS_HasFPRegs, // VSTRD = 3694
21079	CEFBS_HasFPRegs16, // VSTRH = 3695
21080	CEFBS_HasFPRegs, // VSTRS = 3696
21081	CEFBS_HasV8_1MMainline_Has8MSecExt, // VSTR_FPCXTNS_off = 3697
21082	CEFBS_HasV8_1MMainline_Has8MSecExt, // VSTR_FPCXTNS_post = 3698
21083	CEFBS_HasV8_1MMainline_Has8MSecExt, // VSTR_FPCXTNS_pre = 3699
21084	CEFBS_HasV8_1MMainline_Has8MSecExt, // VSTR_FPCXTS_off = 3700
21085	CEFBS_HasV8_1MMainline_Has8MSecExt, // VSTR_FPCXTS_post = 3701
21086	CEFBS_HasV8_1MMainline_Has8MSecExt, // VSTR_FPCXTS_pre = 3702
21087	CEFBS_HasFPRegs_HasV8_1MMainline, // VSTR_FPSCR_NZCVQC_off = 3703
21088	CEFBS_HasFPRegs_HasV8_1MMainline, // VSTR_FPSCR_NZCVQC_post = 3704
21089	CEFBS_HasFPRegs_HasV8_1MMainline, // VSTR_FPSCR_NZCVQC_pre = 3705
21090	CEFBS_HasFPRegs_HasV8_1MMainline, // VSTR_FPSCR_off = 3706
21091	CEFBS_HasFPRegs_HasV8_1MMainline, // VSTR_FPSCR_post = 3707
21092	CEFBS_HasFPRegs_HasV8_1MMainline, // VSTR_FPSCR_pre = 3708
21093	CEFBS_HasV8_1MMainline_HasMVEInt, // VSTR_P0_off = 3709
21094	CEFBS_HasV8_1MMainline_HasMVEInt, // VSTR_P0_post = 3710
21095	CEFBS_HasV8_1MMainline_HasMVEInt, // VSTR_P0_pre = 3711
21096	CEFBS_HasV8_1MMainline_HasMVEInt, // VSTR_VPR_off = 3712
21097	CEFBS_HasV8_1MMainline_HasMVEInt, // VSTR_VPR_post = 3713
21098	CEFBS_HasV8_1MMainline_HasMVEInt, // VSTR_VPR_pre = 3714
21099	CEFBS_HasVFP2_HasDPVFP, // VSUBD = 3715
21100	CEFBS_HasFullFP16, // VSUBH = 3716
21101	CEFBS_HasNEON, // VSUBHNv2i32 = 3717
21102	CEFBS_HasNEON, // VSUBHNv4i16 = 3718
21103	CEFBS_HasNEON, // VSUBHNv8i8 = 3719
21104	CEFBS_HasNEON, // VSUBLsv2i64 = 3720
21105	CEFBS_HasNEON, // VSUBLsv4i32 = 3721
21106	CEFBS_HasNEON, // VSUBLsv8i16 = 3722
21107	CEFBS_HasNEON, // VSUBLuv2i64 = 3723
21108	CEFBS_HasNEON, // VSUBLuv4i32 = 3724
21109	CEFBS_HasNEON, // VSUBLuv8i16 = 3725
21110	CEFBS_HasVFP2, // VSUBS = 3726
21111	CEFBS_HasNEON, // VSUBWsv2i64 = 3727
21112	CEFBS_HasNEON, // VSUBWsv4i32 = 3728
21113	CEFBS_HasNEON, // VSUBWsv8i16 = 3729
21114	CEFBS_HasNEON, // VSUBWuv2i64 = 3730
21115	CEFBS_HasNEON, // VSUBWuv4i32 = 3731
21116	CEFBS_HasNEON, // VSUBWuv8i16 = 3732
21117	CEFBS_HasNEON, // VSUBfd = 3733
21118	CEFBS_HasNEON, // VSUBfq = 3734
21119	CEFBS_HasNEON_HasFullFP16, // VSUBhd = 3735
21120	CEFBS_HasNEON_HasFullFP16, // VSUBhq = 3736
21121	CEFBS_HasNEON, // VSUBv16i8 = 3737
21122	CEFBS_HasNEON, // VSUBv1i64 = 3738
21123	CEFBS_HasNEON, // VSUBv2i32 = 3739
21124	CEFBS_HasNEON, // VSUBv2i64 = 3740
21125	CEFBS_HasNEON, // VSUBv4i16 = 3741
21126	CEFBS_HasNEON, // VSUBv4i32 = 3742
21127	CEFBS_HasNEON, // VSUBv8i16 = 3743
21128	CEFBS_HasNEON, // VSUBv8i8 = 3744
21129	CEFBS_HasMatMulInt8, // VSUDOTDI = 3745
21130	CEFBS_HasMatMulInt8, // VSUDOTQI = 3746
21131	CEFBS_HasNEON, // VSWPd = 3747
21132	CEFBS_HasNEON, // VSWPq = 3748
21133	CEFBS_HasNEON, // VTBL1 = 3749
21134	CEFBS_HasNEON, // VTBL2 = 3750
21135	CEFBS_HasNEON, // VTBL3 = 3751
21136	CEFBS_HasNEON, // VTBL3Pseudo = 3752
21137	CEFBS_HasNEON, // VTBL4 = 3753
21138	CEFBS_HasNEON, // VTBL4Pseudo = 3754
21139	CEFBS_HasNEON, // VTBX1 = 3755
21140	CEFBS_HasNEON, // VTBX2 = 3756
21141	CEFBS_HasNEON, // VTBX3 = 3757
21142	CEFBS_HasNEON, // VTBX3Pseudo = 3758
21143	CEFBS_HasNEON, // VTBX4 = 3759
21144	CEFBS_HasNEON, // VTBX4Pseudo = 3760
21145	CEFBS_HasVFP2_HasDPVFP, // VTOSHD = 3761
21146	CEFBS_HasFullFP16, // VTOSHH = 3762
21147	CEFBS_HasVFP2, // VTOSHS = 3763
21148	CEFBS_HasVFP2_HasDPVFP, // VTOSIRD = 3764
21149	CEFBS_HasFullFP16, // VTOSIRH = 3765
21150	CEFBS_HasVFP2, // VTOSIRS = 3766
21151	CEFBS_HasVFP2_HasDPVFP, // VTOSIZD = 3767
21152	CEFBS_HasFullFP16, // VTOSIZH = 3768
21153	CEFBS_HasVFP2, // VTOSIZS = 3769
21154	CEFBS_HasVFP2_HasDPVFP, // VTOSLD = 3770
21155	CEFBS_HasFullFP16, // VTOSLH = 3771
21156	CEFBS_HasVFP2, // VTOSLS = 3772
21157	CEFBS_HasVFP2_HasDPVFP, // VTOUHD = 3773
21158	CEFBS_HasFullFP16, // VTOUHH = 3774
21159	CEFBS_HasVFP2, // VTOUHS = 3775
21160	CEFBS_HasVFP2_HasDPVFP, // VTOUIRD = 3776
21161	CEFBS_HasFullFP16, // VTOUIRH = 3777
21162	CEFBS_HasVFP2, // VTOUIRS = 3778
21163	CEFBS_HasVFP2_HasDPVFP, // VTOUIZD = 3779
21164	CEFBS_HasFullFP16, // VTOUIZH = 3780
21165	CEFBS_HasVFP2, // VTOUIZS = 3781
21166	CEFBS_HasVFP2_HasDPVFP, // VTOULD = 3782
21167	CEFBS_HasFullFP16, // VTOULH = 3783
21168	CEFBS_HasVFP2, // VTOULS = 3784
21169	CEFBS_HasNEON, // VTRNd16 = 3785
21170	CEFBS_HasNEON, // VTRNd32 = 3786
21171	CEFBS_HasNEON, // VTRNd8 = 3787
21172	CEFBS_HasNEON, // VTRNq16 = 3788
21173	CEFBS_HasNEON, // VTRNq32 = 3789
21174	CEFBS_HasNEON, // VTRNq8 = 3790
21175	CEFBS_HasNEON, // VTSTv16i8 = 3791
21176	CEFBS_HasNEON, // VTSTv2i32 = 3792
21177	CEFBS_HasNEON, // VTSTv4i16 = 3793
21178	CEFBS_HasNEON, // VTSTv4i32 = 3794
21179	CEFBS_HasNEON, // VTSTv8i16 = 3795
21180	CEFBS_HasNEON, // VTSTv8i8 = 3796
21181	CEFBS_HasDotProd, // VUDOTD = 3797
21182	CEFBS_HasDotProd, // VUDOTDI = 3798
21183	CEFBS_HasDotProd, // VUDOTQ = 3799
21184	CEFBS_HasDotProd, // VUDOTQI = 3800
21185	CEFBS_HasVFP2_HasDPVFP, // VUHTOD = 3801
21186	CEFBS_HasFullFP16, // VUHTOH = 3802
21187	CEFBS_HasVFP2, // VUHTOS = 3803
21188	CEFBS_HasVFP2_HasDPVFP, // VUITOD = 3804
21189	CEFBS_HasFullFP16, // VUITOH = 3805
21190	CEFBS_HasVFP2, // VUITOS = 3806
21191	CEFBS_HasVFP2_HasDPVFP, // VULTOD = 3807
21192	CEFBS_HasFullFP16, // VULTOH = 3808
21193	CEFBS_HasVFP2, // VULTOS = 3809
21194	CEFBS_HasMatMulInt8, // VUMMLA = 3810
21195	CEFBS_HasMatMulInt8, // VUSDOTD = 3811
21196	CEFBS_HasMatMulInt8, // VUSDOTDI = 3812
21197	CEFBS_HasMatMulInt8, // VUSDOTQ = 3813
21198	CEFBS_HasMatMulInt8, // VUSDOTQI = 3814
21199	CEFBS_HasMatMulInt8, // VUSMMLA = 3815
21200	CEFBS_HasNEON, // VUZPd16 = 3816
21201	CEFBS_HasNEON, // VUZPd8 = 3817
21202	CEFBS_HasNEON, // VUZPq16 = 3818
21203	CEFBS_HasNEON, // VUZPq32 = 3819
21204	CEFBS_HasNEON, // VUZPq8 = 3820
21205	CEFBS_HasNEON, // VZIPd16 = 3821
21206	CEFBS_HasNEON, // VZIPd8 = 3822
21207	CEFBS_HasNEON, // VZIPq16 = 3823
21208	CEFBS_HasNEON, // VZIPq32 = 3824
21209	CEFBS_HasNEON, // VZIPq8 = 3825
21210	CEFBS_IsARM, // sysLDMDA = 3826
21211	CEFBS_IsARM, // sysLDMDA_UPD = 3827
21212	CEFBS_IsARM, // sysLDMDB = 3828
21213	CEFBS_IsARM, // sysLDMDB_UPD = 3829
21214	CEFBS_IsARM, // sysLDMIA = 3830
21215	CEFBS_IsARM, // sysLDMIA_UPD = 3831
21216	CEFBS_IsARM, // sysLDMIB = 3832
21217	CEFBS_IsARM, // sysLDMIB_UPD = 3833
21218	CEFBS_IsARM, // sysSTMDA = 3834
21219	CEFBS_IsARM, // sysSTMDA_UPD = 3835
21220	CEFBS_IsARM, // sysSTMDB = 3836
21221	CEFBS_IsARM, // sysSTMDB_UPD = 3837
21222	CEFBS_IsARM, // sysSTMIA = 3838
21223	CEFBS_IsARM, // sysSTMIA_UPD = 3839
21224	CEFBS_IsARM, // sysSTMIB = 3840
21225	CEFBS_IsARM, // sysSTMIB_UPD = 3841
21226	CEFBS_IsThumb2, // t2ADCri = 3842
21227	CEFBS_IsThumb2, // t2ADCrr = 3843
21228	CEFBS_IsThumb2, // t2ADCrs = 3844
21229	CEFBS_IsThumb2, // t2ADDri = 3845
21230	CEFBS_IsThumb2, // t2ADDri12 = 3846
21231	CEFBS_IsThumb2, // t2ADDrr = 3847
21232	CEFBS_IsThumb2, // t2ADDrs = 3848
21233	CEFBS_IsThumb2, // t2ADDspImm = 3849
21234	CEFBS_IsThumb2, // t2ADDspImm12 = 3850
21235	CEFBS_IsThumb2, // t2ADR = 3851
21236	CEFBS_IsThumb2, // t2ANDri = 3852
21237	CEFBS_IsThumb2, // t2ANDrr = 3853
21238	CEFBS_IsThumb2, // t2ANDrs = 3854
21239	CEFBS_IsThumb2, // t2ASRri = 3855
21240	CEFBS_IsThumb2, // t2ASRrr = 3856
21241	CEFBS_IsThumb_HasV8MBaseline, // t2B = 3857
21242	CEFBS_IsThumb2, // t2BFC = 3858
21243	CEFBS_IsThumb2, // t2BFI = 3859
21244	CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2BFLi = 3860
21245	CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2BFLr = 3861
21246	CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2BFi = 3862
21247	CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2BFic = 3863
21248	CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2BFr = 3864
21249	CEFBS_IsThumb2, // t2BICri = 3865
21250	CEFBS_IsThumb2, // t2BICrr = 3866
21251	CEFBS_IsThumb2, // t2BICrs = 3867
21252	CEFBS_IsThumb2_IsNotMClass, // t2BXJ = 3868
21253	CEFBS_IsThumb2, // t2Bcc = 3869
21254	CEFBS_IsThumb2_PreV8, // t2CDP = 3870
21255	CEFBS_IsThumb2_PreV8, // t2CDP2 = 3871
21256	CEFBS_IsThumb_HasV7Clrex, // t2CLREX = 3872
21257	CEFBS_HasV8_1MMainline, // t2CLRM = 3873
21258	CEFBS_IsThumb2, // t2CLZ = 3874
21259	CEFBS_IsThumb2, // t2CMNri = 3875
21260	CEFBS_IsThumb2, // t2CMNzrr = 3876
21261	CEFBS_IsThumb2, // t2CMNzrs = 3877
21262	CEFBS_IsThumb2, // t2CMPri = 3878
21263	CEFBS_IsThumb2, // t2CMPrr = 3879
21264	CEFBS_IsThumb2, // t2CMPrs = 3880
21265	CEFBS_IsThumb2_IsNotMClass, // t2CPS1p = 3881
21266	CEFBS_IsThumb2_IsNotMClass, // t2CPS2p = 3882
21267	CEFBS_IsThumb2_IsNotMClass, // t2CPS3p = 3883
21268	CEFBS_IsThumb2_HasV8_HasCRC, // t2CRC32B = 3884
21269	CEFBS_IsThumb2_HasV8_HasCRC, // t2CRC32CB = 3885
21270	CEFBS_IsThumb2_HasV8_HasCRC, // t2CRC32CH = 3886
21271	CEFBS_IsThumb2_HasV8_HasCRC, // t2CRC32CW = 3887
21272	CEFBS_IsThumb2_HasV8_HasCRC, // t2CRC32H = 3888
21273	CEFBS_IsThumb2_HasV8_HasCRC, // t2CRC32W = 3889
21274	CEFBS_HasV8_1MMainline, // t2CSEL = 3890
21275	CEFBS_HasV8_1MMainline, // t2CSINC = 3891
21276	CEFBS_HasV8_1MMainline, // t2CSINV = 3892
21277	CEFBS_HasV8_1MMainline, // t2CSNEG = 3893
21278	CEFBS_IsThumb2, // t2DBG = 3894
21279	CEFBS_IsThumb2_HasV8, // t2DCPS1 = 3895
21280	CEFBS_IsThumb2_HasV8, // t2DCPS2 = 3896
21281	CEFBS_IsThumb2_HasV8, // t2DCPS3 = 3897
21282	CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2DLS = 3898
21283	CEFBS_IsThumb_HasDB, // t2DMB = 3899
21284	CEFBS_IsThumb_HasDB, // t2DSB = 3900
21285	CEFBS_IsThumb2, // t2EORri = 3901
21286	CEFBS_IsThumb2, // t2EORrr = 3902
21287	CEFBS_IsThumb2, // t2EORrs = 3903
21288	CEFBS_IsThumb2, // t2HINT = 3904
21289	CEFBS_IsThumb2_HasVirtualization, // t2HVC = 3905
21290	CEFBS_IsThumb_HasDB, // t2ISB = 3906
21291	CEFBS_IsThumb2, // t2IT = 3907
21292	CEFBS_IsThumb2_HasVFP2, // t2Int_eh_sjlj_setjmp = 3908
21293	CEFBS_IsThumb2, // t2Int_eh_sjlj_setjmp_nofp = 3909
21294	CEFBS_IsThumb_HasAcquireRelease, // t2LDA = 3910
21295	CEFBS_IsThumb_HasAcquireRelease, // t2LDAB = 3911
21296	CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex, // t2LDAEX = 3912
21297	CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex, // t2LDAEXB = 3913
21298	CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex_IsNotMClass, // t2LDAEXD = 3914
21299	CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex, // t2LDAEXH = 3915
21300	CEFBS_IsThumb_HasAcquireRelease, // t2LDAH = 3916
21301	CEFBS_PreV8_IsThumb2, // t2LDC2L_OFFSET = 3917
21302	CEFBS_PreV8_IsThumb2, // t2LDC2L_OPTION = 3918
21303	CEFBS_PreV8_IsThumb2, // t2LDC2L_POST = 3919
21304	CEFBS_PreV8_IsThumb2, // t2LDC2L_PRE = 3920
21305	CEFBS_PreV8_IsThumb2, // t2LDC2_OFFSET = 3921
21306	CEFBS_PreV8_IsThumb2, // t2LDC2_OPTION = 3922
21307	CEFBS_PreV8_IsThumb2, // t2LDC2_POST = 3923
21308	CEFBS_PreV8_IsThumb2, // t2LDC2_PRE = 3924
21309	CEFBS_IsThumb2, // t2LDCL_OFFSET = 3925
21310	CEFBS_IsThumb2, // t2LDCL_OPTION = 3926
21311	CEFBS_IsThumb2, // t2LDCL_POST = 3927
21312	CEFBS_IsThumb2, // t2LDCL_PRE = 3928
21313	CEFBS_IsThumb2, // t2LDC_OFFSET = 3929
21314	CEFBS_IsThumb2, // t2LDC_OPTION = 3930
21315	CEFBS_IsThumb2, // t2LDC_POST = 3931
21316	CEFBS_IsThumb2, // t2LDC_PRE = 3932
21317	CEFBS_IsThumb2, // t2LDMDB = 3933
21318	CEFBS_IsThumb2, // t2LDMDB_UPD = 3934
21319	CEFBS_IsThumb2, // t2LDMIA = 3935
21320	CEFBS_IsThumb2, // t2LDMIA_UPD = 3936
21321	CEFBS_IsThumb2, // t2LDRBT = 3937
21322	CEFBS_IsThumb2, // t2LDRB_POST = 3938
21323	CEFBS_IsThumb2, // t2LDRB_PRE = 3939
21324	CEFBS_IsThumb2, // t2LDRBi12 = 3940
21325	CEFBS_IsThumb2, // t2LDRBi8 = 3941
21326	CEFBS_IsThumb2, // t2LDRBpci = 3942
21327	CEFBS_IsThumb2, // t2LDRBs = 3943
21328	CEFBS_IsThumb2, // t2LDRD_POST = 3944
21329	CEFBS_IsThumb2, // t2LDRD_PRE = 3945
21330	CEFBS_IsThumb2, // t2LDRDi8 = 3946
21331	CEFBS_IsThumb_HasV8MBaseline, // t2LDREX = 3947
21332	CEFBS_IsThumb_HasV8MBaseline, // t2LDREXB = 3948
21333	CEFBS_IsThumb2_IsNotMClass, // t2LDREXD = 3949
21334	CEFBS_IsThumb_HasV8MBaseline, // t2LDREXH = 3950
21335	CEFBS_IsThumb2, // t2LDRHT = 3951
21336	CEFBS_IsThumb2, // t2LDRH_POST = 3952
21337	CEFBS_IsThumb2, // t2LDRH_PRE = 3953
21338	CEFBS_IsThumb2, // t2LDRHi12 = 3954
21339	CEFBS_IsThumb2, // t2LDRHi8 = 3955
21340	CEFBS_IsThumb2, // t2LDRHpci = 3956
21341	CEFBS_IsThumb2, // t2LDRHs = 3957
21342	CEFBS_IsThumb2, // t2LDRSBT = 3958
21343	CEFBS_IsThumb2, // t2LDRSB_POST = 3959
21344	CEFBS_IsThumb2, // t2LDRSB_PRE = 3960
21345	CEFBS_IsThumb2, // t2LDRSBi12 = 3961
21346	CEFBS_IsThumb2, // t2LDRSBi8 = 3962
21347	CEFBS_IsThumb2, // t2LDRSBpci = 3963
21348	CEFBS_IsThumb2, // t2LDRSBs = 3964
21349	CEFBS_IsThumb2, // t2LDRSHT = 3965
21350	CEFBS_IsThumb2, // t2LDRSH_POST = 3966
21351	CEFBS_IsThumb2, // t2LDRSH_PRE = 3967
21352	CEFBS_IsThumb2, // t2LDRSHi12 = 3968
21353	CEFBS_IsThumb2, // t2LDRSHi8 = 3969
21354	CEFBS_IsThumb2, // t2LDRSHpci = 3970
21355	CEFBS_IsThumb2, // t2LDRSHs = 3971
21356	CEFBS_IsThumb2, // t2LDRT = 3972
21357	CEFBS_IsThumb2, // t2LDR_POST = 3973
21358	CEFBS_IsThumb2, // t2LDR_PRE = 3974
21359	CEFBS_IsThumb2, // t2LDRi12 = 3975
21360	CEFBS_IsThumb2, // t2LDRi8 = 3976
21361	CEFBS_IsThumb2, // t2LDRpci = 3977
21362	CEFBS_IsThumb2, // t2LDRs = 3978
21363	CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2LE = 3979
21364	CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2LEUpdate = 3980
21365	CEFBS_IsThumb2, // t2LSLri = 3981
21366	CEFBS_IsThumb2, // t2LSLrr = 3982
21367	CEFBS_IsThumb2, // t2LSRri = 3983
21368	CEFBS_IsThumb2, // t2LSRrr = 3984
21369	CEFBS_IsThumb2, // t2MCR = 3985
21370	CEFBS_IsThumb2_PreV8, // t2MCR2 = 3986
21371	CEFBS_IsThumb2, // t2MCRR = 3987
21372	CEFBS_IsThumb2_PreV8, // t2MCRR2 = 3988
21373	CEFBS_IsThumb2, // t2MLA = 3989
21374	CEFBS_IsThumb2, // t2MLS = 3990
21375	CEFBS_IsThumb_HasV8MBaseline, // t2MOVTi16 = 3991
21376	CEFBS_IsThumb2, // t2MOVi = 3992
21377	CEFBS_IsThumb_HasV8MBaseline, // t2MOVi16 = 3993
21378	CEFBS_IsThumb2, // t2MOVr = 3994
21379	CEFBS_IsThumb2, // t2MOVsra_flag = 3995
21380	CEFBS_IsThumb2, // t2MOVsrl_flag = 3996
21381	CEFBS_IsThumb2, // t2MRC = 3997
21382	CEFBS_IsThumb2_PreV8, // t2MRC2 = 3998
21383	CEFBS_IsThumb2, // t2MRRC = 3999
21384	CEFBS_IsThumb2_PreV8, // t2MRRC2 = 4000
21385	CEFBS_IsThumb2_IsNotMClass, // t2MRS_AR = 4001
21386	CEFBS_IsThumb_IsMClass, // t2MRS_M = 4002
21387	CEFBS_IsThumb_HasVirtualization, // t2MRSbanked = 4003
21388	CEFBS_IsThumb2_IsNotMClass, // t2MRSsys_AR = 4004
21389	CEFBS_IsThumb2_IsNotMClass, // t2MSR_AR = 4005
21390	CEFBS_IsThumb_IsMClass, // t2MSR_M = 4006
21391	CEFBS_IsThumb_HasVirtualization, // t2MSRbanked = 4007
21392	CEFBS_IsThumb2, // t2MUL = 4008
21393	CEFBS_IsThumb2, // t2MVNi = 4009
21394	CEFBS_IsThumb2, // t2MVNr = 4010
21395	CEFBS_IsThumb2, // t2MVNs = 4011
21396	CEFBS_IsThumb2, // t2ORNri = 4012
21397	CEFBS_IsThumb2, // t2ORNrr = 4013
21398	CEFBS_IsThumb2, // t2ORNrs = 4014
21399	CEFBS_IsThumb2, // t2ORRri = 4015
21400	CEFBS_IsThumb2, // t2ORRrr = 4016
21401	CEFBS_IsThumb2, // t2ORRrs = 4017
21402	CEFBS_HasDSP_IsThumb2, // t2PKHBT = 4018
21403	CEFBS_HasDSP_IsThumb2, // t2PKHTB = 4019
21404	CEFBS_IsThumb2_HasV7_HasMP, // t2PLDWi12 = 4020
21405	CEFBS_IsThumb2_HasV7_HasMP, // t2PLDWi8 = 4021
21406	CEFBS_IsThumb2_HasV7_HasMP, // t2PLDWs = 4022
21407	CEFBS_IsThumb2, // t2PLDi12 = 4023
21408	CEFBS_IsThumb2, // t2PLDi8 = 4024
21409	CEFBS_IsThumb2, // t2PLDpci = 4025
21410	CEFBS_IsThumb2, // t2PLDs = 4026
21411	CEFBS_IsThumb2_HasV7, // t2PLIi12 = 4027
21412	CEFBS_IsThumb2_HasV7, // t2PLIi8 = 4028
21413	CEFBS_IsThumb2_HasV7, // t2PLIpci = 4029
21414	CEFBS_IsThumb2_HasV7, // t2PLIs = 4030
21415	CEFBS_IsThumb2_HasDSP, // t2QADD = 4031
21416	CEFBS_IsThumb2_HasDSP, // t2QADD16 = 4032
21417	CEFBS_IsThumb2_HasDSP, // t2QADD8 = 4033
21418	CEFBS_IsThumb2_HasDSP, // t2QASX = 4034
21419	CEFBS_IsThumb2_HasDSP, // t2QDADD = 4035
21420	CEFBS_IsThumb2_HasDSP, // t2QDSUB = 4036
21421	CEFBS_IsThumb2_HasDSP, // t2QSAX = 4037
21422	CEFBS_IsThumb2_HasDSP, // t2QSUB = 4038
21423	CEFBS_IsThumb2_HasDSP, // t2QSUB16 = 4039
21424	CEFBS_IsThumb2_HasDSP, // t2QSUB8 = 4040
21425	CEFBS_IsThumb2, // t2RBIT = 4041
21426	CEFBS_IsThumb2, // t2REV = 4042
21427	CEFBS_IsThumb2, // t2REV16 = 4043
21428	CEFBS_IsThumb2, // t2REVSH = 4044
21429	CEFBS_IsThumb2_IsNotMClass, // t2RFEDB = 4045
21430	CEFBS_IsThumb2_IsNotMClass, // t2RFEDBW = 4046
21431	CEFBS_IsThumb2_IsNotMClass, // t2RFEIA = 4047
21432	CEFBS_IsThumb2_IsNotMClass, // t2RFEIAW = 4048
21433	CEFBS_IsThumb2, // t2RORri = 4049
21434	CEFBS_IsThumb2, // t2RORrr = 4050
21435	CEFBS_IsThumb2, // t2RRX = 4051
21436	CEFBS_IsThumb2, // t2RSBri = 4052
21437	CEFBS_IsThumb2, // t2RSBrr = 4053
21438	CEFBS_IsThumb2, // t2RSBrs = 4054
21439	CEFBS_IsThumb2_HasDSP, // t2SADD16 = 4055
21440	CEFBS_IsThumb2_HasDSP, // t2SADD8 = 4056
21441	CEFBS_IsThumb2_HasDSP, // t2SASX = 4057
21442	CEFBS_IsThumb2_HasSB, // t2SB = 4058
21443	CEFBS_IsThumb2, // t2SBCri = 4059
21444	CEFBS_IsThumb2, // t2SBCrr = 4060
21445	CEFBS_IsThumb2, // t2SBCrs = 4061
21446	CEFBS_IsThumb2, // t2SBFX = 4062
21447	CEFBS_HasDivideInThumb_IsThumb_HasV8MBaseline, // t2SDIV = 4063
21448	CEFBS_IsThumb2_HasDSP, // t2SEL = 4064
21449	CEFBS_IsThumb2_HasV8_HasV8_1a, // t2SETPAN = 4065
21450	CEFBS_Has8MSecExt, // t2SG = 4066
21451	CEFBS_IsThumb2_HasDSP, // t2SHADD16 = 4067
21452	CEFBS_IsThumb2_HasDSP, // t2SHADD8 = 4068
21453	CEFBS_IsThumb2_HasDSP, // t2SHASX = 4069
21454	CEFBS_IsThumb2_HasDSP, // t2SHSAX = 4070
21455	CEFBS_IsThumb2_HasDSP, // t2SHSUB16 = 4071
21456	CEFBS_IsThumb2_HasDSP, // t2SHSUB8 = 4072
21457	CEFBS_IsThumb2_HasTrustZone, // t2SMC = 4073
21458	CEFBS_IsThumb2_HasDSP, // t2SMLABB = 4074
21459	CEFBS_IsThumb2_HasDSP, // t2SMLABT = 4075
21460	CEFBS_IsThumb2_HasDSP, // t2SMLAD = 4076
21461	CEFBS_IsThumb2_HasDSP, // t2SMLADX = 4077
21462	CEFBS_IsThumb2, // t2SMLAL = 4078
21463	CEFBS_IsThumb2_HasDSP, // t2SMLALBB = 4079
21464	CEFBS_IsThumb2_HasDSP, // t2SMLALBT = 4080
21465	CEFBS_IsThumb2_HasDSP, // t2SMLALD = 4081
21466	CEFBS_IsThumb2_HasDSP, // t2SMLALDX = 4082
21467	CEFBS_IsThumb2_HasDSP, // t2SMLALTB = 4083
21468	CEFBS_IsThumb2_HasDSP, // t2SMLALTT = 4084
21469	CEFBS_IsThumb2_HasDSP, // t2SMLATB = 4085
21470	CEFBS_IsThumb2_HasDSP, // t2SMLATT = 4086
21471	CEFBS_IsThumb2_HasDSP, // t2SMLAWB = 4087
21472	CEFBS_IsThumb2_HasDSP, // t2SMLAWT = 4088
21473	CEFBS_IsThumb2_HasDSP, // t2SMLSD = 4089
21474	CEFBS_IsThumb2_HasDSP, // t2SMLSDX = 4090
21475	CEFBS_IsThumb2_HasDSP, // t2SMLSLD = 4091
21476	CEFBS_IsThumb2_HasDSP, // t2SMLSLDX = 4092
21477	CEFBS_IsThumb2_HasDSP, // t2SMMLA = 4093
21478	CEFBS_IsThumb2_HasDSP, // t2SMMLAR = 4094
21479	CEFBS_IsThumb2_HasDSP, // t2SMMLS = 4095
21480	CEFBS_IsThumb2_HasDSP, // t2SMMLSR = 4096
21481	CEFBS_IsThumb2_HasDSP, // t2SMMUL = 4097
21482	CEFBS_IsThumb2_HasDSP, // t2SMMULR = 4098
21483	CEFBS_IsThumb2_HasDSP, // t2SMUAD = 4099
21484	CEFBS_IsThumb2_HasDSP, // t2SMUADX = 4100
21485	CEFBS_IsThumb2_HasDSP, // t2SMULBB = 4101
21486	CEFBS_IsThumb2_HasDSP, // t2SMULBT = 4102
21487	CEFBS_IsThumb2, // t2SMULL = 4103
21488	CEFBS_IsThumb2_HasDSP, // t2SMULTB = 4104
21489	CEFBS_IsThumb2_HasDSP, // t2SMULTT = 4105
21490	CEFBS_IsThumb2_HasDSP, // t2SMULWB = 4106
21491	CEFBS_IsThumb2_HasDSP, // t2SMULWT = 4107
21492	CEFBS_IsThumb2_HasDSP, // t2SMUSD = 4108
21493	CEFBS_IsThumb2_HasDSP, // t2SMUSDX = 4109
21494	CEFBS_IsThumb2_IsNotMClass, // t2SRSDB = 4110
21495	CEFBS_IsThumb2_IsNotMClass, // t2SRSDB_UPD = 4111
21496	CEFBS_IsThumb2_IsNotMClass, // t2SRSIA = 4112
21497	CEFBS_IsThumb2_IsNotMClass, // t2SRSIA_UPD = 4113
21498	CEFBS_IsThumb2, // t2SSAT = 4114
21499	CEFBS_IsThumb2_HasDSP, // t2SSAT16 = 4115
21500	CEFBS_IsThumb2_HasDSP, // t2SSAX = 4116
21501	CEFBS_IsThumb2_HasDSP, // t2SSUB16 = 4117
21502	CEFBS_IsThumb2_HasDSP, // t2SSUB8 = 4118
21503	CEFBS_PreV8_IsThumb2, // t2STC2L_OFFSET = 4119
21504	CEFBS_PreV8_IsThumb2, // t2STC2L_OPTION = 4120
21505	CEFBS_PreV8_IsThumb2, // t2STC2L_POST = 4121
21506	CEFBS_PreV8_IsThumb2, // t2STC2L_PRE = 4122
21507	CEFBS_PreV8_IsThumb2, // t2STC2_OFFSET = 4123
21508	CEFBS_PreV8_IsThumb2, // t2STC2_OPTION = 4124
21509	CEFBS_PreV8_IsThumb2, // t2STC2_POST = 4125
21510	CEFBS_PreV8_IsThumb2, // t2STC2_PRE = 4126
21511	CEFBS_IsThumb2, // t2STCL_OFFSET = 4127
21512	CEFBS_IsThumb2, // t2STCL_OPTION = 4128
21513	CEFBS_IsThumb2, // t2STCL_POST = 4129
21514	CEFBS_IsThumb2, // t2STCL_PRE = 4130
21515	CEFBS_IsThumb2, // t2STC_OFFSET = 4131
21516	CEFBS_IsThumb2, // t2STC_OPTION = 4132
21517	CEFBS_IsThumb2, // t2STC_POST = 4133
21518	CEFBS_IsThumb2, // t2STC_PRE = 4134
21519	CEFBS_IsThumb_HasAcquireRelease, // t2STL = 4135
21520	CEFBS_IsThumb_HasAcquireRelease, // t2STLB = 4136
21521	CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex, // t2STLEX = 4137
21522	CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex, // t2STLEXB = 4138
21523	CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex_IsNotMClass, // t2STLEXD = 4139
21524	CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex, // t2STLEXH = 4140
21525	CEFBS_IsThumb_HasAcquireRelease, // t2STLH = 4141
21526	CEFBS_IsThumb2, // t2STMDB = 4142
21527	CEFBS_IsThumb2, // t2STMDB_UPD = 4143
21528	CEFBS_IsThumb2, // t2STMIA = 4144
21529	CEFBS_IsThumb2, // t2STMIA_UPD = 4145
21530	CEFBS_IsThumb2, // t2STRBT = 4146
21531	CEFBS_IsThumb2, // t2STRB_POST = 4147
21532	CEFBS_IsThumb2, // t2STRB_PRE = 4148
21533	CEFBS_IsThumb2, // t2STRBi12 = 4149
21534	CEFBS_IsThumb2, // t2STRBi8 = 4150
21535	CEFBS_IsThumb2, // t2STRBs = 4151
21536	CEFBS_IsThumb2, // t2STRD_POST = 4152
21537	CEFBS_IsThumb2, // t2STRD_PRE = 4153
21538	CEFBS_IsThumb2, // t2STRDi8 = 4154
21539	CEFBS_IsThumb_HasV8MBaseline, // t2STREX = 4155
21540	CEFBS_IsThumb_HasV8MBaseline, // t2STREXB = 4156
21541	CEFBS_IsThumb2_IsNotMClass, // t2STREXD = 4157
21542	CEFBS_IsThumb_HasV8MBaseline, // t2STREXH = 4158
21543	CEFBS_IsThumb2, // t2STRHT = 4159
21544	CEFBS_IsThumb2, // t2STRH_POST = 4160
21545	CEFBS_IsThumb2, // t2STRH_PRE = 4161
21546	CEFBS_IsThumb2, // t2STRHi12 = 4162
21547	CEFBS_IsThumb2, // t2STRHi8 = 4163
21548	CEFBS_IsThumb2, // t2STRHs = 4164
21549	CEFBS_IsThumb2, // t2STRT = 4165
21550	CEFBS_IsThumb2, // t2STR_POST = 4166
21551	CEFBS_IsThumb2, // t2STR_PRE = 4167
21552	CEFBS_IsThumb2, // t2STRi12 = 4168
21553	CEFBS_IsThumb2, // t2STRi8 = 4169
21554	CEFBS_IsThumb2, // t2STRs = 4170
21555	CEFBS_IsThumb2_IsNotMClass, // t2SUBS_PC_LR = 4171
21556	CEFBS_IsThumb2, // t2SUBri = 4172
21557	CEFBS_IsThumb2, // t2SUBri12 = 4173
21558	CEFBS_IsThumb2, // t2SUBrr = 4174
21559	CEFBS_IsThumb2, // t2SUBrs = 4175
21560	CEFBS_IsThumb2, // t2SUBspImm = 4176
21561	CEFBS_IsThumb2, // t2SUBspImm12 = 4177
21562	CEFBS_HasDSP_IsThumb2, // t2SXTAB = 4178
21563	CEFBS_HasDSP_IsThumb2, // t2SXTAB16 = 4179
21564	CEFBS_HasDSP_IsThumb2, // t2SXTAH = 4180
21565	CEFBS_IsThumb2, // t2SXTB = 4181
21566	CEFBS_HasDSP_IsThumb2, // t2SXTB16 = 4182
21567	CEFBS_IsThumb2, // t2SXTH = 4183
21568	CEFBS_IsThumb2, // t2TBB = 4184
21569	CEFBS_IsThumb2, // t2TBH = 4185
21570	CEFBS_IsThumb2, // t2TEQri = 4186
21571	CEFBS_IsThumb2, // t2TEQrr = 4187
21572	CEFBS_IsThumb2, // t2TEQrs = 4188
21573	CEFBS_IsThumb_HasV8_4a, // t2TSB = 4189
21574	CEFBS_IsThumb2, // t2TSTri = 4190
21575	CEFBS_IsThumb2, // t2TSTrr = 4191
21576	CEFBS_IsThumb2, // t2TSTrs = 4192
21577	CEFBS_IsThumb_Has8MSecExt, // t2TT = 4193
21578	CEFBS_IsThumb_Has8MSecExt, // t2TTA = 4194
21579	CEFBS_IsThumb_Has8MSecExt, // t2TTAT = 4195
21580	CEFBS_IsThumb_Has8MSecExt, // t2TTT = 4196
21581	CEFBS_IsThumb2_HasDSP, // t2UADD16 = 4197
21582	CEFBS_IsThumb2_HasDSP, // t2UADD8 = 4198
21583	CEFBS_IsThumb2_HasDSP, // t2UASX = 4199
21584	CEFBS_IsThumb2, // t2UBFX = 4200
21585	CEFBS_IsThumb2, // t2UDF = 4201
21586	CEFBS_HasDivideInThumb_IsThumb_HasV8MBaseline, // t2UDIV = 4202
21587	CEFBS_IsThumb2_HasDSP, // t2UHADD16 = 4203
21588	CEFBS_IsThumb2_HasDSP, // t2UHADD8 = 4204
21589	CEFBS_IsThumb2_HasDSP, // t2UHASX = 4205
21590	CEFBS_IsThumb2_HasDSP, // t2UHSAX = 4206
21591	CEFBS_IsThumb2_HasDSP, // t2UHSUB16 = 4207
21592	CEFBS_IsThumb2_HasDSP, // t2UHSUB8 = 4208
21593	CEFBS_IsThumb2_HasDSP, // t2UMAAL = 4209
21594	CEFBS_IsThumb2, // t2UMLAL = 4210
21595	CEFBS_IsThumb2, // t2UMULL = 4211
21596	CEFBS_IsThumb2_HasDSP, // t2UQADD16 = 4212
21597	CEFBS_IsThumb2_HasDSP, // t2UQADD8 = 4213
21598	CEFBS_IsThumb2_HasDSP, // t2UQASX = 4214
21599	CEFBS_IsThumb2_HasDSP, // t2UQSAX = 4215
21600	CEFBS_IsThumb2_HasDSP, // t2UQSUB16 = 4216
21601	CEFBS_IsThumb2_HasDSP, // t2UQSUB8 = 4217
21602	CEFBS_IsThumb2_HasDSP, // t2USAD8 = 4218
21603	CEFBS_IsThumb2_HasDSP, // t2USADA8 = 4219
21604	CEFBS_IsThumb2, // t2USAT = 4220
21605	CEFBS_IsThumb2_HasDSP, // t2USAT16 = 4221
21606	CEFBS_IsThumb2_HasDSP, // t2USAX = 4222
21607	CEFBS_IsThumb2_HasDSP, // t2USUB16 = 4223
21608	CEFBS_IsThumb2_HasDSP, // t2USUB8 = 4224
21609	CEFBS_HasDSP_IsThumb2, // t2UXTAB = 4225
21610	CEFBS_HasDSP_IsThumb2, // t2UXTAB16 = 4226
21611	CEFBS_HasDSP_IsThumb2, // t2UXTAH = 4227
21612	CEFBS_IsThumb2, // t2UXTB = 4228
21613	CEFBS_HasDSP_IsThumb2, // t2UXTB16 = 4229
21614	CEFBS_IsThumb2, // t2UXTH = 4230
21615	CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2WLS = 4231
21616	CEFBS_IsThumb, // tADC = 4232
21617	CEFBS_IsThumb, // tADDhirr = 4233
21618	CEFBS_IsThumb, // tADDi3 = 4234
21619	CEFBS_IsThumb, // tADDi8 = 4235
21620	CEFBS_IsThumb, // tADDrSP = 4236
21621	CEFBS_IsThumb, // tADDrSPi = 4237
21622	CEFBS_IsThumb, // tADDrr = 4238
21623	CEFBS_IsThumb, // tADDspi = 4239
21624	CEFBS_IsThumb, // tADDspr = 4240
21625	CEFBS_IsThumb, // tADR = 4241
21626	CEFBS_IsThumb, // tAND = 4242
21627	CEFBS_IsThumb, // tASRri = 4243
21628	CEFBS_IsThumb, // tASRrr = 4244
21629	CEFBS_IsThumb, // tB = 4245
21630	CEFBS_IsThumb, // tBIC = 4246
21631	CEFBS_IsThumb, // tBKPT = 4247
21632	CEFBS_IsThumb, // tBL = 4248
21633	CEFBS_IsThumb_Has8MSecExt, // tBLXNSr = 4249
21634	CEFBS_IsThumb_HasV5T_IsNotMClass, // tBLXi = 4250
21635	CEFBS_IsThumb_HasV5T, // tBLXr = 4251
21636	CEFBS_IsThumb, // tBX = 4252
21637	CEFBS_IsThumb_Has8MSecExt, // tBXNS = 4253
21638	CEFBS_IsThumb, // tBcc = 4254
21639	CEFBS_IsThumb_HasV8MBaseline, // tCBNZ = 4255
21640	CEFBS_IsThumb_HasV8MBaseline, // tCBZ = 4256
21641	CEFBS_IsThumb, // tCMNz = 4257
21642	CEFBS_IsThumb, // tCMPhir = 4258
21643	CEFBS_IsThumb, // tCMPi8 = 4259
21644	CEFBS_IsThumb, // tCMPr = 4260
21645	CEFBS_IsThumb, // tCPS = 4261
21646	CEFBS_IsThumb, // tEOR = 4262
21647	CEFBS_IsThumb_HasV6M, // tHINT = 4263
21648	CEFBS_IsThumb_HasV8, // tHLT = 4264
21649	CEFBS_IsThumb, // tInt_WIN_eh_sjlj_longjmp = 4265
21650	CEFBS_IsThumb, // tInt_eh_sjlj_longjmp = 4266
21651	CEFBS_IsThumb, // tInt_eh_sjlj_setjmp = 4267
21652	CEFBS_IsThumb, // tLDMIA = 4268
21653	CEFBS_IsThumb, // tLDRBi = 4269
21654	CEFBS_IsThumb, // tLDRBr = 4270
21655	CEFBS_IsThumb, // tLDRHi = 4271
21656	CEFBS_IsThumb, // tLDRHr = 4272
21657	CEFBS_IsThumb, // tLDRSB = 4273
21658	CEFBS_IsThumb, // tLDRSH = 4274
21659	CEFBS_IsThumb, // tLDRi = 4275
21660	CEFBS_IsThumb, // tLDRpci = 4276
21661	CEFBS_IsThumb, // tLDRr = 4277
21662	CEFBS_IsThumb, // tLDRspi = 4278
21663	CEFBS_IsThumb, // tLSLri = 4279
21664	CEFBS_IsThumb, // tLSLrr = 4280
21665	CEFBS_IsThumb, // tLSRri = 4281
21666	CEFBS_IsThumb, // tLSRrr = 4282
21667	CEFBS_IsThumb, // tMOVSr = 4283
21668	CEFBS_IsThumb, // tMOVi8 = 4284
21669	CEFBS_IsThumb, // tMOVr = 4285
21670	CEFBS_IsThumb, // tMUL = 4286
21671	CEFBS_IsThumb, // tMVN = 4287
21672	CEFBS_IsThumb, // tORR = 4288
21673	CEFBS_IsThumb, // tPICADD = 4289
21674	CEFBS_IsThumb, // tPOP = 4290
21675	CEFBS_IsThumb, // tPUSH = 4291
21676	CEFBS_IsThumb_HasV6, // tREV = 4292
21677	CEFBS_IsThumb_HasV6, // tREV16 = 4293
21678	CEFBS_IsThumb_HasV6, // tREVSH = 4294
21679	CEFBS_IsThumb, // tROR = 4295
21680	CEFBS_IsThumb, // tRSB = 4296
21681	CEFBS_IsThumb, // tSBC = 4297
21682	CEFBS_IsThumb_IsNotMClass, // tSETEND = 4298
21683	CEFBS_IsThumb, // tSTMIA_UPD = 4299
21684	CEFBS_IsThumb, // tSTRBi = 4300
21685	CEFBS_IsThumb, // tSTRBr = 4301
21686	CEFBS_IsThumb, // tSTRHi = 4302
21687	CEFBS_IsThumb, // tSTRHr = 4303
21688	CEFBS_IsThumb, // tSTRi = 4304
21689	CEFBS_IsThumb, // tSTRr = 4305
21690	CEFBS_IsThumb, // tSTRspi = 4306
21691	CEFBS_IsThumb, // tSUBi3 = 4307
21692	CEFBS_IsThumb, // tSUBi8 = 4308
21693	CEFBS_IsThumb, // tSUBrr = 4309
21694	CEFBS_IsThumb, // tSUBspi = 4310
21695	CEFBS_IsThumb, // tSVC = 4311
21696	CEFBS_IsThumb_HasV6, // tSXTB = 4312
21697	CEFBS_IsThumb_HasV6, // tSXTH = 4313
21698	CEFBS_IsThumb, // tTRAP = 4314
21699	CEFBS_IsThumb, // tTST = 4315
21700	CEFBS_IsThumb, // tUDF = 4316
21701	CEFBS_IsThumb_HasV6, // tUXTB = 4317
21702	CEFBS_IsThumb_HasV6, // tUXTH = 4318
21703	CEFBS_IsThumb, // t__brkdiv0 = 4319
21704	};
21705
21706	assert(Inst.getOpcode() < `4320`);
21707	const FeatureBitset &RequiredFeatures = FeatureBitsets[RequiredFeaturesRefs[Inst.getOpcode()]];
21708	FeatureBitset MissingFeatures =
21709	(AvailableFeatures & RequiredFeatures) ^
21710	RequiredFeatures;
21711	if (MissingFeatures.any()) {
21712	std::ostringstream Msg;
21713	Msg << "Attempting to emit " << MCII.getName(Inst.getOpcode()).str()
21714	<< " instruction but the ";
21715	for (unsigned i = `0`, e = MissingFeatures.size(); i != e; ++i)
21716	if (MissingFeatures.test(i))
21717	Msg << SubtargetFeatureNames[i] << " ";
21718	Msg << "predicate(s) are not met";
21719	report_fatal_error(Msg.str());
21720	}
21721	#else
21722	// Silence unused variable warning on targets that don't use MCII for other purposes (e.g. BPF).
21723	(void)MCII;
21724	#endif // NDEBUG
21725	}
21726	#endif
21727

Browse the source code of llvm/build/lib/Target/ARM/ARMGenMCCodeEmitter.inc